From: kernel test robot <lkp@intel.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: kbuild-all@lists.01.org, linux-kernel@vger.kernel.org
Subject: arch/arm/mach-mmp/pm-pxa910.c:132:6: warning: no previous prototype for 'pxa910_pm_enter_lowpower_mode'
Date: Thu, 22 Sep 2022 11:15:14 +0800 [thread overview]
Message-ID: <202209221119.rhKR3xdI-lkp@intel.com> (raw)
Hi Arnd,
First bad commit (maybe != root cause):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: dc164f4fb00a0abebdfff132f8bc7291a28f5401
commit: a3102fafdce6f150e5a46e1725bb1732f8953a01 ARM: iop32x: enable multiplatform support
date: 6 months ago
config: arm-randconfig-r036-20220921 (https://download.01.org/0day-ci/archive/20220922/202209221119.rhKR3xdI-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a3102fafdce6f150e5a46e1725bb1732f8953a01
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout a3102fafdce6f150e5a46e1725bb1732f8953a01
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> arch/arm/mach-mmp/pm-pxa910.c:132:6: warning: no previous prototype for 'pxa910_pm_enter_lowpower_mode' [-Wmissing-prototypes]
132 | void pxa910_pm_enter_lowpower_mode(int state)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/pxa910_pm_enter_lowpower_mode +132 arch/arm/mach-mmp/pm-pxa910.c
902ca2297180fe Chao Xie 2012-05-07 131
902ca2297180fe Chao Xie 2012-05-07 @132 void pxa910_pm_enter_lowpower_mode(int state)
902ca2297180fe Chao Xie 2012-05-07 133 {
902ca2297180fe Chao Xie 2012-05-07 134 uint32_t idle_cfg, apcr;
902ca2297180fe Chao Xie 2012-05-07 135
902ca2297180fe Chao Xie 2012-05-07 136 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
902ca2297180fe Chao Xie 2012-05-07 137 apcr = __raw_readl(MPMU_APCR);
902ca2297180fe Chao Xie 2012-05-07 138
902ca2297180fe Chao Xie 2012-05-07 139 apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD
902ca2297180fe Chao Xie 2012-05-07 140 | MPMU_APCR_VCTCXOSD | MPMU_APCR_STBYEN);
902ca2297180fe Chao Xie 2012-05-07 141 idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_IDLE
902ca2297180fe Chao Xie 2012-05-07 142 | APMU_MOH_IDLE_CFG_MOH_PWRDWN);
902ca2297180fe Chao Xie 2012-05-07 143
902ca2297180fe Chao Xie 2012-05-07 144 switch (state) {
902ca2297180fe Chao Xie 2012-05-07 145 case POWER_MODE_UDR:
902ca2297180fe Chao Xie 2012-05-07 146 /* only shutdown APB in UDR */
902ca2297180fe Chao Xie 2012-05-07 147 apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
df561f6688fef7 Gustavo A. R. Silva 2020-08-23 148 fallthrough;
902ca2297180fe Chao Xie 2012-05-07 149 case POWER_MODE_SYS_SLEEP:
902ca2297180fe Chao Xie 2012-05-07 150 apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */
902ca2297180fe Chao Xie 2012-05-07 151 apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */
df561f6688fef7 Gustavo A. R. Silva 2020-08-23 152 fallthrough;
902ca2297180fe Chao Xie 2012-05-07 153 case POWER_MODE_APPS_SLEEP:
902ca2297180fe Chao Xie 2012-05-07 154 apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */
df561f6688fef7 Gustavo A. R. Silva 2020-08-23 155 fallthrough;
902ca2297180fe Chao Xie 2012-05-07 156 case POWER_MODE_APPS_IDLE:
902ca2297180fe Chao Xie 2012-05-07 157 apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */
df561f6688fef7 Gustavo A. R. Silva 2020-08-23 158 fallthrough;
902ca2297180fe Chao Xie 2012-05-07 159 case POWER_MODE_CORE_EXTIDLE:
902ca2297180fe Chao Xie 2012-05-07 160 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
902ca2297180fe Chao Xie 2012-05-07 161 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
902ca2297180fe Chao Xie 2012-05-07 162 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
902ca2297180fe Chao Xie 2012-05-07 163 | APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
df561f6688fef7 Gustavo A. R. Silva 2020-08-23 164 fallthrough;
902ca2297180fe Chao Xie 2012-05-07 165 case POWER_MODE_CORE_INTIDLE:
902ca2297180fe Chao Xie 2012-05-07 166 break;
902ca2297180fe Chao Xie 2012-05-07 167 }
902ca2297180fe Chao Xie 2012-05-07 168
902ca2297180fe Chao Xie 2012-05-07 169 /* program the memory controller hardware sleep type and auto wakeup */
902ca2297180fe Chao Xie 2012-05-07 170 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ;
902ca2297180fe Chao Xie 2012-05-07 171 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN;
902ca2297180fe Chao Xie 2012-05-07 172 __raw_writel(0x0, APMU_MC_HW_SLP_TYPE); /* auto refresh */
902ca2297180fe Chao Xie 2012-05-07 173
902ca2297180fe Chao Xie 2012-05-07 174 /* set DSPSD, DTCMSD, BBSD, MSASLPEN */
902ca2297180fe Chao Xie 2012-05-07 175 apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD
902ca2297180fe Chao Xie 2012-05-07 176 | MPMU_APCR_MSASLPEN;
902ca2297180fe Chao Xie 2012-05-07 177
902ca2297180fe Chao Xie 2012-05-07 178 /*always set SLEPEN bit mainly for MSA*/
902ca2297180fe Chao Xie 2012-05-07 179 apcr |= MPMU_APCR_SLPEN;
902ca2297180fe Chao Xie 2012-05-07 180
902ca2297180fe Chao Xie 2012-05-07 181 /* finally write the registers back */
902ca2297180fe Chao Xie 2012-05-07 182 __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
902ca2297180fe Chao Xie 2012-05-07 183 __raw_writel(apcr, MPMU_APCR);
902ca2297180fe Chao Xie 2012-05-07 184
:::::: The code at line 132 was first introduced by commit
:::::: 902ca2297180fe97f840427c114cc6dc7e77375e ARM: mmp: add pm support for pxa910
:::::: TO: Chao Xie <chao.xie@marvell.com>
:::::: CC: Haojian Zhuang <haojian.zhuang@gmail.com>
--
0-DAY CI Kernel Test Service
https://01.org/lkp
next reply other threads:[~2022-09-22 3:22 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 3:15 kernel test robot [this message]
2022-10-20 5:37 kernel test robot
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