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From: Conor Dooley <conor.dooley@microchip.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Shravan Chippa <shravan.chippa@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Cyril Jean <Cyril.Jean@microchip.com>,
	Lewis Hanly <lewis.hanly@microchip.com>,
	Vattipalli Praveen <praveen.kumar@microchip.com>,
	Wolfgang Grandegger <wg@aries-embedded.de>,
	Hugh Breslin <hugh.breslin@microchip.com>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v6 06/11] riscv: dts: microchip: icicle: update pci address properties
Date: Tue, 27 Sep 2022 12:19:18 +0100	[thread overview]
Message-ID: <20220927111922.3602838-7-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com>

For the v2022.09 reference design the PCI root port's data region has
been moved to FIC1 from FIC0. This is a shorter path, allowing for
higher clock rates and improved through-put. As a result, the address at
which the PCIe's data region appears to the core complex has changed.
The config region's address is unchanged.

As FIC0 is no longer used, its clock can be removed too.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi     | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 688ef0fc5a64..9ca2ac4ad8e2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -38,13 +38,13 @@ fabric_clk1: fabric-clk1 {
 		clock-frequency = <125000000>;
 	};
 
-	pcie: pcie@2000000000 {
+	pcie: pcie@3000000000 {
 		compatible = "microchip,pcie-host-1.0";
 		#address-cells = <0x3>;
 		#interrupt-cells = <0x1>;
 		#size-cells = <0x2>;
 		device_type = "pci";
-		reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+		reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
 		reg-names = "cfg", "apb";
 		bus-range = <0x0 0x7f>;
 		interrupt-parent = <&plic>;
@@ -54,9 +54,9 @@ pcie: pcie@2000000000 {
 				<0 0 0 3 &pcie_intc 2>,
 				<0 0 0 4 &pcie_intc 3>;
 		interrupt-map-mask = <0 0 0 7>;
-		clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
-		clock-names = "fic0", "fic1", "fic3";
-		ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+		clocks = <&fabric_clk1>, <&fabric_clk3>;
+		clock-names = "fic1", "fic3";
+		ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
 		dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
 		msi-parent = <&pcie>;
 		msi-controller;
-- 
2.37.3


  parent reply	other threads:[~2022-09-27 11:21 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-27 11:19 ` [PATCH v6 01/11] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-09-27 11:19 ` [PATCH v6 02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
2022-09-27 11:19 ` [PATCH v6 03/11] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
2022-09-27 11:19 ` [PATCH v6 04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
2022-09-27 11:19 ` [PATCH v6 05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
2022-09-27 11:19 ` Conor Dooley [this message]
2022-09-27 11:19 ` [PATCH v6 07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
2022-09-27 11:19 ` [PATCH v6 08/11] riscv: dts: microchip: reduce the fic3 clock rate Conor Dooley
2022-09-27 11:19 ` [PATCH v6 09/11] riscv: dts: microchip: add sevkit device tree Conor Dooley
2022-09-27 11:19 ` [PATCH v6 10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
2022-09-27 11:19 ` [PATCH v6 11/11] riscv: dts: microchip: update memory configuration for v2022.10 Conor Dooley
2022-09-27 11:22 ` [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-27 18:33 ` Conor Dooley

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