From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFC0AC433FE for ; Fri, 30 Sep 2022 05:13:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230519AbiI3FNd (ORCPT ); Fri, 30 Sep 2022 01:13:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230323AbiI3FNM (ORCPT ); Fri, 30 Sep 2022 01:13:12 -0400 Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C66081664A5; Thu, 29 Sep 2022 22:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=mY3EDY/vx2Uownaii2/cI7b2LqzoukIIBmBHq6JBVYo=; b=vI7ufF45c2ZujmarwO4fpkI6J2 zpap5xxdpN2CfStNw3GQuwwLUMY7+frxpSNCvZNT5Qohrdp0v7cBWBW3BC58l3T/LTiiCEZq8+vnS dpcdzs4zdlpAqtijXKAbgSeF9L5FTMMB1eTq/hrGQkHDi9p2paxiA5z9YtlgBihCSv3gM6r564kAM KAlWZwIM9iL46vpgr6WaGJ3yj8AsV5J6F810n1zwlLfjrfwiCzqT0+E+ONHbk1oPCAgd0pK8CJY42 mVrdLb2AywwY5LtrVenjdPtcx5l3/CKscryDf+HhVjz9Wf14RrGOCV+enQGDsydjk61WXWCjERCAK qIvNMIDQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oe8Ke-00Djew-2p; Fri, 30 Sep 2022 07:13:04 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1oe8Kd-001dv6-1V; Fri, 30 Sep 2022 07:13:03 +0200 From: Aurelien Jarno To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Dongjin Kim , Aurelien Jarno , Dan Johansen Subject: [PATCH v3 06/13] arm64: dts: rockchip: Enable vop2 and hdmi tx on ODROID-M1 Date: Fri, 30 Sep 2022 07:12:39 +0200 Message-Id: <20220930051246.391614-7-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930051246.391614-1-aurelien@aurel32.net> References: <20220930051246.391614-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the RK356x Video Output Processor (VOP) 2 on ODROID M1. Signed-off-by: Aurelien Jarno Tested-by: Dan Johansen --- .../boot/dts/rockchip/rk3568-odroid-m1.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts index 634c1bd80b4e..126b893048fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -8,6 +8,7 @@ #include #include #include +#include #include "rk3568.dtsi" / { @@ -37,6 +38,17 @@ dc_12v: dc-12v-regulator { regulator-max-microvolt = <12000000>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -131,6 +143,24 @@ &gmac0_rgmii_clk rx_delay = <0x2d>; }; +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; @@ -517,3 +547,20 @@ &tsadc { &uart2 { status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; -- 2.35.1