From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD2BCC433F5 for ; Sun, 2 Oct 2022 22:53:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230197AbiJBWxF (ORCPT ); Sun, 2 Oct 2022 18:53:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230001AbiJBWwX (ORCPT ); Sun, 2 Oct 2022 18:52:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 480793AE4A; Sun, 2 Oct 2022 15:50:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D36ED60F13; Sun, 2 Oct 2022 22:50:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31251C433D6; Sun, 2 Oct 2022 22:50:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664751044; bh=qBwQs3ScO9mSEiaUzW1hR+6DZafv70x1M0qGHdT/LRw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j+pXqSHwZsZCVCS+0zIYtUYg5YCsmhuT7hUmof8hC+/QwaJbGnD4/bBu+VosM99F+ 5i76S9ldgJOD8EkOfKkE9wwS5DKarPJ90t98CPrOyl2UCnNFT1paWTTd1J2DVfnEsX /6bJnimKTGLFDX2VT/uiYk9y+rFCNVKHR9aKv4aelkG3Gm3Hh3FguEzidgFIm78pTU Rtegip1/08eI6Mwjhqep2XPHkMwNow0brXOKclm4Pij/i5DtJTgttougIAzpBKYVaV TnKmUC9xSQUKqt0w31Yu7r41JPhqEYK5PvqvSivx8f99y3K9E6PwJDHDPwz5lZJXwU DEJFZMX0+nzGA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Cruise Hung , Jun Lei , Wayne Lin , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, wenjing.liu@amd.com, george.shen@amd.com, Jimmy.Kizito@amd.com, michael.strauss@amd.com, mikita.lipski@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.19 27/29] drm/amd/display: Fix DP MST timeslot issue when fallback happened Date: Sun, 2 Oct 2022 18:49:20 -0400 Message-Id: <20221002224922.238837-27-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221002224922.238837-1-sashal@kernel.org> References: <20221002224922.238837-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Cruise Hung [ Upstream commit 20c6168b3c8aadef7d2853c925d99eb546bd5e1c ] [Why] When USB4 DP link training failed and fell back to lower link rate, the time slot calculation uses the verified_link_cap. And the verified_link_cap was not updated to the new one. It caused the wrong VC payload time-slot was allocated. [How] Updated verified_link_cap with the new one from cur_link_settings after the LT completes successfully. Reviewed-by: Jun Lei Acked-by: Wayne Lin Signed-off-by: Cruise Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 0c52506b367d..b4203a812c4b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2857,8 +2857,14 @@ bool perform_link_training_with_retries( skip_video_pattern); /* Transmit idle pattern once training successful. */ - if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) + if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) { dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); + /* Update verified link settings to current one + * Because DPIA LT might fallback to lower link setting. + */ + link->verified_link_cap.link_rate = link->cur_link_settings.link_rate; + link->verified_link_cap.lane_count = link->cur_link_settings.lane_count; + } } else { status = dc_link_dp_perform_link_training(link, &pipe_ctx->link_res, -- 2.35.1