From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com,
avagin@gmail.com, seanjc@google.com, chang.seok.bae@intel.com
Subject: [PATCH v3 3/3] x86/fpu: Correct the legacy state offset and size information
Date: Wed, 5 Oct 2022 14:53:57 -0700 [thread overview]
Message-ID: <20221005215357.1808-4-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20221005215357.1808-1-chang.seok.bae@intel.com>
MXCSR is architecturally part of the SSE state. But, the kernel code
presumes it as part of the FP component. Adjust the offset and size for
these legacy states.
Notably, each legacy component area is not contiguous, unlike extended
components. Add a WARNING to be emitted when the location of those
legacy states is queried.
Fixes: ac73b27aea4e ("x86/fpu/xstate: Fix xstate_offsets, xstate_sizes for non-extended xstates")
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
---
Changes from v2:
* Replace pr_warn() with WARN_ON_ONCE() (Sean Christopherson).
* Massage the code comment (Sean Christopherson).
---
arch/x86/kernel/fpu/xstate.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index d7676cfc32eb..252a54807f0c 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -140,10 +140,11 @@ static unsigned int xfeature_get_offset(u64 xcomp_bv, int xfeature)
/*
* Non-compacted format and legacy features use the cached fixed
- * offsets.
+ * offsets. N.B. Each legacy state is discontiguously located in
+ * memory.
*/
if (!cpu_feature_enabled(X86_FEATURE_XCOMPACTED) ||
- xfeature <= XFEATURE_SSE)
+ WARN_ON_ONCE(xfeature <= XFEATURE_SSE))
return xstate_offsets[xfeature];
/*
@@ -217,14 +218,18 @@ static void __init setup_xstate_cache(void)
* The FP xstates and SSE xstates are legacy states. They are always
* in the fixed offsets in the xsave area in either compacted form
* or standard form.
+ *
+ * But, while MXCSR is part of the SSE state, it is located in
+ * between the FP states. Note that it is erroneous assuming that
+ * each legacy area is contiguous.
*/
xstate_offsets[XFEATURE_FP] = 0;
- xstate_sizes[XFEATURE_FP] = offsetof(struct fxregs_state,
- xmm_space);
+ xstate_sizes[XFEATURE_FP] = offsetof(struct fxregs_state, mxcsr) +
+ sizeof_field(struct fxregs_state, st_space);
- xstate_offsets[XFEATURE_SSE] = xstate_sizes[XFEATURE_FP];
- xstate_sizes[XFEATURE_SSE] = sizeof_field(struct fxregs_state,
- xmm_space);
+ xstate_offsets[XFEATURE_SSE] = offsetof(struct fxregs_state, mxcsr);
+ xstate_sizes[XFEATURE_SSE] = MXCSR_AND_FLAGS_SIZE +
+ sizeof_field(struct fxregs_state, xmm_space);
for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
--
2.17.1
prev parent reply other threads:[~2022-10-05 22:04 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 21:53 [PATCH v3 0/3] x86/fpu: Fix MXCSR handling and SSE component definition Chang S. Bae
2022-10-05 21:53 ` [PATCH v3 1/3] x86/fpu: Fix the MXCSR state reshuffling between userspace and kernel buffers Chang S. Bae
2022-10-05 21:53 ` [PATCH v3 2/3] selftests/x86/mxcsr: Test the MXCSR state write via ptrace Chang S. Bae
2022-10-05 21:53 ` Chang S. Bae [this message]
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