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[31.30.173.61]) by smtp.gmail.com with ESMTPSA id i26-20020a50fc1a000000b00458e73fe1c1sm5802996edr.8.2022.10.06.06.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 06:15:29 -0700 (PDT) Date: Thu, 6 Oct 2022 15:15:28 +0200 From: Andrew Jones To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Message-ID: <20221006131528.ovcvgnp4tdkfcnb7@kamzik> References: <20221006070818.3616-1-jszhang@kernel.org> <20221006070818.3616-4-jszhang@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221006070818.3616-4-jszhang@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 06, 2022 at 03:08:13PM +0800, Jisheng Zhang wrote: > We will make use of ISA extension in asm files, so make the multi-letter > RISC-V ISA extension IDs macros rather than enums and move them and > those base ISA extension IDs to suitable place. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/hwcap.h | 45 +++++++++++++++++----------------- > 1 file changed, 23 insertions(+), 22 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 6f59ec64175e..6cf445653911 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -12,20 +12,6 @@ > #include > #include > > -#ifndef __ASSEMBLY__ > -#include > -/* > - * This yields a mask that user programs can use to figure out what > - * instruction set this cpu supports. > - */ > -#define ELF_HWCAP (elf_hwcap) > - > -enum { > - CAP_HWCAP = 1, > -}; > - > -extern unsigned long elf_hwcap; > - > #define RISCV_ISA_EXT_a ('a' - 'a') > #define RISCV_ISA_EXT_c ('c' - 'a') > #define RISCV_ISA_EXT_d ('d' - 'a') > @@ -46,21 +32,36 @@ extern unsigned long elf_hwcap; > #define RISCV_ISA_EXT_BASE 26 > > /* > - * This enum represent the logical ID for each multi-letter RISC-V ISA extension. > + * These macros represent the logical ID for each multi-letter RISC-V ISA extension. > * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed > * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter > * extensions while all the multi-letter extensions should define the next > * available logical extension id. > */ > -enum riscv_isa_ext_id { > - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > - RISCV_ISA_EXT_SVPBMT, > - RISCV_ISA_EXT_ZICBOM, > - RISCV_ISA_EXT_ZIHINTPAUSE, > - RISCV_ISA_EXT_SSTC, > - RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > +#define RISCV_ISA_EXT_SSCOFPMF 26 > +#define RISCV_ISA_EXT_SVPBMT 27 > +#define RISCV_ISA_EXT_ZICBOM 28 > +#define RISCV_ISA_EXT_ZIHINTPAUSE 29 > +#define RISCV_ISA_EXT_SSTC 30 > + > +#define RISCV_ISA_EXT_ID_MAX RISCV_ISA_EXT_MAX afaict, RISCV_ISA_EXT_ID_MAX is ununsed and can be removed. > + > + > +#ifndef __ASSEMBLY__ > +#include > +/* > + * This yields a mask that user programs can use to figure out what > + * instruction set this cpu supports. > + */ > +#define ELF_HWCAP (elf_hwcap) > + > +enum { > + CAP_HWCAP = 1, > }; > > +extern unsigned long elf_hwcap; > + > + > /* > * This enum represents the logical ID for each RISC-V ISA extension static > * keys. We can use static key to optimize code path if some ISA extensions > -- > 2.37.2 > Otherwise, Reviewed-by: Andrew Jones