From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19047C433FE for ; Thu, 6 Oct 2022 13:37:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229726AbiJFNhC (ORCPT ); Thu, 6 Oct 2022 09:37:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230418AbiJFNhA (ORCPT ); Thu, 6 Oct 2022 09:37:00 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48F19AA3F4 for ; Thu, 6 Oct 2022 06:36:59 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id a13so2905381edj.0 for ; Thu, 06 Oct 2022 06:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date; bh=DZoJlUHmQo7sC5JniZgyDQJ0wSD+jVGoLhaBhI1aGrY=; b=VrDqkwCw5gUn3mEQeJpu9dZ6AF1IXGZyviXwZK0a0SBl8C3saY78DBhb/NdOBGw77D sioORUtf+ZoAvGawjjvFeAr50qIikDof/HLUpqsqTrCtVa84hHZkd/E0dpQmOvJmsCKg qZ9OMEmE/hBTKMJW/rXB9LjDUvMy45qOBk1xsAcIxkP1o1SOlIqrt5LYHaxORiElDwe4 R9MZ0qz9U5yOptdEaPV/ZihLWb3ludMoViQRvpsVTZslK6Hu73ZRKH1EXmP8DwyIesF7 oz8lu2coaNvI6Sl0AoAymj5KIn4GobvoY9tgws3Nwugy4Wj5zSaaSmR9MocBH/bPBHRk J+rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date; bh=DZoJlUHmQo7sC5JniZgyDQJ0wSD+jVGoLhaBhI1aGrY=; b=L6pIea6oIwvQ7X+TGoUCFC8Uwx9ow4iYkIWbXvZPntuIL+aKDjcAh9pOiBHOPVWxkP 1t/AOrTSm9h784Nu2cWntWb+nehXheMagVjW5YTxjxKSeRXC+sM/MuzvH9wrasPpG39L y9ftcpdAfYSjTxL6tjdgPbZ4XSIiy+uEM2X5QlztphYi3VG7b3dM0T2iqMDJcWFzpT5o zf9UuXZ2Oa3vF2EE7654XmOWD4UEyZUPO+dzUm/LR2wS9d0Pw7XhxtDMCkkzbsRvru6O g1efTSoopz3dOYvqCw5cUyVT5xGTk7otyKRinxf3z2RfZ/5qMxNCJ56jBsvzSOT5sSAA sTZg== X-Gm-Message-State: ACrzQf0JRoTzQvADK79YtNUFFlKGkGX8xINbqfSZ/lo1pFv67KglqgwY +FLlTD+xll2fGaFBTYsN6lrI7A== X-Google-Smtp-Source: AMsMyM4nMOW1IAKp6SZkiuHt6/NehY++eUad8HKnZasoygesNi8fvEa5ilT/pi5mdZrAC6xvW9K3kQ== X-Received: by 2002:a05:6402:428c:b0:440:8259:7a2b with SMTP id g12-20020a056402428c00b0044082597a2bmr4549032edc.329.1665063417836; Thu, 06 Oct 2022 06:36:57 -0700 (PDT) Received: from localhost (cst2-173-61.cust.vodafone.cz. [31.30.173.61]) by smtp.gmail.com with ESMTPSA id e24-20020a17090681d800b0078246b1360csm10146351ejx.225.2022.10.06.06.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 06:36:57 -0700 (PDT) Date: Thu, 6 Oct 2022 15:36:56 +0200 From: Andrew Jones To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Message-ID: <20221006133656.sdtxrpopvmy6b5mw@kamzik> References: <20221006070818.3616-1-jszhang@kernel.org> <20221006070818.3616-7-jszhang@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221006070818.3616-7-jszhang@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 06, 2022 at 03:08:16PM +0800, Jisheng Zhang wrote: > Switch has_fpu() from statich branch to the new helper > riscv_has_extension_likely(). > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/switch_to.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h > index 11463489fec6..60f8ca01d36e 100644 > --- a/arch/riscv/include/asm/switch_to.h > +++ b/arch/riscv/include/asm/switch_to.h > @@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *prev, > > static __always_inline bool has_fpu(void) > { > - return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]); > + return riscv_has_extension_likely(RISCV_ISA_EXT_f) || > + riscv_has_extension_likely(RISCV_ISA_EXT_d); > } > #else > static __always_inline bool has_fpu(void) { return false; } > -- > 2.37.2 > Reviewed-by: Andrew Jones