From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D267C433F5 for ; Thu, 6 Oct 2022 16:03:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232007AbiJFQDv (ORCPT ); Thu, 6 Oct 2022 12:03:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232008AbiJFQDq (ORCPT ); Thu, 6 Oct 2022 12:03:46 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5B51AE200 for ; Thu, 6 Oct 2022 09:03:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665072224; x=1696608224; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=KPZR+Xpk+WcMi2zviZBQO4WTHIOesHRnYBlHUZR//zQ=; b=fd2Qn1nofYmeP9kJM+K6fNoVTagd5GDyRN7K+9+Djj0iF3uZxdscT+EM YGCaF8+eLmHVK/Plez/pd6pmRIwdTdrOyuFgYJ6I0larDXA27o0W73PuO 1/AdPN0xszYsrNHxD8VnZ6DnIqZlYQd0qSWc4Z8zAVZrz1DzTqnTZoOpv q51vXuzM20cIrsUcD4m5khh4Qut4FWkucMxbf+R7tsJjGuoOhp4mX9Zwu 1/EOm5eEtHFMCwr43dMOhT3b2CSWSdLuTBR2QqlfK6V0h88YT6wup+O3+ KcDuwrE/CnuSq+PGKQ4VLvR6NNgngebYrtpcDLKNGj5YAobO/xAIPSW74 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10492"; a="304480694" X-IronPort-AV: E=Sophos;i="5.95,164,1661842800"; d="scan'208";a="304480694" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2022 09:02:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="687486223" X-IronPort-AV: E=Sophos;i="5.95,164,1661842800"; d="scan'208";a="687486223" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 06 Oct 2022 09:02:35 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com Subject: [PATCH 0/6] Enable LKGS instruction Date: Thu, 6 Oct 2022 08:40:35 -0700 Message-Id: <20221006154041.13001-1-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specification https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS is independent of FRED, so we enable it as a standalone CPU feature. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache, which is exactly what Linux kernel does to load user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. H. Peter Anvin (Intel) (6): x86/cpufeature: add cpu feature bit for LKGS x86/opcode: add LKGS instruction to x86-opcode-map x86/gsseg: make asm_load_gs_index() take an u16 x86/gsseg: move local_irq_save/restore() into asm_load_gs_index() x86/gsseg: move load_gs_index() to its own header file x86/gsseg: use the LKGS instruction if available for load_gs_index() arch/x86/entry/entry_64.S | 28 +++++++++--- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/gsseg.h | 58 ++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 21 --------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 11 files changed, 88 insertions(+), 27 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h -- 2.34.1