From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06FDEC433FE for ; Mon, 17 Oct 2022 22:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230345AbiJQWaF (ORCPT ); Mon, 17 Oct 2022 18:30:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230053AbiJQW3w (ORCPT ); Mon, 17 Oct 2022 18:29:52 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C13FDF29; Mon, 17 Oct 2022 15:29:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0C9F3B81B36; Mon, 17 Oct 2022 22:29:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1D51C433D7; Mon, 17 Oct 2022 22:29:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666045749; bh=k7MLUjceCFWiLok658ldq37/tAw0aML4ER0Pm1Q0SNg=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=ZIv+zDO258AM0sK3Ogqd/emWlIJ9ZHxWfWfUAy4IDvPQZFzAI5tsmxWsPS/Rhz8lj HMu3oxZaic5Z/2g6tpoLKw7ou+2DafNTHkODlZSZgDRe3b75OkPiMyRwmbybq7TKA5 NM8yZfhqZX3R7v/XCaFRQBxd51U0xVX734abys+wAVccL2ic1Q0wVs6t7Ebe3oMFKc ilqIPLtbBY8Lxl6c8vH66NnmB2ac67WVBsgNeoNE2YMoOjznNawIgGZNcgE2UDvNZT 2Gz/nFsTe3+AvGjpPNwt0EFh64Ks/ue3BsQAE0K2XexkF4Ai574IM40UXEM/aeqto2 Lj3Kvq3DU1Csw== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: References: Subject: Re: [PATCH v4 4/4] clk: mxl: Fix a clk entry by adding relevant flags From: Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-lgm-soc@maxlinear.com, Rahul Tanwar To: Rahul Tanwar , linux-clk@vger.kernel.org, mturquette@baylibre.com, yzhu@maxlinear.com Date: Mon, 17 Oct 2022 15:29:07 -0700 User-Agent: alot/0.10 Message-Id: <20221017222909.A1D51C433D7@smtp.kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Rahul Tanwar (2022-10-12 23:48:33) > One of the clock entry "dcl" clk has some HW limitations. One is that > its rate can only by changed by changing its parent clk's rate & two > is that HW does not support enable/disable for this clk. >=20 > Handle above two limitations by adding relevant flags. Add standard > flag CLK_SET_RATE_PARENT to handle rate change and add driver internal > flag DIV_CLK_NO_MASK to handle enable/disable. >=20 > Fixes: d058fd9e8984c ("clk: intel: Add CGU clock driver for a new SoC") > Reviewed-by: Yi xin Zhu > Signed-off-by: Rahul Tanwar > --- Applied to clk-next