Hi Ulf,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on rafael-pm/linux-next arm/for-next arm64/for-next/core clk/clk-next kvmarm/next rockchip/for-next shawnguo/for-next soc/for-next linus/master v6.1-rc1 next-20221018]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ulf-Hansson/soc-qcom-Add-APSS-RSC-to-the-CPU-cluster-PM-domain/20221018-233137
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson%40linaro.org
patch subject: [PATCH v3 6/6] soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup
config: m68k-allyesconfig
compiler: m68k-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/2f9e747dca385eca0eb09df0df78572223ca9486
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Ulf-Hansson/soc-qcom-Add-APSS-RSC-to-the-CPU-cluster-PM-domain/20221018-233137
        git checkout 2f9e747dca385eca0eb09df0df78572223ca9486
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/soc/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/soc/qcom/rpmh-rsc.c: In function 'xloops_to_cycles':
>> drivers/soc/qcom/rpmh-rsc.c:160:48: warning: right shift count >= width of type [-Wshift-count-overflow]
     160 |         return (xloops * loops_per_jiffy * HZ) >> 32;
         |                                                ^~


vim +160 drivers/soc/qcom/rpmh-rsc.c

   100	
   101	/*
   102	 * Here's a high level overview of how all the registers in RPMH work
   103	 * together:
   104	 *
   105	 * - The main rpmh-rsc address is the base of a register space that can
   106	 *   be used to find overall configuration of the hardware
   107	 *   (DRV_PRNT_CHLD_CONFIG). Also found within the rpmh-rsc register
   108	 *   space are all the TCS blocks. The offset of the TCS blocks is
   109	 *   specified in the device tree by "qcom,tcs-offset" and used to
   110	 *   compute tcs_base.
   111	 * - TCS blocks come one after another. Type, count, and order are
   112	 *   specified by the device tree as "qcom,tcs-config".
   113	 * - Each TCS block has some registers, then space for up to 16 commands.
   114	 *   Note that though address space is reserved for 16 commands, fewer
   115	 *   might be present. See ncpt (num cmds per TCS).
   116	 *
   117	 * Here's a picture:
   118	 *
   119	 *  +---------------------------------------------------+
   120	 *  |RSC                                                |
   121	 *  | ctrl                                              |
   122	 *  |                                                   |
   123	 *  | Drvs:                                             |
   124	 *  | +-----------------------------------------------+ |
   125	 *  | |DRV0                                           | |
   126	 *  | | ctrl/config                                   | |
   127	 *  | | IRQ                                           | |
   128	 *  | |                                               | |
   129	 *  | | TCSes:                                        | |
   130	 *  | | +------------------------------------------+  | |
   131	 *  | | |TCS0  |  |  |  |  |  |  |  |  |  |  |  |  |  | |
   132	 *  | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15|  | |
   133	 *  | | |      |  |  |  |  |  |  |  |  |  |  |  |  |  | |
   134	 *  | | +------------------------------------------+  | |
   135	 *  | | +------------------------------------------+  | |
   136	 *  | | |TCS1  |  |  |  |  |  |  |  |  |  |  |  |  |  | |
   137	 *  | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15|  | |
   138	 *  | | |      |  |  |  |  |  |  |  |  |  |  |  |  |  | |
   139	 *  | | +------------------------------------------+  | |
   140	 *  | | +------------------------------------------+  | |
   141	 *  | | |TCS2  |  |  |  |  |  |  |  |  |  |  |  |  |  | |
   142	 *  | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15|  | |
   143	 *  | | |      |  |  |  |  |  |  |  |  |  |  |  |  |  | |
   144	 *  | | +------------------------------------------+  | |
   145	 *  | |                    ......                     | |
   146	 *  | +-----------------------------------------------+ |
   147	 *  | +-----------------------------------------------+ |
   148	 *  | |DRV1                                           | |
   149	 *  | | (same as DRV0)                                | |
   150	 *  | +-----------------------------------------------+ |
   151	 *  |                      ......                       |
   152	 *  +---------------------------------------------------+
   153	 */
   154	
   155	#define USECS_TO_CYCLES(time_usecs)			\
   156		xloops_to_cycles((time_usecs) * 0x10C7UL)
   157	
   158	static inline unsigned long xloops_to_cycles(unsigned long xloops)
   159	{
 > 160		return (xloops * loops_per_jiffy * HZ) >> 32;
   161	}
   162	

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