Hi Gwan-gyeong, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on linus/master] [also build test WARNING on v6.1-rc3 next-20221101] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Gwan-gyeong-Mun/bitfield-Use-argument-type-for-size-comparison-on-Bitfield-access-macros/20221029-133640 patch link: https://lore.kernel.org/r/20221029053429.38381-1-gwan-gyeong.mun%40intel.com patch subject: [PATCH] bitfield: Use argument type for size comparison on Bitfield access macros config: ia64-randconfig-s053-20221031 compiler: ia64-linux-gcc (GCC) 12.1.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.4-39-gce1a6720-dirty # https://github.com/intel-lab-lkp/linux/commit/91f22fce5cc0639c001bcf755c9dec0913073876 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Gwan-gyeong-Mun/bitfield-Use-argument-type-for-size-comparison-on-Bitfield-access-macros/20221029-133640 git checkout 91f22fce5cc0639c001bcf755c9dec0913073876 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/cxl/core/ drivers/net/ethernet/intel/ice/ drivers/net/phy/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot sparse warnings: (new ones prefixed by >>) drivers/cxl/core/pci.c: note: in included file (through arch/ia64/include/asm/io.h, include/linux/io.h, include/linux/io-64-nonatomic-lo-hi.h): include/asm-generic/io.h:239:15: sparse: sparse: cast to restricted __le64 >> drivers/cxl/core/pci.c:380:21: sparse: sparse: cast truncates bits from constant value (ffff0001 becomes 1) drivers/cxl/core/pci.c:395:28: sparse: sparse: cast truncates bits from constant value (ffff0001 becomes 1) -- >> drivers/net/phy/aquantia_main.c:487:14: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) -- >> drivers/net/ethernet/intel/ice/ice_common.c:3742:25: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c:3745:32: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c:3748:38: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c:3756:33: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c:3759:39: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c:3769:34: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c:3771:45: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c: note: in included file (through arch/ia64/include/asm/io.h, include/linux/io.h, drivers/net/ethernet/intel/ice/ice_osdep.h, ...): include/asm-generic/io.h:239:15: sparse: sparse: cast to restricted __le64 drivers/net/ethernet/intel/ice/ice_common.c:5106:21: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) drivers/net/ethernet/intel/ice/ice_common.c:5157:21: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1) vim +380 drivers/cxl/core/pci.c a12562bb707760 Dan Williams 2022-05-18 339 a12562bb707760 Dan Williams 2022-05-18 340 /** a12562bb707760 Dan Williams 2022-05-18 341 * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint a12562bb707760 Dan Williams 2022-05-18 342 * @cxlds: Device state fcfbc93cc33ec6 Dan Williams 2022-05-18 343 * @cxlhdm: Mapped HDM decoder Capability a12562bb707760 Dan Williams 2022-05-18 344 * a12562bb707760 Dan Williams 2022-05-18 345 * Try to enable the endpoint's HDM Decoder Capability a12562bb707760 Dan Williams 2022-05-18 346 */ fcfbc93cc33ec6 Dan Williams 2022-05-18 347 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm) 14d78874077442 Dan Williams 2022-05-18 348 { 14d78874077442 Dan Williams 2022-05-18 349 struct pci_dev *pdev = to_pci_dev(cxlds->dev); 92804edb11f065 Dan Williams 2022-05-18 350 struct cxl_endpoint_dvsec_info info = { 0 }; 14d78874077442 Dan Williams 2022-05-18 351 int hdm_count, rc, i, ranges = 0; 14d78874077442 Dan Williams 2022-05-18 352 struct device *dev = &pdev->dev; 14d78874077442 Dan Williams 2022-05-18 353 int d = cxlds->cxl_dvsec; 14d78874077442 Dan Williams 2022-05-18 354 u16 cap, ctrl; 14d78874077442 Dan Williams 2022-05-18 355 14d78874077442 Dan Williams 2022-05-18 356 if (!d) { 14d78874077442 Dan Williams 2022-05-18 357 dev_dbg(dev, "No DVSEC Capability\n"); 14d78874077442 Dan Williams 2022-05-18 358 return -ENXIO; 14d78874077442 Dan Williams 2022-05-18 359 } 14d78874077442 Dan Williams 2022-05-18 360 14d78874077442 Dan Williams 2022-05-18 361 rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); 14d78874077442 Dan Williams 2022-05-18 362 if (rc) 14d78874077442 Dan Williams 2022-05-18 363 return rc; 14d78874077442 Dan Williams 2022-05-18 364 14d78874077442 Dan Williams 2022-05-18 365 rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); 14d78874077442 Dan Williams 2022-05-18 366 if (rc) 14d78874077442 Dan Williams 2022-05-18 367 return rc; 14d78874077442 Dan Williams 2022-05-18 368 14d78874077442 Dan Williams 2022-05-18 369 if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { 14d78874077442 Dan Williams 2022-05-18 370 dev_dbg(dev, "Not MEM Capable\n"); 14d78874077442 Dan Williams 2022-05-18 371 return -ENXIO; 14d78874077442 Dan Williams 2022-05-18 372 } 14d78874077442 Dan Williams 2022-05-18 373 14d78874077442 Dan Williams 2022-05-18 374 /* 14d78874077442 Dan Williams 2022-05-18 375 * It is not allowed by spec for MEM.capable to be set and have 0 legacy 14d78874077442 Dan Williams 2022-05-18 376 * HDM decoders (values > 2 are also undefined as of CXL 2.0). As this 14d78874077442 Dan Williams 2022-05-18 377 * driver is for a spec defined class code which must be CXL.mem 14d78874077442 Dan Williams 2022-05-18 378 * capable, there is no point in continuing to enable CXL.mem. 14d78874077442 Dan Williams 2022-05-18 379 */ 14d78874077442 Dan Williams 2022-05-18 @380 hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); 14d78874077442 Dan Williams 2022-05-18 381 if (!hdm_count || hdm_count > 2) 14d78874077442 Dan Williams 2022-05-18 382 return -EINVAL; 14d78874077442 Dan Williams 2022-05-18 383 14d78874077442 Dan Williams 2022-05-18 384 rc = wait_for_valid(cxlds); 14d78874077442 Dan Williams 2022-05-18 385 if (rc) { 14d78874077442 Dan Williams 2022-05-18 386 dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc); 14d78874077442 Dan Williams 2022-05-18 387 return rc; 14d78874077442 Dan Williams 2022-05-18 388 } 14d78874077442 Dan Williams 2022-05-18 389 34e37b4c432cd0 Dan Williams 2022-05-20 390 /* 34e37b4c432cd0 Dan Williams 2022-05-20 391 * The current DVSEC values are moot if the memory capability is 34e37b4c432cd0 Dan Williams 2022-05-20 392 * disabled, and they will remain moot after the HDM Decoder 34e37b4c432cd0 Dan Williams 2022-05-20 393 * capability is enabled. 34e37b4c432cd0 Dan Williams 2022-05-20 394 */ 92804edb11f065 Dan Williams 2022-05-18 395 info.mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); 92804edb11f065 Dan Williams 2022-05-18 396 if (!info.mem_enabled) 34e37b4c432cd0 Dan Williams 2022-05-20 397 goto hdm_init; 14d78874077442 Dan Williams 2022-05-18 398 14d78874077442 Dan Williams 2022-05-18 399 for (i = 0; i < hdm_count; i++) { 14d78874077442 Dan Williams 2022-05-18 400 u64 base, size; 14d78874077442 Dan Williams 2022-05-18 401 u32 temp; 14d78874077442 Dan Williams 2022-05-18 402 14d78874077442 Dan Williams 2022-05-18 403 rc = pci_read_config_dword( 14d78874077442 Dan Williams 2022-05-18 404 pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); 14d78874077442 Dan Williams 2022-05-18 405 if (rc) 14d78874077442 Dan Williams 2022-05-18 406 return rc; 14d78874077442 Dan Williams 2022-05-18 407 14d78874077442 Dan Williams 2022-05-18 408 size = (u64)temp << 32; 14d78874077442 Dan Williams 2022-05-18 409 14d78874077442 Dan Williams 2022-05-18 410 rc = pci_read_config_dword( 14d78874077442 Dan Williams 2022-05-18 411 pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp); 14d78874077442 Dan Williams 2022-05-18 412 if (rc) 14d78874077442 Dan Williams 2022-05-18 413 return rc; 14d78874077442 Dan Williams 2022-05-18 414 14d78874077442 Dan Williams 2022-05-18 415 size |= temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; 14d78874077442 Dan Williams 2022-05-18 416 14d78874077442 Dan Williams 2022-05-18 417 rc = pci_read_config_dword( 14d78874077442 Dan Williams 2022-05-18 418 pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp); 14d78874077442 Dan Williams 2022-05-18 419 if (rc) 14d78874077442 Dan Williams 2022-05-18 420 return rc; 14d78874077442 Dan Williams 2022-05-18 421 14d78874077442 Dan Williams 2022-05-18 422 base = (u64)temp << 32; 14d78874077442 Dan Williams 2022-05-18 423 14d78874077442 Dan Williams 2022-05-18 424 rc = pci_read_config_dword( 14d78874077442 Dan Williams 2022-05-18 425 pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp); 14d78874077442 Dan Williams 2022-05-18 426 if (rc) 14d78874077442 Dan Williams 2022-05-18 427 return rc; 14d78874077442 Dan Williams 2022-05-18 428 14d78874077442 Dan Williams 2022-05-18 429 base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK; 14d78874077442 Dan Williams 2022-05-18 430 92804edb11f065 Dan Williams 2022-05-18 431 info.dvsec_range[i] = (struct range) { 14d78874077442 Dan Williams 2022-05-18 432 .start = base, 14d78874077442 Dan Williams 2022-05-18 433 .end = base + size - 1 14d78874077442 Dan Williams 2022-05-18 434 }; 14d78874077442 Dan Williams 2022-05-18 435 14d78874077442 Dan Williams 2022-05-18 436 if (size) 14d78874077442 Dan Williams 2022-05-18 437 ranges++; 14d78874077442 Dan Williams 2022-05-18 438 } 14d78874077442 Dan Williams 2022-05-18 439 92804edb11f065 Dan Williams 2022-05-18 440 info.ranges = ranges; 14d78874077442 Dan Williams 2022-05-18 441 a12562bb707760 Dan Williams 2022-05-18 442 /* a12562bb707760 Dan Williams 2022-05-18 443 * If DVSEC ranges are being used instead of HDM decoder registers there a12562bb707760 Dan Williams 2022-05-18 444 * is no use in trying to manage those. a12562bb707760 Dan Williams 2022-05-18 445 */ 34e37b4c432cd0 Dan Williams 2022-05-20 446 hdm_init: fcfbc93cc33ec6 Dan Williams 2022-05-18 447 if (!__cxl_hdm_decode_init(cxlds, cxlhdm, &info)) { a12562bb707760 Dan Williams 2022-05-18 448 dev_err(dev, a12562bb707760 Dan Williams 2022-05-18 449 "Legacy range registers configuration prevents HDM operation.\n"); a12562bb707760 Dan Williams 2022-05-18 450 return -EBUSY; a12562bb707760 Dan Williams 2022-05-18 451 } a12562bb707760 Dan Williams 2022-05-18 452 14d78874077442 Dan Williams 2022-05-18 453 return 0; 14d78874077442 Dan Williams 2022-05-18 454 } a12562bb707760 Dan Williams 2022-05-18 455 EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); c97006046c791f Ira Weiny 2022-07-19 456 -- 0-DAY CI Kernel Test Service https://01.org/lkp