Hi Gwan-gyeong,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v6.1-rc3 next-20221101]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Gwan-gyeong-Mun/bitfield-Use-argument-type-for-size-comparison-on-Bitfield-access-macros/20221029-133640
patch link:    https://lore.kernel.org/r/20221029053429.38381-1-gwan-gyeong.mun%40intel.com
patch subject: [PATCH] bitfield: Use argument type for size comparison on Bitfield access macros
config: arm-randconfig-s032-20221031
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/intel-lab-lkp/linux/commit/91f22fce5cc0639c001bcf755c9dec0913073876
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Gwan-gyeong-Mun/bitfield-Use-argument-type-for-size-comparison-on-Bitfield-access-macros/20221029-133640
        git checkout 91f22fce5cc0639c001bcf755c9dec0913073876
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=arm SHELL=/bin/bash drivers/gpu/drm/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/drm_edid.c:6095:17: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1)
   drivers/gpu/drm/drm_edid.c:6115:35: sparse: sparse: cast truncates bits from constant value (ffffff01 becomes 1)

vim +6095 drivers/gpu/drm/drm_edid.c

a1d11d1efe4d18 Manasi Navare 2020-03-10  6073  
18a9cbbe558016 Jani Nikula   2021-08-31  6074  static void drm_parse_vesa_mso_data(struct drm_connector *connector,
18a9cbbe558016 Jani Nikula   2021-08-31  6075  				    const struct displayid_block *block)
18a9cbbe558016 Jani Nikula   2021-08-31  6076  {
18a9cbbe558016 Jani Nikula   2021-08-31  6077  	struct displayid_vesa_vendor_specific_block *vesa =
18a9cbbe558016 Jani Nikula   2021-08-31  6078  		(struct displayid_vesa_vendor_specific_block *)block;
18a9cbbe558016 Jani Nikula   2021-08-31  6079  	struct drm_display_info *info = &connector->display_info;
18a9cbbe558016 Jani Nikula   2021-08-31  6080  
18a9cbbe558016 Jani Nikula   2021-08-31  6081  	if (block->num_bytes < 3) {
18a9cbbe558016 Jani Nikula   2021-08-31  6082  		drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
18a9cbbe558016 Jani Nikula   2021-08-31  6083  			    block->num_bytes);
18a9cbbe558016 Jani Nikula   2021-08-31  6084  		return;
18a9cbbe558016 Jani Nikula   2021-08-31  6085  	}
18a9cbbe558016 Jani Nikula   2021-08-31  6086  
18a9cbbe558016 Jani Nikula   2021-08-31  6087  	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
18a9cbbe558016 Jani Nikula   2021-08-31  6088  		return;
18a9cbbe558016 Jani Nikula   2021-08-31  6089  
18a9cbbe558016 Jani Nikula   2021-08-31  6090  	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
18a9cbbe558016 Jani Nikula   2021-08-31  6091  		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
18a9cbbe558016 Jani Nikula   2021-08-31  6092  		return;
18a9cbbe558016 Jani Nikula   2021-08-31  6093  	}
18a9cbbe558016 Jani Nikula   2021-08-31  6094  
18a9cbbe558016 Jani Nikula   2021-08-31 @6095  	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
18a9cbbe558016 Jani Nikula   2021-08-31  6096  	default:
18a9cbbe558016 Jani Nikula   2021-08-31  6097  		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
18a9cbbe558016 Jani Nikula   2021-08-31  6098  		fallthrough;
18a9cbbe558016 Jani Nikula   2021-08-31  6099  	case 0:
18a9cbbe558016 Jani Nikula   2021-08-31  6100  		info->mso_stream_count = 0;
18a9cbbe558016 Jani Nikula   2021-08-31  6101  		break;
18a9cbbe558016 Jani Nikula   2021-08-31  6102  	case 1:
18a9cbbe558016 Jani Nikula   2021-08-31  6103  		info->mso_stream_count = 2; /* 2 or 4 links */
18a9cbbe558016 Jani Nikula   2021-08-31  6104  		break;
18a9cbbe558016 Jani Nikula   2021-08-31  6105  	case 2:
18a9cbbe558016 Jani Nikula   2021-08-31  6106  		info->mso_stream_count = 4; /* 4 links */
18a9cbbe558016 Jani Nikula   2021-08-31  6107  		break;
18a9cbbe558016 Jani Nikula   2021-08-31  6108  	}
18a9cbbe558016 Jani Nikula   2021-08-31  6109  
18a9cbbe558016 Jani Nikula   2021-08-31  6110  	if (!info->mso_stream_count) {
18a9cbbe558016 Jani Nikula   2021-08-31  6111  		info->mso_pixel_overlap = 0;
18a9cbbe558016 Jani Nikula   2021-08-31  6112  		return;
18a9cbbe558016 Jani Nikula   2021-08-31  6113  	}
18a9cbbe558016 Jani Nikula   2021-08-31  6114  
18a9cbbe558016 Jani Nikula   2021-08-31  6115  	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
18a9cbbe558016 Jani Nikula   2021-08-31  6116  	if (info->mso_pixel_overlap > 8) {
18a9cbbe558016 Jani Nikula   2021-08-31  6117  		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
18a9cbbe558016 Jani Nikula   2021-08-31  6118  			    info->mso_pixel_overlap);
18a9cbbe558016 Jani Nikula   2021-08-31  6119  		info->mso_pixel_overlap = 8;
18a9cbbe558016 Jani Nikula   2021-08-31  6120  	}
18a9cbbe558016 Jani Nikula   2021-08-31  6121  
18a9cbbe558016 Jani Nikula   2021-08-31  6122  	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
18a9cbbe558016 Jani Nikula   2021-08-31  6123  		    info->mso_stream_count, info->mso_pixel_overlap);
18a9cbbe558016 Jani Nikula   2021-08-31  6124  }
18a9cbbe558016 Jani Nikula   2021-08-31  6125  

-- 
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https://01.org/lkp