From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B60A7C433FE for ; Sun, 6 Nov 2022 17:07:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230527AbiKFRHy (ORCPT ); Sun, 6 Nov 2022 12:07:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230455AbiKFRHb (ORCPT ); Sun, 6 Nov 2022 12:07:31 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B05BD12A8F; Sun, 6 Nov 2022 09:05:37 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 2B080CE0DFE; Sun, 6 Nov 2022 17:05:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E41AC433D6; Sun, 6 Nov 2022 17:05:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667754329; bh=xQF0jd4vAlo1a0bwEqYmq8NGnNEGxxUiKpQE6/53kLc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WXu7Wps1ZB0BxZl+ctuYC2s8cxedibOqvzuXnIA8F7bNk0K9SFV4I5vHEkaFSjtQc ZhfoHrk9Z81zJum/DutJdNnqHcYfpGVz5fxqoHZIQDDT8XKp8K7q2KF7Q76O3es7o7 AlheKNw40cVsZ/IvALS8ggY2xm7LPxaxe5FEkHPFjcmHGFaRw6ZqLI+3c51zU9G3IO a0JeJVDLR4VQ++4Ui34gFCwl+HiLvkbyeGRa2BVXEf4e2KP3MjG6+0IFL1xZvHA3NI Wl59WmWU/imCjpj1TizKOwrjx/D2oqgENcVs8V7BKhqtsdsOGAFnAKVtfnvYB7gsWq 6N5NjQV12mkFg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mauro Lima , Mika Westerberg , Mark Brown , Sasha Levin , tudor.ambarus@microchip.com, pratyush@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, andriy.shevchenko@linux.intel.com, lee.jones@linaro.org, linux-mtd@lists.infradead.org Subject: [PATCH AUTOSEL 5.15 07/18] spi: intel: Fix the offset to get the 64K erase opcode Date: Sun, 6 Nov 2022 12:04:56 -0500 Message-Id: <20221106170509.1580304-7-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221106170509.1580304-1-sashal@kernel.org> References: <20221106170509.1580304-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mauro Lima [ Upstream commit 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 ] According to documentation, the 64K erase opcode is located in VSCC range [16:23] instead of [8:15]. Use the proper value to shift the mask over the correct range. Signed-off-by: Mauro Lima Reviewed-by: Mika Westerberg Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/mtd/spi-nor/controllers/intel-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/controllers/intel-spi.c b/drivers/mtd/spi-nor/controllers/intel-spi.c index a413892ff449..72dab5937df1 100644 --- a/drivers/mtd/spi-nor/controllers/intel-spi.c +++ b/drivers/mtd/spi-nor/controllers/intel-spi.c @@ -116,7 +116,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 -#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) +#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) #define INTEL_SPI_TIMEOUT 5000 /* ms */ #define INTEL_SPI_FIFO_SZ 64 -- 2.35.1