From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE6CEC433FE for ; Sun, 6 Nov 2022 17:10:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231245AbiKFRKt (ORCPT ); Sun, 6 Nov 2022 12:10:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231232AbiKFRKR (ORCPT ); Sun, 6 Nov 2022 12:10:17 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 141E413F76; Sun, 6 Nov 2022 09:06:59 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 216AE60CD4; Sun, 6 Nov 2022 17:06:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B3FBC433C1; Sun, 6 Nov 2022 17:06:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667754373; bh=8s1SAEAUQi9Iu/CB0Z3srSJkqdB0oJJaPfhfxwFNUpQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MiBVkZhJzacEvad7pL+DlplueGva46afQtQZr0ifF8B4c25eBp2Zc29o8SLXwbA9O CPER7IlQ8qMWEQf+tLdMK/aGjhCBm1Sm4v9K+lhXCaV8B8Cq/0Z0gnlj2iVD1WlgiQ Kv7IwBuCV47hGJlQnWXUFPPZM9shhWQh0ADFCTEcD/fz0Dx+Rvd2htFpBuSfIfNC7d yp6wfnKMX0Jz1Kbmu9L4YTz1/x42ig8VJv0+GS4kXF5WF/IO4Qpm1hMKBAT85q8RRB VBcIlUewVkqG7LjgFAB9IPdcyI433/evxNEyRg+5OsvIcmba53A47r8vUJH1UIEPnp yA0Hb5IvKjn4A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mauro Lima , Mika Westerberg , Mark Brown , Sasha Levin , tudor.ambarus@microchip.com, pratyush@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, andriy.shevchenko@linux.intel.com, lee.jones@linaro.org, linux-mtd@lists.infradead.org Subject: [PATCH AUTOSEL 5.10 06/16] spi: intel: Fix the offset to get the 64K erase opcode Date: Sun, 6 Nov 2022 12:05:43 -0500 Message-Id: <20221106170555.1580584-6-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221106170555.1580584-1-sashal@kernel.org> References: <20221106170555.1580584-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mauro Lima [ Upstream commit 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 ] According to documentation, the 64K erase opcode is located in VSCC range [16:23] instead of [8:15]. Use the proper value to shift the mask over the correct range. Signed-off-by: Mauro Lima Reviewed-by: Mika Westerberg Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/mtd/spi-nor/controllers/intel-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/controllers/intel-spi.c b/drivers/mtd/spi-nor/controllers/intel-spi.c index b54a56a68100..b4b0affd16c8 100644 --- a/drivers/mtd/spi-nor/controllers/intel-spi.c +++ b/drivers/mtd/spi-nor/controllers/intel-spi.c @@ -117,7 +117,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 -#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) +#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) #define INTEL_SPI_TIMEOUT 5000 /* ms */ #define INTEL_SPI_FIFO_SZ 64 -- 2.35.1