tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: f141df371335645ce29a87d9683a3f79fba7fd67 commit: c6abbcbc769554bf5661b3fa54b7ef52975d561d drm/amdgpu: add mes ctx data in amdgpu_ring date: 6 months ago config: mips-randconfig-r025-20221108 compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 463da45892e2d2a262277b91b96f5f8c05dc25d0) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install mips cross compiling tool for clang build # apt-get install binutils-mips-linux-gnu # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c6abbcbc769554bf5661b3fa54b7ef52975d561d git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout c6abbcbc769554bf5661b3fa54b7ef52975d561d # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/gpu/drm/amd/amdgpu/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot All warnings (new ones prefixed by >>): >> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1089:12: warning: stack frame size (1040) exceeds limit (1024) in 'vcn_v3_0_start' [-Wframe-larger-than] static int vcn_v3_0_start(struct amdgpu_device *adev) ^ 1016/1040 (97.69%) spills, 24/1040 (2.31%) variables 1 warning generated. vim +/vcn_v3_0_start +1089 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c ec2d0577b466c2 Boyuan Zhang 2020-03-27 1088 cf14826cdfb5c9 Leo Liu 2019-11-15 @1089 static int vcn_v3_0_start(struct amdgpu_device *adev) cf14826cdfb5c9 Leo Liu 2019-11-15 1090 { e42dd87e70e66a Sonny Jiang 2020-11-27 1091 volatile struct amdgpu_fw_shared *fw_shared; cf14826cdfb5c9 Leo Liu 2019-11-15 1092 struct amdgpu_ring *ring; cf14826cdfb5c9 Leo Liu 2019-11-15 1093 uint32_t rb_bufsz, tmp; cf14826cdfb5c9 Leo Liu 2019-11-15 1094 int i, j, k, r; cf14826cdfb5c9 Leo Liu 2019-11-15 1095 cf14826cdfb5c9 Leo Liu 2019-11-15 1096 if (adev->pm.dpm_enabled) cf14826cdfb5c9 Leo Liu 2019-11-15 1097 amdgpu_dpm_enable_uvd(adev, true); cf14826cdfb5c9 Leo Liu 2019-11-15 1098 cf14826cdfb5c9 Leo Liu 2019-11-15 1099 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { cf14826cdfb5c9 Leo Liu 2019-11-15 1100 if (adev->vcn.harvest_config & (1 << i)) cf14826cdfb5c9 Leo Liu 2019-11-15 1101 continue; cf14826cdfb5c9 Leo Liu 2019-11-15 1102 ec2d0577b466c2 Boyuan Zhang 2020-03-27 1103 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ ec2d0577b466c2 Boyuan Zhang 2020-03-27 1104 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); ec2d0577b466c2 Boyuan Zhang 2020-03-27 1105 continue; ec2d0577b466c2 Boyuan Zhang 2020-03-27 1106 } ec2d0577b466c2 Boyuan Zhang 2020-03-27 1107 fedac0155a1c28 Leo Liu 2019-11-27 1108 /* disable VCN power gating */ fedac0155a1c28 Leo Liu 2019-11-27 1109 vcn_v3_0_disable_static_power_gating(adev, i); fedac0155a1c28 Leo Liu 2019-11-27 1110 cf14826cdfb5c9 Leo Liu 2019-11-15 1111 /* set VCN status busy */ cf14826cdfb5c9 Leo Liu 2019-11-15 1112 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; cf14826cdfb5c9 Leo Liu 2019-11-15 1113 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); cf14826cdfb5c9 Leo Liu 2019-11-15 1114 fedac0155a1c28 Leo Liu 2019-11-27 1115 /*SW clock gating */ fedac0155a1c28 Leo Liu 2019-11-27 1116 vcn_v3_0_disable_clock_gating(adev, i); fedac0155a1c28 Leo Liu 2019-11-27 1117 cf14826cdfb5c9 Leo Liu 2019-11-15 1118 /* enable VCPU clock */ cf14826cdfb5c9 Leo Liu 2019-11-15 1119 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), cf14826cdfb5c9 Leo Liu 2019-11-15 1120 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1121 cf14826cdfb5c9 Leo Liu 2019-11-15 1122 /* disable master interrupt */ cf14826cdfb5c9 Leo Liu 2019-11-15 1123 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, cf14826cdfb5c9 Leo Liu 2019-11-15 1124 ~UVD_MASTINT_EN__VCPU_EN_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1125 d6b0185b8dc738 Leo Liu 2020-01-28 1126 /* enable LMI MC and UMC channels */ d6b0185b8dc738 Leo Liu 2020-01-28 1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, d6b0185b8dc738 Leo Liu 2020-01-28 1128 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); d6b0185b8dc738 Leo Liu 2020-01-28 1129 d6b0185b8dc738 Leo Liu 2020-01-28 1130 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); d6b0185b8dc738 Leo Liu 2020-01-28 1131 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; d6b0185b8dc738 Leo Liu 2020-01-28 1132 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; d6b0185b8dc738 Leo Liu 2020-01-28 1133 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); d6b0185b8dc738 Leo Liu 2020-01-28 1134 cf14826cdfb5c9 Leo Liu 2019-11-15 1135 /* setup mmUVD_LMI_CTRL */ cf14826cdfb5c9 Leo Liu 2019-11-15 1136 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); cf14826cdfb5c9 Leo Liu 2019-11-15 1137 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | cf14826cdfb5c9 Leo Liu 2019-11-15 1138 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | cf14826cdfb5c9 Leo Liu 2019-11-15 1139 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | cf14826cdfb5c9 Leo Liu 2019-11-15 1140 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | cf14826cdfb5c9 Leo Liu 2019-11-15 1141 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1142 cf14826cdfb5c9 Leo Liu 2019-11-15 1143 /* setup mmUVD_MPC_CNTL */ cf14826cdfb5c9 Leo Liu 2019-11-15 1144 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); cf14826cdfb5c9 Leo Liu 2019-11-15 1145 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; cf14826cdfb5c9 Leo Liu 2019-11-15 1146 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; cf14826cdfb5c9 Leo Liu 2019-11-15 1147 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); cf14826cdfb5c9 Leo Liu 2019-11-15 1148 cf14826cdfb5c9 Leo Liu 2019-11-15 1149 /* setup UVD_MPC_SET_MUXA0 */ cf14826cdfb5c9 Leo Liu 2019-11-15 1150 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, cf14826cdfb5c9 Leo Liu 2019-11-15 1151 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1152 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1153 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1154 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); cf14826cdfb5c9 Leo Liu 2019-11-15 1155 cf14826cdfb5c9 Leo Liu 2019-11-15 1156 /* setup UVD_MPC_SET_MUXB0 */ cf14826cdfb5c9 Leo Liu 2019-11-15 1157 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, cf14826cdfb5c9 Leo Liu 2019-11-15 1158 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1159 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1160 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1161 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); cf14826cdfb5c9 Leo Liu 2019-11-15 1162 cf14826cdfb5c9 Leo Liu 2019-11-15 1163 /* setup mmUVD_MPC_SET_MUX */ cf14826cdfb5c9 Leo Liu 2019-11-15 1164 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, cf14826cdfb5c9 Leo Liu 2019-11-15 1165 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1166 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | cf14826cdfb5c9 Leo Liu 2019-11-15 1167 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); cf14826cdfb5c9 Leo Liu 2019-11-15 1168 cf14826cdfb5c9 Leo Liu 2019-11-15 1169 vcn_v3_0_mc_resume(adev, i); cf14826cdfb5c9 Leo Liu 2019-11-15 1170 cf14826cdfb5c9 Leo Liu 2019-11-15 1171 /* VCN global tiling registers */ cf14826cdfb5c9 Leo Liu 2019-11-15 1172 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, cf14826cdfb5c9 Leo Liu 2019-11-15 1173 adev->gfx.config.gb_addr_config); cf14826cdfb5c9 Leo Liu 2019-11-15 1174 cf14826cdfb5c9 Leo Liu 2019-11-15 1175 /* unblock VCPU register access */ cf14826cdfb5c9 Leo Liu 2019-11-15 1176 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, cf14826cdfb5c9 Leo Liu 2019-11-15 1177 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1178 cf14826cdfb5c9 Leo Liu 2019-11-15 1179 /* release VCPU reset to boot */ cf14826cdfb5c9 Leo Liu 2019-11-15 1180 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, cf14826cdfb5c9 Leo Liu 2019-11-15 1181 ~UVD_VCPU_CNTL__BLK_RST_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1182 cf14826cdfb5c9 Leo Liu 2019-11-15 1183 for (j = 0; j < 10; ++j) { cf14826cdfb5c9 Leo Liu 2019-11-15 1184 uint32_t status; cf14826cdfb5c9 Leo Liu 2019-11-15 1185 cf14826cdfb5c9 Leo Liu 2019-11-15 1186 for (k = 0; k < 100; ++k) { cf14826cdfb5c9 Leo Liu 2019-11-15 1187 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); cf14826cdfb5c9 Leo Liu 2019-11-15 1188 if (status & 2) cf14826cdfb5c9 Leo Liu 2019-11-15 1189 break; cf14826cdfb5c9 Leo Liu 2019-11-15 1190 mdelay(10); cf14826cdfb5c9 Leo Liu 2019-11-15 1191 } cf14826cdfb5c9 Leo Liu 2019-11-15 1192 r = 0; cf14826cdfb5c9 Leo Liu 2019-11-15 1193 if (status & 2) cf14826cdfb5c9 Leo Liu 2019-11-15 1194 break; cf14826cdfb5c9 Leo Liu 2019-11-15 1195 cf14826cdfb5c9 Leo Liu 2019-11-15 1196 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); cf14826cdfb5c9 Leo Liu 2019-11-15 1197 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), cf14826cdfb5c9 Leo Liu 2019-11-15 1198 UVD_VCPU_CNTL__BLK_RST_MASK, cf14826cdfb5c9 Leo Liu 2019-11-15 1199 ~UVD_VCPU_CNTL__BLK_RST_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1200 mdelay(10); cf14826cdfb5c9 Leo Liu 2019-11-15 1201 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, cf14826cdfb5c9 Leo Liu 2019-11-15 1202 ~UVD_VCPU_CNTL__BLK_RST_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1203 cf14826cdfb5c9 Leo Liu 2019-11-15 1204 mdelay(10); cf14826cdfb5c9 Leo Liu 2019-11-15 1205 r = -1; cf14826cdfb5c9 Leo Liu 2019-11-15 1206 } cf14826cdfb5c9 Leo Liu 2019-11-15 1207 cf14826cdfb5c9 Leo Liu 2019-11-15 1208 if (r) { cf14826cdfb5c9 Leo Liu 2019-11-15 1209 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); cf14826cdfb5c9 Leo Liu 2019-11-15 1210 return r; cf14826cdfb5c9 Leo Liu 2019-11-15 1211 } cf14826cdfb5c9 Leo Liu 2019-11-15 1212 cf14826cdfb5c9 Leo Liu 2019-11-15 1213 /* enable master interrupt */ cf14826cdfb5c9 Leo Liu 2019-11-15 1214 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), cf14826cdfb5c9 Leo Liu 2019-11-15 1215 UVD_MASTINT_EN__VCPU_EN_MASK, cf14826cdfb5c9 Leo Liu 2019-11-15 1216 ~UVD_MASTINT_EN__VCPU_EN_MASK); cf14826cdfb5c9 Leo Liu 2019-11-15 1217 cf14826cdfb5c9 Leo Liu 2019-11-15 1218 /* clear the busy bit of VCN_STATUS */ cf14826cdfb5c9 Leo Liu 2019-11-15 1219 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, cf14826cdfb5c9 Leo Liu 2019-11-15 1220 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); cf14826cdfb5c9 Leo Liu 2019-11-15 1221 cf14826cdfb5c9 Leo Liu 2019-11-15 1222 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); cf14826cdfb5c9 Leo Liu 2019-11-15 1223 cf14826cdfb5c9 Leo Liu 2019-11-15 1224 ring = &adev->vcn.inst[i].ring_dec; cf14826cdfb5c9 Leo Liu 2019-11-15 1225 /* force RBC into idle state */ cf14826cdfb5c9 Leo Liu 2019-11-15 1226 rb_bufsz = order_base_2(ring->ring_size); cf14826cdfb5c9 Leo Liu 2019-11-15 1227 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); cf14826cdfb5c9 Leo Liu 2019-11-15 1228 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); cf14826cdfb5c9 Leo Liu 2019-11-15 1229 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); cf14826cdfb5c9 Leo Liu 2019-11-15 1230 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); cf14826cdfb5c9 Leo Liu 2019-11-15 1231 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); cf14826cdfb5c9 Leo Liu 2019-11-15 1232 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); cf14826cdfb5c9 Leo Liu 2019-11-15 1233 b6065ebf55ff2f Ruijing Dong 2022-03-02 1234 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; e42dd87e70e66a Sonny Jiang 2020-11-27 1235 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); e42dd87e70e66a Sonny Jiang 2020-11-27 1236 cf14826cdfb5c9 Leo Liu 2019-11-15 1237 /* programm the RB_BASE for ring buffer */ cf14826cdfb5c9 Leo Liu 2019-11-15 1238 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, cf14826cdfb5c9 Leo Liu 2019-11-15 1239 lower_32_bits(ring->gpu_addr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1240 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, cf14826cdfb5c9 Leo Liu 2019-11-15 1241 upper_32_bits(ring->gpu_addr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1242 cf14826cdfb5c9 Leo Liu 2019-11-15 1243 /* Initialize the ring buffer's read and write pointers */ cf14826cdfb5c9 Leo Liu 2019-11-15 1244 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); cf14826cdfb5c9 Leo Liu 2019-11-15 1245 b2576c3bf4ce9b Sonny Jiang 2021-01-31 1246 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); cf14826cdfb5c9 Leo Liu 2019-11-15 1247 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); cf14826cdfb5c9 Leo Liu 2019-11-15 1248 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, cf14826cdfb5c9 Leo Liu 2019-11-15 1249 lower_32_bits(ring->wptr)); b2576c3bf4ce9b Sonny Jiang 2021-01-31 1250 fw_shared->rb.wptr = lower_32_bits(ring->wptr); e42dd87e70e66a Sonny Jiang 2020-11-27 1251 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); e42dd87e70e66a Sonny Jiang 2020-11-27 1252 1d789535a03679 Alex Deucher 2021-10-04 1253 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) { e42dd87e70e66a Sonny Jiang 2020-11-27 1254 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); cf14826cdfb5c9 Leo Liu 2019-11-15 1255 ring = &adev->vcn.inst[i].ring_enc[0]; cf14826cdfb5c9 Leo Liu 2019-11-15 1256 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1257 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1258 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); cf14826cdfb5c9 Leo Liu 2019-11-15 1259 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1260 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); e42dd87e70e66a Sonny Jiang 2020-11-27 1261 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); cf14826cdfb5c9 Leo Liu 2019-11-15 1262 e42dd87e70e66a Sonny Jiang 2020-11-27 1263 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); cf14826cdfb5c9 Leo Liu 2019-11-15 1264 ring = &adev->vcn.inst[i].ring_enc[1]; cf14826cdfb5c9 Leo Liu 2019-11-15 1265 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1266 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1267 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); cf14826cdfb5c9 Leo Liu 2019-11-15 1268 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); cf14826cdfb5c9 Leo Liu 2019-11-15 1269 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); e42dd87e70e66a Sonny Jiang 2020-11-27 1270 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); cf14826cdfb5c9 Leo Liu 2019-11-15 1271 } f703d4b6f20688 Veerabadhran Gopalakrishnan 2021-03-11 1272 } cf14826cdfb5c9 Leo Liu 2019-11-15 1273 cf14826cdfb5c9 Leo Liu 2019-11-15 1274 return 0; cf14826cdfb5c9 Leo Liu 2019-11-15 1275 } cf14826cdfb5c9 Leo Liu 2019-11-15 1276 :::::: The code at line 1089 was first introduced by commit :::::: cf14826cdfb5c9fe10f98210d040b9d7486c381d drm/amdgpu: add VCN3.0 support for Sienna_Cichlid :::::: TO: Leo Liu :::::: CC: Alex Deucher -- 0-DAY CI Kernel Test Service https://01.org/lkp