From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DAC7C4332F for ; Wed, 9 Nov 2022 16:52:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231145AbiKIQwL (ORCPT ); Wed, 9 Nov 2022 11:52:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229835AbiKIQwJ (ORCPT ); Wed, 9 Nov 2022 11:52:09 -0500 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74D7EF5AA for ; Wed, 9 Nov 2022 08:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668012728; x=1699548728; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YRI2YivWJDaeR3A5b46DIJCCsip9GmvTxTmH9XsxWxQ=; b=QpTntwL+FVQNTknom4ZIYddUTiI+tOIcetkLbYYUZP8o1WhDjKJ6EkHl 5olebQlHyFG8z+P33xcJGBZPzNkUsaS5xSrxK8G/dKRqQ4auSDWaPlWB4 anPB5wUNJYXC3zy0Qlhj7avVVjhxmNU3RZLMi9CxS2olm+NGwcVZCEjJg K4j5uExCozC1hMZc3g+plmpcJtOvKLx/0o6vCGco8oGDqoBvGgQVYzU9P Vtq1Y3yhN2LvHRrU4vk1QuugtnxOYbsMFBykbjPjnRLVEWL2cD6My2e4Y 2/a4c5J3i4mllwrby5yK10iORBaI5lQ6B6+r9H+7bDVMTs9oOwGhqgVD2 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="294405263" X-IronPort-AV: E=Sophos;i="5.96,151,1665471600"; d="scan'208";a="294405263" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 08:52:07 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="700426422" X-IronPort-AV: E=Sophos;i="5.96,151,1665471600"; d="scan'208";a="700426422" Received: from dschramm-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.251.219.85]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 08:52:03 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 6269610946C; Wed, 9 Nov 2022 19:52:00 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv12 01/16] x86/mm: Fix CR3_ADDR_MASK Date: Wed, 9 Nov 2022 19:51:25 +0300 Message-Id: <20221109165140.9137-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221109165140.9137-1-kirill.shutemov@linux.intel.com> References: <20221109165140.9137-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The mask must not include bits above physical address mask. These bits are reserved and can be used for other things. Bits 61 and 62 are used for Linear Address Masking. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe Reviewed-by: Alexander Potapenko Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/processor-flags.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index 02c2cbda4a74..a7f3d9100adb 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) -- 2.38.0