From: Shradha Todi <shradha.t@samsung.com>
To: bhelgaas@google.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, kishon@ti.com,
vkoul@kernel.org, lpieralisi@kernel.org, kw@linux.com,
mani@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org,
alim.akhtar@samsung.com, ajaykumar.rs@samsung.com,
rcsekar@samsung.com, sriranjani.p@samsung.com,
bharat.uppal@samsung.com, s.prashar@samsung.com,
aswani.reddy@samsung.com, pankaj.dubey@samsung.com,
p.rajanbabu@samsung.com, niyas.ahmed@samsung.com,
chanho61.park@samsung.com
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
Shradha Todi <shradha.t@samsung.com>
Subject: [PATCH 5/6] arm64: dts: fsd: Add PCIe support for Tesla FSD SoC
Date: Mon, 21 Nov 2022 16:22:09 +0530 [thread overview]
Message-ID: <20221121105210.68596-6-shradha.t@samsung.com> (raw)
In-Reply-To: <20221121105210.68596-1-shradha.t@samsung.com>
Add the support for PCIe controller driver and phy driver
for Tesla FSD. It includes support for both RC and EP.
Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
---
arch/arm64/boot/dts/tesla/fsd-evb.dts | 48 ++++++
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 65 ++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 171 +++++++++++++++++++++
3 files changed, 284 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 1db6ddf03f01..cda72b0f76f8 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -41,3 +41,51 @@
&ufs {
status = "okay";
};
+
+&pcie_phy0 {
+ status = "disabled";
+};
+
+&pcie_phy1 {
+ status = "disabled";
+};
+
+&pcie4_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>,
+ <&pcie0_slot1>;
+ status = "disabled";
+};
+
+&pcie4_ep {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>,
+ <&pcie0_slot1>;
+ status = "disabled";
+};
+
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>,
+ <&pcie0_slot0>;
+ status = "disabled";
+};
+
+&pcie0_ep {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>,
+ <&pcie0_slot0>;
+ status = "disabled";
+};
+
+&pcie1_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>;
+ status = "disabled";
+};
+
+&pcie1_ep {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>;
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index d0abb9aa0e9e..edae62dfa987 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -64,6 +64,27 @@
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
samsung,pin-drv = <FSD_PIN_DRV_LV2>;
};
+
+ pcie1_clkreq: pcie1-clkreq {
+ samsung,pins = "gpf6-0";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ pcie1_wake: pcie1-wake {
+ samsung,pins = "gpf6-1";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ pcie1_preset: pcie1-preset {
+ samsung,pins = "gpf6-2";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
};
&pinctrl_peric {
@@ -339,6 +360,50 @@
samsung,pin-pud = <FSD_PIN_PULL_UP>;
samsung,pin-drv = <FSD_PIN_DRV_LV1>;
};
+
+ pcie0_clkreq: pcie0-clkreq {
+ samsung,pins = "gpc8-0";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ pcie0_wake1: pcie0-wake1 {
+ samsung,pins = "gpc8-3";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ pcie0_wake0: pcie0-wake0 {
+ samsung,pins = "gpc8-1";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ pcie0_preset0: pcie0-preset0 {
+ samsung,pins = "gpc8-2";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ pcie0_slot0: pcie0-gpio22 {
+ samsung,pins = "gpg2-6";
+ samsung,pin-function = <FSD_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ samsung,pin-val = <1>;
+ };
+
+ pcie0_slot1: pcie0-gpio23 {
+ samsung,pins = "gpg2-7";
+ samsung,pin-function = <FSD_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ samsung,pin-val = <1>;
+ };
};
&pinctrl_pmu {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index f35bc5a288c2..2177f6964553 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -32,6 +32,14 @@
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
+ pciephy0 = &pcie_phy0;
+ pciephy1 = &pcie_phy1;
+ pcierc0 = &pcie0_rc;
+ pcieep0 = &pcie0_ep;
+ pcierc1 = &pcie1_rc;
+ pcieep1 = &pcie1_ep;
+ pcierc2 = &pcie4_rc;
+ pcieep2 = &pcie4_ep;
};
cpus {
@@ -860,6 +868,169 @@
clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
clock-names = "ref_clk";
};
+
+ pcie_phy0: pcie-phy@15080000 {
+ compatible = "tesla,fsd-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x15080000 0x0 0x2000>,
+ <0x0 0x150A0000 0x0 0x1000>;
+ reg-names = "phy", "pcs";
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+ tesla,pcie-sysreg = <&sysreg_fsys0>;
+ phy-mode = <0>;
+ status = "disabled";
+ };
+
+ pcie_phy1: pcie-phy@16880000 {
+ compatible = "tesla,fsd-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x16880000 0x0 0x2000>,
+ <0x0 0x16860000 0x0 0x1000>;
+ reg-names = "phy", "pcs";
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+ tesla,pcie-sysreg = <&sysreg_fsys1>;
+ phy-mode = <0>;
+ status = "disabled";
+ };
+
+ pcie4_rc: pcie@15400000 {
+ compatible = "tesla,fsd-pcie";
+ clocks = <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>,
+ <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>,
+ <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>,
+ <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>;
+ clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ num-lanes = <4>;
+ reg = <0x0 0x15090000 0x0 0x1000>,
+ <0x0 0x15400000 0x0 0x1000>,
+ <0x0 0x15800000 0x0 0x1000>;
+ reg-names = "appl", "dbi", "config";
+ ranges = <0x82000000 0 0x15801000 0 0x15801000 0 0xffefff>;
+ tesla,pcie-sysreg = <&sysreg_fsys0 0x434>;
+ phys = <&pcie_phy0>;
+ phy-names = "pcie_phy0";
+ iommu-map = <0x0 &smmu_fsys0 0x4 0x10000>;
+ iommu-map-mask = <0x0>;
+ status = "disabled";
+ };
+
+ pcie4_ep: pcie-ep@15400000 {
+ compatible = "tesla,fsd-pcie-ep";
+ clocks = <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>,
+ <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>,
+ <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>,
+ <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>;
+ clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "sub_ctrl_intr";
+ reg = <0x0 0x15090000 0x0 0x1000>,
+ <0x0 0x15400000 0x0 0x1000>,
+ <0x0 0x15401000 0x0 0x80>,
+ <0x0 0x15800000 0x0 0xFF0000>;
+ reg-names = "appl", "dbi", "dbi2", "addr_space";
+ num-lanes = <4>;
+ tesla,pcie-sysreg = <&sysreg_fsys0 0x434>;
+ phys = <&pcie_phy0>;
+ phy-names = "pcie_phy0";
+ status = "disabled";
+ };
+
+ pcie0_rc: pcie@16A00000 {
+ compatible = "tesla,fsd-pcie";
+ clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ num-lanes = <4>;
+ reg = <0x0 0x168B0000 0x0 0x1000>,
+ <0x0 0x16A00000 0x0 0x2000>,
+ <0x0 0x17000000 0x0 0x1000>;
+ reg-names = "appl", "dbi", "config";
+ ranges = <0x82000000 0 0x17001000 0 0x17001000 0 0xffefff>;
+ tesla,pcie-sysreg = <&sysreg_fsys1 0x50C>;
+ phys = <&pcie_phy1>;
+ phy-names = "pcie_phy1";
+ iommu-map = <0x0 &smmu_imem 0x0 0x10000>;
+ iommu-map-mask = <0x0>;
+ status = "disabled";
+ };
+
+ pcie0_ep: pcie-ep@16A00000 {
+ compatible = "tesla,fsd-pcie-ep";
+ clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "sub_ctrl_intr";
+ reg = <0x0 0x168B0000 0x0 0x1000>,
+ <0x0 0x16A00000 0x0 0x1000>,
+ <0x0 0x16A01000 0x0 0x80>,
+ <0x0 0x17000000 0x0 0xFF0000>;
+ reg-names = "appl", "dbi", "dbi2", "addr_space";
+ num-lanes = <4>;
+ tesla,pcie-sysreg = <&sysreg_fsys1 0x50C>;
+ phys = <&pcie_phy1>;
+ phy-names = "pcie_phy1";
+ status = "disabled";
+ };
+
+ pcie1_rc: pcie-rc@16B00000 {
+ compatible = "tesla,fsd-pcie";
+ clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ num-lanes = <4>;
+ reg = <0x0 0x168C0000 0x0 0x1000>,
+ <0x0 0x16B00000 0x0 0x1000>,
+ <0x0 0x18000000 0x0 0x1000>;
+ reg-names = "appl", "dbi", "config";
+ ranges = <0x82000000 0 0x18001000 0 0x18001000 0 0xffefff>;
+ tesla,pcie-sysreg = <&sysreg_fsys1 0x510>;
+ phys = <&pcie_phy1>;
+ phy-names = "pcie_phy1";
+ status = "disabled";
+ };
+
+ pcie1_ep: pcie-ep@16B00000 {
+ compatible = "tesla,fsd-pcie";
+ clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "intr";
+ reg = <0x0 0x168C0000 0x0 0x1000>,
+ <0x0 0x16B00000 0x0 0x1000>,
+ <0x0 0x16B01000 0x0 0x80>,
+ <0x0 0x18000000 0x0 0xFF0000>;
+ reg-names = "appl", "dbi", "dbi2", "addr_space";
+ num-lanes = <4>;
+ tesla,pcie-sysreg = <&sysreg_fsys1 0x510>;
+ phys = <&pcie_phy1>;
+ phy-names = "pcie_phy1";
+ status = "disabled";
+ };
};
};
--
2.17.1
next prev parent reply other threads:[~2022-11-21 11:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20221121104714epcas5p27508b91010c72117dd7116fc387b382f@epcas5p2.samsung.com>
2022-11-21 10:52 ` [PATCH 0/6] " Shradha Todi
[not found] ` <CGME20221121104719epcas5p2f87febfba74a4ca6807b3095acf507d0@epcas5p2.samsung.com>
2022-11-21 10:52 ` [PATCH 1/6] dt-bindings: phy: Add PCIe PHY bindings for FSD Shradha Todi
2022-11-21 11:59 ` Krzysztof Kozlowski
[not found] ` <CGME20221121104725epcas5p3af00b0c717f2132f5c1ba7fd4e903e26@epcas5p3.samsung.com>
2022-11-21 10:52 ` [PATCH 2/6] dt-bindings: PCI: Add PCIe controller " Shradha Todi
2022-11-21 12:05 ` Krzysztof Kozlowski
[not found] ` <CGME20221121104731epcas5p48f96c92e5bfb4ede56ce74a78887a2f3@epcas5p4.samsung.com>
2022-11-21 10:52 ` [PATCH 3/6] PCI: dwc: fsd: Add FSD PCIe Controller driver support Shradha Todi
2022-11-21 12:07 ` Krzysztof Kozlowski
2022-11-21 23:18 ` Bjorn Helgaas
2022-11-30 18:44 ` Rob Herring
[not found] ` <CGME20221121104736epcas5p36c12ff0b575af77f8cf99811b055b339@epcas5p3.samsung.com>
2022-11-21 10:52 ` [PATCH 4/6] phy: tesla-pcie: Add PCIe PHY driver support for FSD Shradha Todi
2022-11-21 12:08 ` Krzysztof Kozlowski
[not found] ` <CGME20221121104741epcas5p31e1320bc4c0912485c1fabe52ea19988@epcas5p3.samsung.com>
2022-11-21 10:52 ` Shradha Todi [this message]
2022-11-21 12:11 ` [PATCH 5/6] arm64: dts: fsd: Add PCIe support for Tesla FSD SoC Krzysztof Kozlowski
2022-12-03 9:55 ` kernel test robot
[not found] ` <CGME20221121104746epcas5p109c7bb299cf19070a9237c00c162ed8f@epcas5p1.samsung.com>
2022-11-21 10:52 ` [PATCH 6/6] misc: pci_endpoint_test: Add driver data for FSD PCIe controllers Shradha Todi
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