From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1795C4332F for ; Tue, 22 Nov 2022 10:17:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233219AbiKVKRk (ORCPT ); Tue, 22 Nov 2022 05:17:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233399AbiKVKRA (ORCPT ); Tue, 22 Nov 2022 05:17:00 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84AAB51328; Tue, 22 Nov 2022 02:16:51 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGjG0118385; Tue, 22 Nov 2022 04:16:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669112205; bh=ac4Z8P3rBXZkZq+HC3t7a6d1XGYyHS+dBSY/4gN4278=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=twiD3GSeMPrLYlxSLVLnkzZvQqvferS+enX6t48JadDlVZDVLLWwdc00VW/fKz/NN 7Uw7pE27vX8EZhrrhr8574EFGPSMFiBzozW2Z7+g96fk51idRspgKDpFQprT7mtxS+ qFmkMQ3DzdC1b7PD8XyNvskpme+G6Raf3uAxDEMg= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AMAGjm2019851 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Nov 2022 04:16:45 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 22 Nov 2022 04:16:45 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 22 Nov 2022 04:16:44 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AMAGg5t030109; Tue, 22 Nov 2022 04:16:43 -0600 From: Matt Ranostay To: , , , , , , , CC: , , Subject: [PATCH v7 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Date: Tue, 22 Nov 2022 02:16:13 -0800 Message-ID: <20221122101616.770050-6-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221122101616.770050-1-mranostay@ti.com> References: <20221122101616.770050-1-mranostay@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Aswath Govindraju The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Reviewed-by: Ravi Gunasekaran Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c3a397484c70..c787d46f89de 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; &wkup_pmx0 { @@ -318,6 +324,22 @@ serdes0_pcie_link: phy@0 { }; }; +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- 2.38.GIT