Hi Guillaume, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on e4cd8d3ff7f9efeb97330e5e9b99eeb2a68f5cf9] url: https://github.com/intel-lab-lkp/linux/commits/Guillaume-Ranquet/Add-MT8195-HDMI-phy-support/20221121-222450 base: e4cd8d3ff7f9efeb97330e5e9b99eeb2a68f5cf9 patch link: https://lore.kernel.org/r/20220919-v4-3-bdc21e1307e9%40baylibre.com patch subject: [PATCH v4 3/3] phy: mediatek: add support for phy-mtk-hdmi-mt8195 config: sh-allmodconfig compiler: sh4-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/d32ab013c35b27ecaaa5de4148bdf8d2dfff5a86 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Guillaume-Ranquet/Add-MT8195-HDMI-phy-support/20221121-222450 git checkout d32ab013c35b27ecaaa5de4148bdf8d2dfff5a86 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=sh SHELL=/bin/bash drivers/phy/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot All warnings (new ones prefixed by >>): In file included from include/linux/bits.h:6, from include/linux/bitops.h:6, from include/linux/log2.h:12, from include/asm-generic/div64.h:55, from ./arch/sh/include/generated/asm/div64.h:1, from include/linux/math.h:6, from include/linux/delay.h:22, from drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:6: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function 'mtk_hdmi_pll_calculate_params': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:317:20: note: in expansion of macro 'BIT' 317 | if ((pcw / BIT(32)) > 1) { | ^~~ >> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:317:18: warning: division by zero [-Wdiv-by-zero] 317 | if ((pcw / BIT(32)) > 1) { | ^ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:319:27: note: in expansion of macro 'BIT' 319 | } else if ((pcw / BIT(32)) == 1) { | ^~~ drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:319:25: warning: division by zero [-Wdiv-by-zero] 319 | } else if ((pcw / BIT(32)) == 1) { | ^ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:321:36: note: in expansion of macro 'BIT' 321 | fbkdiv_low = pcw % BIT(32); | ^~~ drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:321:34: warning: division by zero [-Wdiv-by-zero] 321 | fbkdiv_low = pcw % BIT(32); | ^ Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for COMMON_CLK Depends on [n]: !HAVE_LEGACY_CLK [=y] Selected by [m]: - VIDEO_TC358746 [=m] && MEDIA_SUPPORT [=m] && VIDEO_DEV [=m] && PM [=y] && I2C [=m] vim +317 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c 234 235 static int mtk_hdmi_pll_calculate_params(struct clk_hw *hw, unsigned long rate, 236 unsigned long parent_rate) 237 { 238 int ret; 239 unsigned long long tmds_clk; 240 unsigned long long pixel_clk; 241 /* pll input source frequency */ 242 unsigned long long da_hdmitx21_ref_ck; 243 /* ICO output clk */ 244 unsigned long long ns_hdmipll_ck; 245 /* source clk for Display digital */ 246 unsigned long long ad_hdmipll_pixel_ck; 247 unsigned char digital_div; 248 unsigned long long pcw; 249 unsigned char txprediv; 250 unsigned char txposdiv; 251 unsigned char fbkdiv_high; 252 unsigned long fbkdiv_low; 253 unsigned char posdiv1; 254 unsigned char posdiv2; 255 /* prediv is always 1 */ 256 unsigned char prediv = 1; 257 /* fbkdiv_hs3 is always 1 */ 258 unsigned char fbkdiv_hs3 = 1; 259 int i = 0; 260 unsigned char txpredivs[4] = { 2, 4, 6, 12 }; 261 262 pixel_clk = rate; 263 tmds_clk = pixel_clk; 264 265 if (tmds_clk < 25000000 || tmds_clk > 594000000) 266 return -EINVAL; 267 268 /* in Hz */ 269 da_hdmitx21_ref_ck = 26000000UL; 270 271 /* TXPOSDIV stage treatment: 272 * 0M < TMDS clk < 54M /8 273 * 54M <= TMDS clk < 148.35M /4 274 * 148.35M <=TMDS clk < 296.7M /2 275 * 296.7 <=TMDS clk <= 594M /1 276 */ 277 if (tmds_clk < 54000000UL) 278 txposdiv = 8; 279 else if (tmds_clk >= 54000000UL && tmds_clk < 148350000UL) 280 txposdiv = 4; 281 else if (tmds_clk >= 148350000UL && tmds_clk < 296700000UL) 282 txposdiv = 2; 283 else if (tmds_clk >= 296700000UL && tmds_clk <= 594000000UL) 284 txposdiv = 1; 285 else 286 return -EINVAL; 287 288 /* calculate txprediv: can be 2, 4, 6, 12 289 * ICO clk = 5*TMDS_CLK*TXPOSDIV*TXPREDIV 290 * ICO clk constraint: 5G =< ICO clk <= 12G 291 */ 292 for (i = 0; i < ARRAY_SIZE(txpredivs); i++) { 293 ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i]; 294 if (ns_hdmipll_ck >= 5000000000UL && 295 ns_hdmipll_ck <= 12000000000UL) 296 break; 297 } 298 if (i == (ARRAY_SIZE(txpredivs) - 1) && 299 (ns_hdmipll_ck < 5000000000UL || ns_hdmipll_ck > 12000000000UL)) { 300 return -EINVAL; 301 } 302 if (i == ARRAY_SIZE(txpredivs)) 303 return -EINVAL; 304 305 txprediv = txpredivs[i]; 306 307 /* PCW calculation: FBKDIV 308 * formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3; 309 * RG_HDMITXPLL_FBKDIV[32:0]: 310 * [32,24] 9bit integer, [23,0]:24bit fraction 311 */ 312 pcw = ns_hdmipll_ck; 313 pcw = pcw << PCW_DECIMAL_WIDTH; 314 pcw = pcw / da_hdmitx21_ref_ck; 315 pcw = pcw / fbkdiv_hs3; 316 > 317 if ((pcw / BIT(32)) > 1) { 318 return -EINVAL; 319 } else if ((pcw / BIT(32)) == 1) { 320 fbkdiv_high = 1; 321 fbkdiv_low = pcw % BIT(32); 322 } else { 323 fbkdiv_high = 0; 324 fbkdiv_low = pcw; 325 } 326 327 /* posdiv1: 328 * posdiv1 stage treatment according to color_depth: 329 * 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5, 330 * 36bit -> posdiv1 /15, 48bit -> posdiv1 /10 331 */ 332 posdiv1 = 10; 333 posdiv2 = 1; 334 ad_hdmipll_pixel_ck = (ns_hdmipll_ck / 10) / 1; 335 336 /* Digital clk divider, max /32 */ 337 digital_div = ad_hdmipll_pixel_ck / pixel_clk; 338 if (!(digital_div <= 32 && digital_div >= 1)) 339 return -EINVAL; 340 341 ret = mtk_hdmi_pll_set_hw(hw, prediv, fbkdiv_high, fbkdiv_low, 342 fbkdiv_hs3, posdiv1, posdiv2, txprediv, 343 txposdiv, digital_div); 344 if (ret) 345 return -EINVAL; 346 347 return 0; 348 } 349 -- 0-DAY CI Kernel Test Service https://01.org/lkp