From: Pierre Gondois <pierre.gondois@arm.com>
To: linux-kernel@vger.kernel.org
Cc: Pierre Gondois <pierre.gondois@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Aswani Reddy <aswani.reddy@samsung.com>,
Shashank Prashar <s.prashar@samsung.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org
Subject: [PATCH v4 2/2] arm64: dts: fsd: Update cache properties
Date: Wed, 23 Nov 2022 10:24:45 +0100 [thread overview]
Message-ID: <20221123092449.88097-3-pierre.gondois@arm.com> (raw)
In-Reply-To: <20221123092449.88097-1-pierre.gondois@arm.com>
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/tesla/fsd.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index f35bc5a288c2..d58d47618c95 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -281,6 +281,8 @@ cpucl2_3: cpu@203 {
cpucl_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
cache-size = <0x400000>;
cache-line-size = <64>;
cache-sets = <4096>;
--
2.25.1
next prev parent reply other threads:[~2022-11-23 9:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-23 9:24 [PATCH v4 0/2] arm64: dts: [exynos|fsd]: " Pierre Gondois
2022-11-23 9:24 ` [PATCH v4 1/2] arm64: dts: exynos: " Pierre Gondois
2022-11-23 9:24 ` Pierre Gondois [this message]
2022-11-27 21:25 ` [PATCH v4 0/2] arm64: dts: [exynos|fsd]: " Krzysztof Kozlowski
2022-11-27 21:26 ` Krzysztof Kozlowski
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