From: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
To: unlisted-recipients:; (no To-header on input)
Cc: nathan.morrison@timesys.com, greg.malysa@timesys.com,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-mtd@lists.infradead.org (open list:SPI NOR SUBSYSTEM),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 2/3] mtd: spi-nor: Add additional octal-mode flags to be checked during SFDP
Date: Thu, 1 Dec 2022 13:15:31 -0500 [thread overview]
Message-ID: <20221201181532.255449-3-nathan.morrison@timesys.com> (raw)
In-Reply-To: <20221201181532.255449-1-nathan.morrison@timesys.com>
This adds some support for searching a chips SFDP table for:
read commands: 1S-8S-8S
program commands: 1S-1S-8S, 1S-8S-8S
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
---
drivers/mtd/spi-nor/core.c | 21 ++++++++++++++++++++-
drivers/mtd/spi-nor/core.h | 9 ++++++---
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index bee8fc4c9f07..7475a9a22881 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2335,7 +2335,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
struct spi_nor_erase_map *map = ¶ms->erase_map;
- const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
+ const u16 no_sfdp_flags = nor->info->no_sfdp_flags;
u8 i, erase_mask;
if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
@@ -2359,6 +2359,25 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
SNOR_PROTO_1_1_8);
}
+ if (no_sfdp_flags & SPI_NOR_OCTAL_READ_1_8_8) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_8_8],
+ 0, 16, SPINOR_OP_READ_1_8_8,
+ SNOR_PROTO_1_8_8);
+ }
+
+ if (no_sfdp_flags & SPI_NOR_OCTAL_PP) {
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_8;
+ spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_8],
+ SPINOR_OP_PP_1_1_8, SNOR_PROTO_1_1_8);
+ }
+
+ if (no_sfdp_flags & SPI_NOR_OCTAL_PP_1_8_8) {
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_1_8_8;
+ spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8],
+ SPINOR_OP_PP_1_8_8, SNOR_PROTO_1_8_8);
+ }
+
if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 85b0cf254e97..25a0d4f1850b 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -508,14 +508,17 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(7)
#define SPI_NOR_NO_FR BIT(8)
- u8 no_sfdp_flags;
+ u16 no_sfdp_flags;
#define SPI_NOR_SKIP_SFDP BIT(0)
#define SECT_4K BIT(1)
#define SPI_NOR_DUAL_READ BIT(3)
#define SPI_NOR_QUAD_READ BIT(4)
#define SPI_NOR_OCTAL_READ BIT(5)
-#define SPI_NOR_OCTAL_DTR_READ BIT(6)
-#define SPI_NOR_OCTAL_DTR_PP BIT(7)
+#define SPI_NOR_OCTAL_READ_1_8_8 BIT(6)
+#define SPI_NOR_OCTAL_PP BIT(7)
+#define SPI_NOR_OCTAL_PP_1_8_8 BIT(8)
+#define SPI_NOR_OCTAL_DTR_READ BIT(9)
+#define SPI_NOR_OCTAL_DTR_PP BIT(10)
u8 fixup_flags;
#define SPI_NOR_4B_OPCODES BIT(0)
--
2.30.2
next prev parent reply other threads:[~2022-12-01 18:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 18:15 [PATCH 0/3] mtd: spi-nor: Extend SFDP to support additional octal modes as per latest JEDEC standard Nathan Barrett-Morrison
2022-12-01 18:15 ` [PATCH 1/3] mtd: spi-nor: Extend SFDP 4byte address instruction lookup table with new octal modes as per JEDEC JESD216F Nathan Barrett-Morrison
2022-12-01 18:15 ` Nathan Barrett-Morrison [this message]
2022-12-01 18:15 ` [PATCH 3/3] mtd: spi-nor: Add support for IS25LX256 operating in 1S-1S-8S mode Nathan Barrett-Morrison
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