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[66.187.233.206]) by smtp.gmail.com with ESMTPSA id y3-20020ac85243000000b00398313f286dsm281671qtn.40.2022.12.13.10.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 10:18:56 -0800 (PST) Date: Tue, 13 Dec 2022 13:18:55 -0500 From: Eric Chanudet To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Halaney , Brian Masney Subject: Re: [PATCH 1/2] arm64: dts: qcom: pm8450a: add rtc node Message-ID: <20221213181855.ylkb3dglw3bkwor5@echanude> References: <20221213005539.1133443-1-echanude@redhat.com> <219F5CF2-BA91-4749-A32C-84BCF541ECE0@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <219F5CF2-BA91-4749-A32C-84BCF541ECE0@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Dec 13, 2022 at 04:18:00AM +0300, Dmitry Baryshkov wrote: > >diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi > >index 34fc72896761..af761dbfbc66 100644 > >--- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi > >+++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi > >@@ -13,6 +13,14 @@ pm8450a: pmic@0 { > > #address-cells = <1>; > > #size-cells = <0>; > > > >+ rtc@6000 { > >+ compatible = "qcom,pm8941-rtc"; > >+ reg = <0x6000>; > >+ reg-names = "rtc", "alarm"; > >+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; > > > 0x60? Checking downstream it uses 0x61 for the ppid. This is also the case for all other descriptions of that RTC I could find. On the other hand, that does not describe the "alarm" register bank at 0x6100. Should it be added, if anything to match reg-names? I tried a quick test of the alarm on sa8540p-ride: $ echo $(date '+%s' -d '+ 10 seconds') > /sys/class/rtc/rtc0/wakealarm It logged the interrupt: 172: 3 0 0 0 0 0 0 0 pmic_arb 101777441 Edge pm8xxx_rtc_alarm -- Eric Chanudet