From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC3E6C4332F for ; Thu, 15 Dec 2022 07:02:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230009AbiLOHCJ (ORCPT ); Thu, 15 Dec 2022 02:02:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229898AbiLOHA0 (ORCPT ); Thu, 15 Dec 2022 02:00:26 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D61CF6A74E for ; Wed, 14 Dec 2022 22:57:52 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id p124-20020a257482000000b0073867e191adso254035ybc.9 for ; Wed, 14 Dec 2022 22:57:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=UOnqeDp13LfEOFsCqAa7xRaY3KCwcqHjVuXRVdFzI5g=; b=hgMGqwvgV2j4YKvScrHs+3nqFXQYDg7tz+jo4gDb54Tj27Baady1eBQLvC0awG721v OKWps8K+hG+bjim9HVHr/PJmQCuzmdAkx0HFzWwRPHQbQoo8vLptBI0cadotf8u5xYyr 8Z04U/PFmZ2baHihDJllRJqJG3Nf7qkT2YQCSDCPoPhcLLeLizjR0p/z9wz8WRA43cU4 Y0uj3KkWLOhX8s3ZjzsxvsqazoA9Ovd5gu49aZJJnWNmPWKkDibLYUYduGV7nP/7O0y/ WxzpQD4EZpDC/gK5GC2/NceqONzhweliSfGybfp45nKYw1XVU+MQ7r4blUdql468jzGf +AIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=UOnqeDp13LfEOFsCqAa7xRaY3KCwcqHjVuXRVdFzI5g=; b=cOIcMCyBY/P0CzbKMYcDF94w7gNaHM6tvL4kyIe+5fvFe6/hcz7gpJk3IN04P1sylr BsnmWtv479/RSrNvYwH1a+GRZ9n2R8o8w+1N7JRKBSugUfsx4PwVp4ennk2kbBFNZJRD zPRs1/mPnwUmUHfRkneaJ8FgcCisouhg/QtnjKR4h06vQ9PRRBpNgPr59ZXY5Q7ibJ8O /L2OGPHBEG4c6auG4kndhak4J78yYSjp7lw6l6LSD+I6D137F+IjWyxUnsCG9i4Nqz0v 8Tz1RMyrLfeWbTnJyGkaTmBDBvYnTkIQWjdAfF2v2mmZKNzbdj6HoT4UVhnxQfUXr8sp Qxvw== X-Gm-Message-State: AFqh2kpKJxZ6RpWbecQLiruP2cJU3e0UxhhoHj0x05kgj51ffAy0S5w3 EKETFcN+Rrv68LnWagovpOP12u494xD8 X-Google-Smtp-Source: AMrXdXt+f46CweYBVuAwHOjgaIS84KbdrKZiO6o/n5jXW3JTzVH0WM6K8wrBEzICMp+oLMehQcQMvPSNA6j0 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:c7dc:d96f:4f9:f59d]) (user=irogers job=sendgmr) by 2002:a5b:2c1:0:b0:734:d6ab:d28c with SMTP id h1-20020a5b02c1000000b00734d6abd28cmr347095ybp.589.1671087471851; Wed, 14 Dec 2022 22:57:51 -0800 (PST) Date: Wed, 14 Dec 2022 22:55:04 -0800 In-Reply-To: <20221215065510.1621979-1-irogers@google.com> Message-Id: <20221215065510.1621979-18-irogers@google.com> Mime-Version: 1.0 References: <20221215065510.1621979-1-irogers@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Subject: [PATCH v1 26/32] perf vendor events intel: Refresh skylake metrics and events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Kan Liang , Xing Zhengjun , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Garry , Stephane Eranian , Perry Taylor , Caleb Biggers , Ian Rogers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the skylake metrics and events using the new tooling from: https://github.com/intel/perfmon The metrics are unchanged but the formulas differ due to parentheses, use of exponents and removal of redundant operations like "* 1". The events are unchanged but unused json values are removed. The formatting changes increase consistency across the json files. Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/skylake/cache.json | 660 ------------------ .../arch/x86/skylake/floating-point.json | 14 - .../pmu-events/arch/x86/skylake/frontend.json | 109 --- .../pmu-events/arch/x86/skylake/memory.json | 358 ---------- .../pmu-events/arch/x86/skylake/other.json | 4 - .../pmu-events/arch/x86/skylake/pipeline.json | 192 ----- .../arch/x86/skylake/skl-metrics.json | 155 ++-- .../arch/x86/skylake/uncore-cache.json | 18 - .../arch/x86/skylake/uncore-other.json | 31 +- .../arch/x86/skylake/virtual-memory.json | 56 -- 10 files changed, 103 insertions(+), 1494 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf= /pmu-events/arch/x86/skylake/cache.json index c3183819bf52..1538ddb5752f 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "L1D data line replacements", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Number of times a request needed a FB (Fill = Buffer) entry but there was no entry available for it. A request includes c= acheable/uncacheable demands that are load, store or SW prefetch instructio= ns.", @@ -21,8 +17,6 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts duration of L1D miss outstanding, tha= t is each cycle number of Fill Buffers (FB) outstanding required by Demand = Reads. FB either is held by demand loads, or it is held by non-demand loads= and gets hit at least once by demand. The valid outstanding interval is de= fined until the FB deallocation by one of the following ways: from FB alloc= ation, if FB is allocated by demand from the demand Hit FB, if it is alloca= ted by hardware or software prefetch.Note: In the L1D, a Demand Read contai= ns cacheable or noncacheable demand loads, including ones causing cache-lin= e splits and reads due to page walks resulted from any request type.", @@ -31,8 +25,6 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -43,8 +35,6 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -53,8 +43,6 @@ }, { "BriefDescription": "L2 cache lines filling L2", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -63,8 +51,6 @@ }, { "BriefDescription": "Counts the number of lines that are evicted b= y L2 cache when triggered by an L2 cache fill. Those lines are in Modified = state. Modified lines are written back to L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "SampleAfterValue": "200003", @@ -72,8 +58,6 @@ }, { "BriefDescription": "Counts the number of lines that are silently = dropped by L2 cache when triggered by an L2 cache fill. These lines are typ= ically in Shared or Exclusive state. A non-threaded event.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "SampleAfterValue": "200003", @@ -81,8 +65,6 @@ }, { "BriefDescription": "Counts the number of lines that have been har= dware prefetched but not used and now evicted by L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_HWPF", "SampleAfterValue": "200003", @@ -90,8 +72,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L2_LINES_OUT.USELESS_HWPF", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_PREF", "SampleAfterValue": "200003", @@ -99,8 +79,6 @@ }, { "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -109,8 +87,6 @@ }, { "BriefDescription": "Demand Data Read requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -119,8 +95,6 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Demand requests that miss L2 cache.", @@ -129,8 +103,6 @@ }, { "BriefDescription": "Demand requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Demand requests to L2 cache.", @@ -139,8 +111,6 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts the total number of requests from the= L2 hardware prefetchers.", @@ -149,8 +119,6 @@ }, { "BriefDescription": "RFO requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -159,8 +127,6 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -169,8 +135,6 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -179,8 +143,6 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", @@ -189,8 +151,6 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -199,8 +159,6 @@ }, { "BriefDescription": "All requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "All requests that miss L2 cache.", @@ -209,8 +167,6 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that hit L2 cache.", @@ -219,8 +175,6 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that miss L2 cache.", @@ -229,8 +183,6 @@ }, { "BriefDescription": "All L2 requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "All L2 requests.", @@ -239,8 +191,6 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -249,8 +199,6 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -259,8 +207,6 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -269,8 +215,6 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", @@ -280,8 +224,6 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", @@ -291,8 +233,6 @@ }, { "BriefDescription": "All retired load instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -302,24 +242,18 @@ }, { "BriefDescription": "All retired store instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", - "L1_Hit_Indication": "1", "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x82" }, { "BriefDescription": "All retired memory instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ANY", - "L1_Hit_Indication": "1", "PEBS": "1", "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", "SampleAfterValue": "2000003", @@ -327,8 +261,6 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -338,8 +270,6 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -350,12 +280,9 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", - "L1_Hit_Indication": "1", "PEBS": "1", "PublicDescription": "Counts retired store instructions that split= across a cacheline boundary.", "SampleAfterValue": "100003", @@ -363,8 +290,6 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -375,12 +300,9 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "L1_Hit_Indication": "1", "PEBS": "1", "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", @@ -388,8 +310,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 and cross-core snoop hits in on-pkg core cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -400,8 +320,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were HitM responses from shared L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -412,8 +330,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -423,8 +339,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were hits in L3 without snoops required", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -435,8 +349,6 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -446,8 +358,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were load missed L1 but hit FB due to preceding miss to the same cache line= with data not ready", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -458,8 +368,6 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -470,8 +378,6 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -482,8 +388,6 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -494,8 +398,6 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -506,8 +408,6 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -518,8 +418,6 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -530,8 +428,6 @@ }, { "BriefDescription": "Demand and prefetch data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -540,8 +436,6 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", @@ -550,8 +444,6 @@ }, { "BriefDescription": "Cacheable and noncachaeble code read requests= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", @@ -560,8 +452,6 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -570,8 +460,6 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -580,8 +468,6 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "Counts the number of cases when the offcore = requests buffer cannot take more entries for the core. This can happen when= the superqueue does not contain eligible entries, or when L1D writeback pe= nding FIFO requests is full.Note: Writeback pending FIFO has six entries.", @@ -590,8 +476,6 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", @@ -600,8 +484,6 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -611,8 +493,6 @@ }, { "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -622,8 +502,6 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -633,8 +511,6 @@ }, { "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO"= , @@ -644,8 +520,6 @@ }, { "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", @@ -654,8 +528,6 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding Dem= and Data Read transactions in the super queue (SQ) every cycle. A transacti= on is considered to be in the Offcore outstanding state between L2 miss and= transaction completion sent to requestor. See the corresponding Umask unde= r OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the = promotion point.", @@ -664,8 +536,6 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -674,8 +544,6 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of offcore outstanding RFO= (store) transactions in the super queue (SQ) every cycle. A transaction is= considered to be in the Offcore outstanding state between L2 miss and tran= saction completion sent to requestor (SQ de-allocation). See corresponding = Umask under OFFCORE_REQUESTS.", @@ -684,8 +552,6 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -694,2072 +560,1554 @@ }, { "BriefDescription": "Counts all demand code readshave any response= type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4001C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2001C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x801C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1001C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x401C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_= HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0020004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400020004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200020004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80020004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100020004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HI= T", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40020004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data readshave any response typ= e.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4001C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2001C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x801C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1001C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x401C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0080001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000080001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400080001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200080001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80080001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100080001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40080001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0040001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000040001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400040001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200040001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80040001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100040001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40040001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0100001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000100001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400100001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200100001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80100001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100100001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40100001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0400001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000400001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400400001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200400001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80400001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100400001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_= HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40400001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0020001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400020001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200020001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80020001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100020001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HI= T", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40020001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)have any = response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4001C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2001C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x801C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1001C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x401C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0080002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000080002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400080002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200080002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80080002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100080002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40080002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0040002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000040002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400040002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200040002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80040002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100040002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40040002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0100002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000100002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400100002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200100002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80100002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100100002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40100002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOO= P", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= TM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= T_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= T_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requestshave any response ty= pe.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x18000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC01C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4001C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2001C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x801C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1001C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x401C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC0028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x80028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x40028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Number of cache line split locks sent to unco= re.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "Counts the number of cache line split locks = sent to the uncore.", @@ -2768,8 +2116,6 @@ }, { "BriefDescription": "Number of PREFETCHNTA instructions executed."= , - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "SampleAfterValue": "2000003", @@ -2777,8 +2123,6 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "SampleAfterValue": "2000003", @@ -2786,8 +2130,6 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "SampleAfterValue": "2000003", @@ -2795,8 +2137,6 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/t= ools/perf/pmu-events/arch/x86/skylake/floating-point.json index d6cee5ae4402..eb83fa537e7d 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", @@ -31,8 +25,6 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -41,8 +33,6 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", @@ -51,8 +41,6 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", @@ -61,8 +49,6 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/p= erf/pmu-events/arch/x86/skylake/frontend.json index 8633ee406813..13ccf50db43d 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "PublicDescription": "This event counts the number of the Decode S= tream Buffer (DSB)-to-MITE switches including all misses because of missing= Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking= MITE requires two or three cycles delay.", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE sw= itch true penalty cycles. These cycles do not include uops routed through b= ecause of the switch itself, for example, when Instruction Decode Queue (ID= Q) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full= . SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) re= ceives Decode Stream Buffer (DSB) Sync-indication until receiving the first= MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops= being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Strea= m Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer = (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit follo= wed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which= no uops are delivered to the IDQ. Most often, such switches from the Decod= e Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", @@ -31,8 +25,6 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -40,13 +32,10 @@ "PEBS": "1", "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -54,13 +43,10 @@ "PEBS": "1", "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -68,39 +54,30 @@ "PEBS": "1", "PublicDescription": "Counts retired Instructions that experienced= iTLB (Instruction TLB) true miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", "MSRValue": "0x12", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", "MSRValue": "0x13", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -108,26 +85,20 @@ "PEBS": "2", "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", "MSRValue": "0x408006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -135,39 +106,30 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 16 cycles. During th= is period the front-end delivered no uops.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 2 cycles w= hich was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", "MSRValue": "0x400206", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", "MSRValue": "0x410006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -175,39 +137,30 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 2 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", "MSRIndex": "0x3F7", "MSRValue": "0x200206", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 3 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", "MSRIndex": "0x3F7", "MSRValue": "0x300206", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -215,52 +168,40 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 32 cycles. During th= is period the front-end delivered no uops.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", "MSRValue": "0x400406", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", "MSRValue": "0x420006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", "MSRValue": "0x404006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -268,13 +209,10 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 8 cycles. During thi= s period the front-end delivered no uops.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -282,13 +220,10 @@ "PEBS": "1", "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Cycles where a code line fetch is stalled du= e to an L1 instruction cache miss. The legacy decode pipeline works at a 16= Byte granularity.", @@ -297,8 +232,6 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "SampleAfterValue": "200003", @@ -306,8 +239,6 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "SampleAfterValue": "200003", @@ -315,8 +246,6 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "SampleAfterValue": "200003", @@ -324,8 +253,6 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -335,8 +262,6 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -346,8 +271,6 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -357,8 +280,6 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -368,8 +289,6 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -379,8 +298,6 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Countin= g includes uops that may 'bypass' the IDQ.", @@ -389,8 +306,6 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -400,8 +315,6 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. Counting includes uops that m= ay 'bypass' the IDQ. This also means that uops are not being delivered from= the Decode Stream Buffer (DSB).", @@ -410,8 +323,6 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -421,8 +332,6 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -432,8 +341,6 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE = and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenc= er (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -442,8 +349,6 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -454,8 +359,6 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -464,8 +367,6 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to R= esource Allocation Table (RAT) per thread adding 4 x when Resource Allocat= ion Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers = x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). C= ounting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) p= ipe serves the other thread. b. Resource Allocation Table (RAT) is stalled = for the thread (including uop drops and clear BE conditions). c. Instructi= on Decode Queue (IDQ) delivers four uops.", @@ -474,8 +375,6 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -485,8 +384,6 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -496,8 +393,6 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -507,8 +402,6 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -518,8 +411,6 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/skylake/memory.json b/tools/per= f/pmu-events/arch/x86/skylake/memory.json index 74ea4ccb4c9a..588ad6059a13 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/memory.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -32,8 +26,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_EVENTS", "SampleAfterValue": "2000003", @@ -41,8 +33,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEM", "SampleAfterValue": "2000003", @@ -50,8 +40,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an HLE execution aborted due= to incompatible memory type.", @@ -60,8 +48,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to hardware timer expiration.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -69,8 +55,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "SampleAfterValue": "2000003", @@ -78,8 +62,6 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -88,8 +70,6 @@ }, { "BriefDescription": "Number of times an HLE execution started.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region. Do= es not count nested transactions.", @@ -98,8 +78,6 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL089", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", @@ -109,8 +87,6 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -119,13 +95,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", "SampleAfterValue": "1009", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -134,13 +107,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", "SampleAfterValue": "20011", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -149,13 +119,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", "SampleAfterValue": "503", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -164,13 +131,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -179,13 +143,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", "SampleAfterValue": "100003", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -194,13 +155,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", "SampleAfterValue": "101", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -209,13 +167,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", "SampleAfterValue": "2003", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -224,13 +179,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", "SampleAfterValue": "50021", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Demand Data Read requests who miss L3 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", @@ -239,8 +191,6 @@ }, { "BriefDescription": "Cycles with at least 1 Demand Data Read reque= sts who miss L3 cache in the superQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -249,8 +199,6 @@ }, { "BriefDescription": "Counts number of Offcore outstanding Demand D= ata Read requests that miss L3 cache in the superQ every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD"= , "SampleAfterValue": "2000003", @@ -258,8 +206,6 @@ }, { "BriefDescription": "Cycles with at least 6 Demand Data Read reque= sts that miss L3 cache in the superQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", @@ -268,1064 +214,798 @@ }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20001C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000080004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000040004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000100004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFC400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103C400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x43C400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x23C400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0xBC400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DR= AM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x203C400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x13C400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x7C400004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC4000004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads", - 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"Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x203C400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x13C400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x7C400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC4000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x404000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x204000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x84000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NON_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x104000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_H= IT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x44000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= N_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000400002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000020002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x20001C8000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000088000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000048000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000108000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FFC408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103C408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x43C408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x23C408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0xBC408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x203C408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x13C408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x7C408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FC4008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x404008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x204008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x84008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2004008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x104008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x44008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000408000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000028000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -1335,8 +1015,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", @@ -1345,8 +1023,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", @@ -1355,8 +1031,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an RTM execution aborted due= to incompatible memory type.", @@ -1365,8 +1039,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to uncommon conditions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -1374,8 +1046,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Number of times an RTM execution aborted due= to HLE-unfriendly instructions.", @@ -1384,8 +1054,6 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -1394,8 +1062,6 @@ }, { "BriefDescription": "Number of times an RTM execution started.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region. Do= es not count nested transactions.", @@ -1404,8 +1070,6 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -1413,8 +1077,6 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupp= er instruction.", @@ -1423,8 +1085,6 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -1433,8 +1093,6 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -1443,8 +1101,6 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "PublicDescription": "Counts the number of times an HLE XACQUIRE i= nstruction was executed inside an RTM transactional region.", @@ -1453,8 +1109,6 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional reads or writes."= , - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY", "SampleAfterValue": "2000003", @@ -1462,8 +1116,6 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -1472,8 +1124,6 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -1482,8 +1132,6 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -1492,8 +1140,6 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -1502,8 +1148,6 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -1512,8 +1156,6 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf= /pmu-events/arch/x86/skylake/other.json index 8f4bc8892c47..9f3a9dffb807 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Number of hardware interrupts received by the= processor.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PublicDescription": "Counts the number of hardware interruptions = received by the processor.", @@ -10,8 +8,6 @@ "UMask": "0x1" }, { - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x09", "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/p= erf/pmu-events/arch/x86/skylake/pipeline.json index 79fda10ec4bb..cf35a535c2f6 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations. Accounts for integer and floating-point oper= ations.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -11,8 +9,6 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", @@ -21,8 +17,6 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -33,8 +27,6 @@ }, { "BriefDescription": "Conditional branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", @@ -45,8 +37,6 @@ }, { "BriefDescription": "Not taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", @@ -56,8 +46,6 @@ }, { "BriefDescription": "Far branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -68,8 +56,6 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", @@ -80,8 +66,6 @@ }, { "BriefDescription": "Return instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", @@ -92,8 +76,6 @@ }, { "BriefDescription": "Taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", @@ -104,8 +86,6 @@ }, { "BriefDescription": "Not taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", @@ -115,8 +95,6 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", @@ -124,8 +102,6 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -135,8 +111,6 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -146,8 +120,6 @@ }, { "BriefDescription": "Mispredicted direct and indirect near call in= structions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -157,8 +129,6 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -167,8 +137,6 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -176,8 +144,6 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -186,8 +152,6 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -195,8 +159,6 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -204,8 +166,6 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", - "Counter": "Fixed counter 2", - "CounterHTOff": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the four (eight when Hyperthre= ading is disabled) programmable counters available for other events. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -213,8 +173,6 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -223,8 +181,6 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -232,8 +188,6 @@ }, { "BriefDescription": "Counts when there is a transition from ring 1= , 2 or 3 to ring 0.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x3C", @@ -243,8 +197,6 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the four (eight when Hyperthreading is disabled) programmable counters a= vailable for other events.", "SampleAfterValue": "2000003", @@ -253,16 +205,12 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -271,16 +219,12 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -289,8 +233,6 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -299,8 +241,6 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -309,8 +249,6 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -319,8 +257,6 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -329,8 +265,6 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "CounterMask": "20", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -339,8 +273,6 @@ }, { "BriefDescription": "Total execution stalls.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -349,8 +281,6 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -359,8 +289,6 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -369,8 +297,6 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -379,8 +305,6 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -389,8 +313,6 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= outstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "SampleAfterValue": "2000003", @@ -398,8 +320,6 @@ }, { "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", @@ -408,8 +328,6 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", @@ -418,8 +336,6 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -428,8 +344,6 @@ }, { "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "CounterHTOff": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "Counts the number of instructions retired fr= om execution. For instructions that consist of multiple micro-ops, Counts t= he retirement of the last micro-op of the instruction. Counting continues d= uring hardware interrupts, traps, and inside interrupt handlers. Notes: INS= T_RETIRED.ANY is counted by a designated fixed counter, leaving the four (e= ight when Hyperthreading is disabled) programmable counters available for o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter and it= is an architectural performance event. Counting: Faulting executions of GE= TSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "SampleAfterValue": "2000003", @@ -437,8 +351,6 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -447,8 +359,6 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.NOP", @@ -458,8 +368,6 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "Counter": "1", - "CounterHTOff": "1", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -470,8 +378,6 @@ }, { "BriefDescription": "Number of cycles using always true condition = applied to PEBS instructions retired event.", - "Counter": "0,2,3", - "CounterHTOff": "0,2,3", "CounterMask": "10", "Errata": "SKL091, SKL044", "EventCode": "0xC0", @@ -484,8 +390,6 @@ }, { "BriefDescription": "Cycles the issue-stage is waiting for front-e= nd to fetch from resteered path following branch misprediction or machine c= lear events.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "SampleAfterValue": "2000003", @@ -493,8 +397,6 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Core cycles the Resource allocator was stall= ed due to recovery from an earlier branch misprediction or machine clear ev= ent.", @@ -504,8 +406,6 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", @@ -513,8 +413,6 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -523,8 +421,6 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -533,8 +429,6 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts false dependencies in MOB when the pa= rtial comparison upon loose net check and dependency was resolved by the En= hanced Loose net mechanism. This may not result in high performance penalti= es. Loose net checks can fail when loads and stores are 4k aliased.", @@ -543,8 +437,6 @@ }, { "BriefDescription": "Demand load dispatches that hit L1D fill buff= er (FB) allocated for software prefetch.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -553,8 +445,6 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -564,8 +454,6 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -575,8 +463,6 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA8", "EventName": "LSD.UOPS", "PublicDescription": "Number of uops delivered to the back-end by = the LSD(Loop Stream Detector).", @@ -585,8 +471,6 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -596,8 +480,6 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -606,8 +488,6 @@ }, { "BriefDescription": "Number of times a microcode assist is invoked= by HW other than FP-assist. Examples include AD (page Access Dirty) and AV= X* related assists.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY", "SampleAfterValue": "100003", @@ -615,8 +495,6 @@ }, { "BriefDescription": "Cycles where the pipeline is stalled due to s= erializing operations.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", "PublicDescription": "This event counts cycles during which the mi= crocode scoreboard stalls happen.", @@ -625,8 +503,6 @@ }, { "BriefDescription": "Resource-related stall cycles", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Counts resource-related stall cycles.", @@ -635,8 +511,6 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -645,8 +519,6 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -655,8 +527,6 @@ }, { "BriefDescription": "Number of retired PAUSE instructions (that do= not end up with a VMExit to the VMM; TSX aborted Instructions may be count= ed). This event is not supported on first SKL and KBL products.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.PAUSE_INST", "SampleAfterValue": "2000003", @@ -664,8 +534,6 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for the thread.; Note: In ST-mode, not active thread s= hould drive 0. This is usually caused by severely costly branch mispredicti= ons, or allocator/FE issues.", @@ -674,8 +542,6 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -687,8 +553,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -697,8 +561,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -707,8 +569,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 2.", @@ -717,8 +577,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 3.", @@ -727,8 +585,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 4.", @@ -737,8 +593,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -747,8 +601,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -757,8 +609,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 7.", @@ -767,8 +617,6 @@ }, { "BriefDescription": "Number of uops executed on the core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -777,8 +625,6 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -787,8 +633,6 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -797,8 +641,6 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -807,8 +649,6 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -817,8 +657,6 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", @@ -828,8 +666,6 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -839,8 +675,6 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -850,8 +684,6 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -861,8 +693,6 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -872,8 +702,6 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -884,8 +712,6 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -894,8 +720,6 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -904,8 +728,6 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -914,8 +736,6 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -923,8 +743,6 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -935,8 +753,6 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", @@ -945,8 +761,6 @@ }, { "BriefDescription": "Number of macro-fused uops retired. (non prec= ise)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PublicDescription": "Counts the number of macro-fused uops retire= d. (non precise)", @@ -955,8 +769,6 @@ }, { "BriefDescription": "Retirement slots used.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PublicDescription": "Counts the retirement slots used.", @@ -965,8 +777,6 @@ }, { "BriefDescription": "Cycles without actually retired uops.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -977,8 +787,6 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tool= s/perf/pmu-events/arch/x86/skylake/skl-metrics.json index f138b9836b51..972d3744c2c8 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -41,7 +41,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", - "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.AL= L_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS"= , + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteer= s_group", "MetricName": "tma_mispredicts_resteers", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", @@ -49,7 +49,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES /= CLKS", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / C= LKS", "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteer= s_group", "MetricName": "tma_clears_resteers", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sa= mple with: INT_MISC.CLEAR_RESTEER_CYCLES", @@ -120,7 +120,7 @@ }, { "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * = ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLE= S)) / SLOTS", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * = (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)= ) / SLOTS", "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", @@ -128,7 +128,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", - "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.AL= L_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_b= ad_speculation_group", "MetricName": "tma_branch_mispredicts", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", @@ -144,7 +144,7 @@ }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((I= NT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES))= / SLOTS", + "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (IN= T_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) /= SLOTS", "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", @@ -152,7 +152,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUN= D_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + = tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) = * tma_backend_bound", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND= _ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + t= ma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * = tma_backend_bound", "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_g= roup", "MetricName": "tma_memory_bound", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", @@ -198,7 +198,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU spent handling cache misses due to lock operations", - "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS= .ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (= 9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTA= NDING.CYCLES_WITH_DEMAND_RFO))) / CLKS", + "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS= .ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 = * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTAND= ING.CYCLES_WITH_DEMAND_RFO))) / CLKS", "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", "MetricName": "tma_lock_latency", "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS", @@ -230,7 +230,7 @@ }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", - "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.= FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (ME= M_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_= FULL\\,cmask\\=3D1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.S= TALLS_L2_MISS) / CLKS)", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cm= ask\\=3D1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_M= ISS) / CLKS)", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_mem= ory_bound_group", "MetricName": "tma_l2_bound", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -246,7 +246,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", - "MetricExpr": "((18.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIR= ED.XSNP_HITM + (16.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MI= SS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS= ", + "MetricExpr": "(18.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED= .XSNP_HITM + 16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) = * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_g= roup", "MetricName": "tma_contested_accesses", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", @@ -254,7 +254,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", - "MetricExpr": "(16.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRE= D.XSNP_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2)= / CLKS", + "MetricExpr": "16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.= XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / C= LKS", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", "MetricName": "tma_data_sharing", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS", @@ -262,7 +262,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited)", - "MetricExpr": "(6.5 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT= * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS", + "MetricExpr": "6.5 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT *= (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "PublicDescription": "This metric represents fraction of cycles wi= th demand load accesses that hit the L3 cache under unloaded scenarios (pos= sibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L= 3 hits) will improve the latency; reduce contention with sibling physical c= ores and increase performance. Note the value of this node may overlap wit= h its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", @@ -270,7 +270,7 @@ }, { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", - "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on e= lse OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", "MetricName": "tma_sq_full", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). The Super Queue is used for = requests to access the L2 cache or to go out to the Uncore.", @@ -278,7 +278,7 @@ }, { "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACT= IVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bou= nd)", + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIV= ITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound"= , "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_gr= oup", "MetricName": "tma_dram_bound", "PublicDescription": "This metric estimates how often the CPU was = stalled on accesses to external memory (DRAM) by loads. Better caching can = improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED= .L3_MISS_PS", @@ -310,7 +310,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", - "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_INST_RETIRED.LOC= K_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOAD= S / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_RE= QUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_= LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / M= EM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group"= , "MetricName": "tma_store_latency", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full)", @@ -318,7 +318,7 @@ }, { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", - "MetricExpr": "(22 * Average_Frequency) * OFFCORE_RESPONSE.DEMAND_= RFO.L3_HIT.SNOOP_HITM / CLKS", + "MetricExpr": "22 * Average_Frequency * OFFCORE_RESPONSE.DEMAND_RF= O.L3_HIT.SNOOP_HITM / CLKS", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_boun= d_group", "MetricName": "tma_false_sharing", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT= _RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", @@ -372,7 +372,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related)", - "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_P= ORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIV= IDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)= ) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTI= L) / CLKS", + "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_= PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIV= IDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY e= lse (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) = / CLKS)", "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", "MetricName": "tma_ports_utilization", "PublicDescription": "This metric estimates fraction of cycles the= CPU performance was potentially limited due to Core computation issues (no= n divider-related). Two distinct categories can be attributed into this me= tric: (1) heavy data-dependency among contiguous instructions would manifes= t in this metric - such cases are often referred to as low Instruction Leve= l Parallelism (ILP). (2) Contention on some hardware execution unit other t= han Divider. For example; when there are too many multiply operations.", @@ -427,7 +427,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT= .PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 *= CORE_CLKS)", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT= .PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOT= S", "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", "MetricName": "tma_alu_op_utilization", "ScaleUnit": "100%" @@ -483,7 +483,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Store operations", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", + "MetricExpr": "tma_port_4", "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", "MetricName": "tma_store_op_utilization", "ScaleUnit": "100%" @@ -622,7 +622,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ= .MS_UOPS / SLOTS", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.M= S_UOPS / SLOTS", "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", "MetricName": "tma_microcode_sequencer", "PublicDescription": "This metric represents fraction of slots the= CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The M= S is used for CISC instructions not supported by the default decoders (like= repeat move strings; or CPUID); or by microcode assists used to address so= me operation modes (like in Floating Point assists). These cases can often = be avoided. Sample with: IDQ.MS_UOPS", @@ -652,19 +652,19 @@ }, { "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_boun= d / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_stor= e_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma= _l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1= _bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (= tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_spli= t_loads + tma_store_fwd_blk)) ", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound /= (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_b= ound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_= hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_boun= d + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k= _aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_load= s + tma_store_fwd_blk))", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "Memory_Bandwidth" }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound = / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_= bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing = + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tm= a_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore", "MetricName": "Memory_Latency" }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_boun= d + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + = tma_false_sharing + tma_split_stores + tma_store_latency))) ", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_= dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fw= d_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound += tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_= false_sharing + tma_split_stores + tma_store_latency)))", "MetricGroup": "Mem;MemoryTLB;Offcore", "MetricName": "Memory_Data_TLBs" }, @@ -737,32 +737,32 @@ }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARIT= H_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBL= E + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.2= 56B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_C= LKS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", "MetricGroup": "Flops;Ret", "MetricName": "FLOPc" }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_IN= ST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_= ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_D= OUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_AR= ITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOU= BLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "FP_Arith_Utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_= GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", - "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_= core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else= 0", + "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma= _core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 els= e 0)", "MetricGroup": "Cor;SMT", "MetricName": "Core_Bound_Likely" }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", - "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHAL= TED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else = (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTE= D.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CP= U_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, @@ -804,13 +804,13 @@ }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCAL= AR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRE= D.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_A= RITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACK= ED_SINGLE)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SI= NGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_I= NST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SIN= GLE)", "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_S= INGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_= PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RE= TIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SI= NGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PA= CKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETI= RED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", "MetricGroup": "Flops;InsType", "MetricName": "IpArith", "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." @@ -905,7 +905,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_= mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache= _misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_R= ETIRED.ALL_BRANCHES", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RE= TIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts", "MetricName": "Branch_Misprediction_Cost" }, @@ -947,55 +947,55 @@ }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY"= , + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "L1MPKI" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.AN= Y", "MetricGroup": "CacheMisses;Mem", "MetricName": "L1MPKI_Load" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY"= , + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", "MetricGroup": "Backend;CacheMisses;Mem", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem;Offcore", "MetricName": "L2MPKI_All" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.A= NY", "MetricGroup": "CacheMisses;Mem", "MetricName": "L2MPKI_Load" }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST= _RETIRED.ANY", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "L2HPKI_All" }, { "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.AN= Y", "MetricGroup": "CacheMisses;Mem", "MetricName": "L2HPKI_Load" }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY"= , + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "L3MPKI" }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "FB_HPKI" }, @@ -1008,25 +1008,25 @@ }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, @@ -1056,19 +1056,19 @@ }, { "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, { "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", - "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duratio= n_time", + "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", "MetricGroup": "Power;Summary", "MetricName": "Average_Frequency" }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARI= TH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUB= LE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.= 256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 10000= 00000) / duration_time", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / durati= on_time", "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs", "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." @@ -1081,7 +1081,7 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_U= NHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, @@ -1099,74 +1099,99 @@ }, { "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", - "MetricExpr": "64 * (arb@event\\=3D0x81\\,umask\\=3D0x1@ + arb@eve= nt\\=3D0x84\\,umask\\=3D0x1@) / 1000000 / duration_time / 1000", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_RE= QUESTS.ALL) / 1e6 / duration_time / 1e3", "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of all requests to external m= emory (in Uncore cycles)", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricExpr": "MEM_Parallel_Requests", "MetricGroup": "Mem;SoC", "MetricName": "MEM_Request_Latency" }, { "BriefDescription": "Average number of parallel requests to extern= al memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=3D0x81\\,um= ask\\=3D0x1@", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.AL= L", "MetricGroup": "Mem;SoC", "MetricName": "MEM_Parallel_Requests" }, + { + "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", + "MetricExpr": "1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TR= K_REQUESTS.DATA_READ) / (Socket_CLKS / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" + }, { "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "arb@event\\=3D0x80\\,umask\\=3D0x2@ / arb@event\\= =3D0x80\\,umask\\=3D0x2\\,cmask\\=3D1@", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUP= ANCY.DATA_READ@thresh\\=3D1@", "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, + { + "BriefDescription": "Socket actual clocks when any core is active = on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "Socket_CLKS" + }, { "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricGroup": "Branches;OS", "MetricName": "IpFarBranch" }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, { "BriefDescription": "C3 residency percent per core", - "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", "MetricGroup": "Power", - "MetricName": "C3_Core_Residency" + "MetricName": "C3_Core_Residency", + "ScaleUnit": "100%" }, { "BriefDescription": "C6 residency percent per core", - "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", "MetricGroup": "Power", - "MetricName": "C6_Core_Residency" + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { "BriefDescription": "C7 residency percent per core", - "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", "MetricGroup": "Power", - "MetricName": "C7_Core_Residency" + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" }, { "BriefDescription": "C2 residency percent per package", - "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency" + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { "BriefDescription": "C3 residency percent per package", - "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency" + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" }, { "BriefDescription": "C6 residency percent per package", - "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency" + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { "BriefDescription": "C7 residency percent per package", - "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency" + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json b/too= ls/perf/pmu-events/arch/x86/skylake/uncore-cache.json index edb1014bee0f..ec9463c94ffe 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json @@ -1,7 +1,6 @@ [ { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", @@ -11,7 +10,6 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", @@ -21,7 +19,6 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", @@ -31,7 +28,6 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", @@ -41,7 +37,6 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", @@ -51,7 +46,6 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", @@ -61,7 +55,6 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", @@ -71,7 +64,6 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", @@ -81,7 +73,6 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", @@ -91,7 +82,6 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state", - "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", @@ -101,41 +91,33 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", - "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", - "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a modified line in some proce= ssor core.", "UMask": "0x48", "Unit": "CBO" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", - "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", - "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which hits a non-modified line in some p= rocessor core.", "UMask": "0x44", "Unit": "CBO" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", - "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction= which misses in some processor core.", "UMask": "0x81", "Unit": "CBO" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", - "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", - "PublicDescription": "A cross-core snoop initiated by this Cbox du= e to processor core memory request which misses in some processor core.", "UMask": "0x41", "Unit": "CBO" } diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/skylake/uncore-other.json index bf5d4acdd6b8..e6d4cd625597 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json @@ -1,12 +1,10 @@ [ { "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, Core aperture, etc.", - "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", - "PublicDescription": "Number of entries allocated. Account for Any= type: e.g. Snoop, Core aperture, etc.", - "UMask": "0x01", + "UMask": "0x1", "Unit": "ARB" }, { @@ -14,8 +12,7 @@ "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", - "PublicDescription": "Number of all Core entries outstanding for t= he memory controller. The outstanding interval starts after LLC miss till r= eturn of first data chunk. Accounts for Coherent and non-coherent traffic."= , - "UMask": "0x01", + "UMask": "0x1", "Unit": "ARB" }, { @@ -24,8 +21,7 @@ "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", "PerPkg": "1", - "PublicDescription": "Cycles with at least one request outstanding= is waiting for data return from memory controller. Account for coherent an= d non-coherent requests initiated by IA Cores, Processor Graphics Unit, or = LLC.", - "UMask": "0x01", + "UMask": "0x1", "Unit": "ARB" }, { @@ -33,43 +29,42 @@ "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", "PerPkg": "1", - "PublicDescription": "Number of Core Data Read entries outstanding= for the memory controller. The outstanding interval starts after LLC miss = till return of first data chunk.", - "UMask": "0x02", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", "Unit": "ARB" }, { "BriefDescription": "Number of Core coherent Data Read requests se= nt to memory controller whose data is returned directly to requesting agent= .", - "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", "PerPkg": "1", - "PublicDescription": "Number of Core coherent Data Read requests s= ent to memory controller whose data is returned directly to requesting agen= t.", - "UMask": "0x02", + "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Number of Core coherent Data Read requests se= nt to memory controller whose data is returned directly to requesting agent= .", - "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", "PerPkg": "1", - "PublicDescription": "Number of Core coherent Data Read requests s= ent to memory controller whose data is returned directly to requesting agen= t.", - "UMask": "0x02", + "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Number of Writes allocated - any write transa= ctions: full/partials writes and evictions.", - "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", "PerPkg": "1", - "PublicDescription": "Number of Writes allocated - any write trans= actions: full/partials writes and evictions.", "UMask": "0x20", "Unit": "ARB" }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", - "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/skylake/virtual-memory.json index dd334b416c57..f59405877ae8 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data loads that caused a page = walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB leve= ls, but the walk need not have completed.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a load. EPT page walk duration are excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -32,8 +26,6 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -42,8 +34,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 1G page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -52,8 +42,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 2M/4M page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -62,8 +50,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 4K page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -72,8 +58,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a load. EPT page walk duration are excluded in Skylake= .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a load. EPT page walk duration are excluded in Skylak= e microarchitecture.", @@ -82,8 +66,6 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data stores that caused a page= walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB lev= els, but the walk need not have completed.", @@ -92,8 +74,6 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit= the STLB (2nd Level TLB).", @@ -102,8 +82,6 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store. EPT page walk duration are excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -113,8 +91,6 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -123,8 +99,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 1G page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -133,8 +107,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M/4M page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -143,8 +115,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -153,8 +123,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a store. EPT page walk duration are excluded in Skylak= e.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a store. EPT page walk duration are excluded in Skyla= ke microarchitecture.", @@ -163,8 +131,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a EPT (Extended Page Table) walk for any request type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts cycles for each PMH (Page Miss Handle= r) that is busy with an EPT (Extended Page Table) walk for any request type= .", @@ -173,8 +139,6 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of flushes of the big or s= mall ITLB pages. Counting include both TLB Flush (covering all sets) and TL= B Set Clear (set-specific).", @@ -183,8 +147,6 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts page walks of any page size (4K/2M/4M= /1G) caused by a code fetch. This implies it missed in the ITLB and further= levels of TLB, but the walk need not have completed.", @@ -193,8 +155,6 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -202,8 +162,6 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request. EPT page walk duration are e= xcluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -213,8 +171,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -223,8 +179,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (1G)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -233,8 +187,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -243,8 +195,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -253,8 +203,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for an instruction fetch request. EPT page walk duration a= re excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss H= andler) that is busy with a page walk for an instruction fetch request. EPT= page walk duration are excluded in Skylake michroarchitecture.", @@ -263,8 +211,6 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -273,8 +219,6 @@ }, { "BriefDescription": "STLB flush attempts", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", --=20 2.39.0.314.g84b9a713c41-goog