From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ACEDC4332F for ; Thu, 15 Dec 2022 07:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230024AbiLOHCg (ORCPT ); Thu, 15 Dec 2022 02:02:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229983AbiLOHAr (ORCPT ); Thu, 15 Dec 2022 02:00:47 -0500 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31B9F6A757 for ; Wed, 14 Dec 2022 22:58:04 -0800 (PST) Received: by mail-pf1-x44a.google.com with SMTP id 67-20020a621946000000b00575f8210320so5594468pfz.10 for ; Wed, 14 Dec 2022 22:58:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=jbGYrW4urGiH7KDtLStD+l1nxgFIKpyNleZq94LosTg=; b=ngGAD+0o1sJmlFst/GAlR3ubGN13Ze0pQ4/iEcLD0ZvTwWSs0gVJI+XxdMaYOLQTDr GlRcVDtjcuE2BDDb+uM/MotHxRvv6KGowHEjUJfKEtSYPPT8SAKFMd8n9jq9t2uJTLz7 kmz6Hi6JxZxtPmCz7lcobOb6Act4Y1i08udHFSIiDRLUfhaSV0lG3H3WAJ2miC3rO+gT /mnrSy7rW2JodI/IXjBmCgcOGrxnY3srfyww18I82Emh2BOp4lELwEakWCWJNeZt0xgN XrkGwtK9RxObaeKWoSAJEWvVNyGdnNVq2CqO5BUVBktS90tBdZ7pwqXvSEYJ5n6x0UMk OQXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jbGYrW4urGiH7KDtLStD+l1nxgFIKpyNleZq94LosTg=; b=orFsOwfLg9Ys4IeFQ7iXFHHVc+KpLPofUhJzopWTL4oFwr5C2nVoUUu1iBqYtqwpn1 5/vaBjl5YRZ5d23f4OuLtOyKU/f8FcnB0lPx5m8klVbOlxCSCvyjTuk344NQ39Y5C/CJ U0Im0k7HCgjLSDwFHPmKhYIOaAw4PU6TAmIwzYhwvzwrkRaX15E5RHZbrlalHvJY/NFR mrQU+0gCy9jCE0OLPl+t6yyCN+a2bOQhCM8YpbYruO6aF99SPCZcs9xZ069bzDuSSQ0S zVhdu8QTcVxStJeg1AREqz1MMB0jsjR7A7ugCSuZVzetQBwIBpVrzFkRm6SHUQiTkSfZ h/rQ== X-Gm-Message-State: ANoB5pkKZ/J18aH98hrpELevJt+QMiJbqy0mwjLZ0KUSQhpq7ptVHVTb CR7FexbYA6TnGJrdGjCuRTzJGpYA9LAR X-Google-Smtp-Source: AA0mqf62jopiLpE+WmSZYlo1yoh8/iVcyPUOXwEMCTACbru/VMYr7ewfwzeIbr6TrLfHqNISWHWelqCHHurF X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:c7dc:d96f:4f9:f59d]) (user=irogers job=sendgmr) by 2002:a17:90a:ad09:b0:219:5079:7aa3 with SMTP id r9-20020a17090aad0900b0021950797aa3mr474017pjq.183.1671087483319; Wed, 14 Dec 2022 22:58:03 -0800 (PST) Date: Wed, 14 Dec 2022 22:55:05 -0800 In-Reply-To: <20221215065510.1621979-1-irogers@google.com> Message-Id: <20221215065510.1621979-19-irogers@google.com> Mime-Version: 1.0 References: <20221215065510.1621979-1-irogers@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Subject: [PATCH v1 27/32] perf vendor events intel: Refresh skylakex metrics and events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Kan Liang , Xing Zhengjun , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Garry , Stephane Eranian , Perry Taylor , Caleb Biggers , Ian Rogers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the skylakex metrics and events using the new tooling from: https://github.com/intel/perfmon The metrics are unchanged but the formulas differ due to parentheses, use of exponents and removal of redundant operations like "* 1". The order of metrics varies as TMA metrics are first converted and then removed if perfmon versions are found. The events are updated with fixes to uncore events and improved descriptions. uncore-other.json changes due to events now being sorted. The formatting changes increase consistency across the json files. Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/skylakex/cache.json | 368 - .../arch/x86/skylakex/floating-point.json | 18 - .../arch/x86/skylakex/frontend.json | 109 - .../pmu-events/arch/x86/skylakex/memory.json | 310 - .../pmu-events/arch/x86/skylakex/other.json | 30 - .../arch/x86/skylakex/pipeline.json | 194 - .../arch/x86/skylakex/skx-metrics.json | 2134 +- .../arch/x86/skylakex/uncore-memory.json | 2303 +- .../arch/x86/skylakex/uncore-other.json | 29356 +++++++++------- .../arch/x86/skylakex/uncore-power.json | 45 +- .../arch/x86/skylakex/virtual-memory.json | 56 - 11 files changed, 18426 insertions(+), 16497 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/per= f/pmu-events/arch/x86/skylakex/cache.json index e21010c0df41..92da692795e7 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "L1D data line replacements", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Number of times a request needed a FB (Fill = Buffer) entry but there was no entry available for it. A request includes c= acheable/uncacheable demands that are load, store or SW prefetch instructio= ns.", @@ -21,8 +17,6 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts duration of L1D miss outstanding, tha= t is each cycle number of Fill Buffers (FB) outstanding required by Demand = Reads. FB either is held by demand loads, or it is held by non-demand loads= and gets hit at least once by demand. The valid outstanding interval is de= fined until the FB deallocation by one of the following ways: from FB alloc= ation, if FB is allocated by demand from the demand Hit FB, if it is alloca= ted by hardware or software prefetch.Note: In the L1D, a Demand Read contai= ns cacheable or noncacheable demand loads, including ones causing cache-lin= e splits and reads due to page walks resulted from any request type.", @@ -31,8 +25,6 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -43,8 +35,6 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -53,8 +43,6 @@ }, { "BriefDescription": "L2 cache lines filling L2", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -63,8 +51,6 @@ }, { "BriefDescription": "Counts the number of lines that are evicted b= y L2 cache when triggered by an L2 cache fill. Those lines can be either in= modified state or clean state. Modified lines may either be written back t= o L3 or directly written to memory and not allocated in L3. Clean lines ma= y either be allocated in L3 or dropped", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines can be either i= n modified state or clean state. Modified lines may either be written back = to L3 or directly written to memory and not allocated in L3. Clean lines m= ay either be allocated in L3 or dropped.", @@ -73,8 +59,6 @@ }, { "BriefDescription": "Counts the number of lines that are silently = dropped by L2 cache when triggered by an L2 cache fill. These lines are typ= ically in Shared state. A non-threaded event.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "SampleAfterValue": "200003", @@ -82,8 +66,6 @@ }, { "BriefDescription": "Counts the number of lines that have been har= dware prefetched but not used and now evicted by L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_HWPF", "SampleAfterValue": "200003", @@ -91,8 +73,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L2_LINES_OUT.USELESS_HWPF", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_PREF", @@ -101,8 +81,6 @@ }, { "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -111,8 +89,6 @@ }, { "BriefDescription": "Demand Data Read requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -121,8 +97,6 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Demand requests that miss L2 cache.", @@ -131,8 +105,6 @@ }, { "BriefDescription": "Demand requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Demand requests to L2 cache.", @@ -141,8 +113,6 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts the total number of requests from the= L2 hardware prefetchers.", @@ -151,8 +121,6 @@ }, { "BriefDescription": "RFO requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -161,8 +129,6 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -171,8 +137,6 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -181,8 +145,6 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", @@ -191,8 +153,6 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -201,8 +161,6 @@ }, { "BriefDescription": "All requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "All requests that miss L2 cache.", @@ -211,8 +169,6 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that hit L2 cache.", @@ -221,8 +177,6 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that miss L2 cache.", @@ -231,8 +185,6 @@ }, { "BriefDescription": "All L2 requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "All L2 requests.", @@ -241,8 +193,6 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -251,8 +201,6 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -261,8 +209,6 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -271,8 +217,6 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", @@ -282,8 +226,6 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", @@ -293,8 +235,6 @@ }, { "BriefDescription": "All retired load instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -304,24 +244,18 @@ }, { "BriefDescription": "All retired store instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", - "L1_Hit_Indication": "1", "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x82" }, { "BriefDescription": "All retired memory instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ANY", - "L1_Hit_Indication": "1", "PEBS": "1", "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", "SampleAfterValue": "2000003", @@ -329,8 +263,6 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -340,8 +272,6 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -352,12 +282,9 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", - "L1_Hit_Indication": "1", "PEBS": "1", "PublicDescription": "Counts retired store instructions that split= across a cacheline boundary.", "SampleAfterValue": "100003", @@ -365,8 +292,6 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -377,12 +302,9 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "L1_Hit_Indication": "1", "PEBS": "1", "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", @@ -390,8 +312,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 and cross-core snoop hits in on-pkg core cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -402,8 +322,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were HitM responses from shared L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -414,8 +332,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -425,8 +341,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were hits in L3 without snoops required", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -437,8 +351,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -449,8 +361,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from remote dram", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", @@ -460,8 +370,6 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", @@ -472,8 +380,6 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was remote HITM", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", @@ -484,8 +390,6 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -495,8 +399,6 @@ }, { "BriefDescription": "Retired load instructions which data sources = were load missed L1 but hit FB due to preceding miss to the same cache line= with data not ready", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -507,8 +409,6 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -519,8 +419,6 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -531,8 +429,6 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -543,8 +439,6 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -555,8 +449,6 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -567,8 +459,6 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -579,8 +469,6 @@ }, { "BriefDescription": "Demand and prefetch data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -589,8 +477,6 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", @@ -599,8 +485,6 @@ }, { "BriefDescription": "Cacheable and noncachaeble code read requests= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", @@ -609,8 +493,6 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -619,8 +501,6 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -629,8 +509,6 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "Counts the number of cases when the offcore = requests buffer cannot take more entries for the core. This can happen when= the superqueue does not contain eligible entries, or when L1D writeback pe= nding FIFO requests is full.Note: Writeback pending FIFO has six entries.", @@ -639,8 +517,6 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", @@ -649,8 +525,6 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -660,8 +534,6 @@ }, { "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -671,8 +543,6 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -682,8 +552,6 @@ }, { "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO"= , @@ -693,8 +561,6 @@ }, { "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", @@ -703,8 +569,6 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding Dem= and Data Read transactions in the super queue (SQ) every cycle. A transacti= on is considered to be in the Offcore outstanding state between L2 miss and= transaction completion sent to requestor. See the corresponding Umask unde= r OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the = promotion point.", @@ -713,8 +577,6 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -723,8 +585,6 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of offcore outstanding RFO= (store) transactions in the super queue (SQ) every cycle. A transaction is= considered to be in the Offcore outstanding state between L2 miss and tran= saction completion sent to requestor (SQ de-allocation). See corresponding = Umask under OFFCORE_REQUESTS.", @@ -733,8 +593,6 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -743,872 +601,654 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = have any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3 and the snoop to one of the sibling cores hits the line in M = state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3 and the snoop to one of the sibling cores hits the line in M = state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3 and sibling core snoops are not needed as either the core-val= id bit is not set or the shared line is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT= _WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_F= WD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that have any = response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3 and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3 and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3 and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_= HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that have any response t= ype.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3 and s= ibling core snoops are not needed as either the core-valid bit is not set o= r the shared line is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_= WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that have a= ny response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3 and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3 and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3 and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WIT= H_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that have any re= sponse type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that hit in the = L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that hit in the = L3 and sibling core snoops are not needed as either the core-valid bit is n= ot set or the shared line is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_= HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that have any respon= se type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that hit in the L3."= , - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that hit in the L3 a= nd sibling core snoops are not needed as either the core-valid bit is not s= et or the shared line is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_= HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that hav= e any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3 and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3 and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3 and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_= WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that have any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3 and the snoop to one o= f the sibling cores hits the line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3 and the snoop to one o= f the sibling cores hits the line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3 and sibling core snoop= s are not needed as either the core-valid bit is not set or the shared line= is present in multiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_H= IT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that have any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3 and the snoop to one of the sibling cores hits the= line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3 and the snoop to one of the sibling cores hits the= line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3 and sibling core snoops are not needed as either t= he core-valid bit is not set or the shared line is present in multiple core= s.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_H= IT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that have any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3 and the snoop to one of the sibling cores hits the l= ine in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3 and the snoop to one of the sibling cores hits the l= ine in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3 and sibling core snoops are not needed as either the= core-valid bit is not set or the shared line is present in multiple cores.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_W= ITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that have any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3 and the snoop to one of the sibling core= s hits the line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3 and the snoop to one of the sibling core= s hits the line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3 and sibling core snoops are not needed a= s either the core-valid bit is not set or the shared line is present in mul= tiple cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_H= IT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that have any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3F803C0100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3 and the snoop to one of the sibling cores hits= the line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3 and the snoop to one of the sibling cores hits= the line in M state and the line is forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3 and sibling core snoops are not needed as eith= er the core-valid bit is not set or the shared line is present in multiple = cores.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_W= ITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Number of cache line split locks sent to unco= re.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "Counts the number of cache line split locks = sent to the uncore.", @@ -1617,8 +1257,6 @@ }, { "BriefDescription": "Number of PREFETCHNTA instructions executed."= , - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "SampleAfterValue": "2000003", @@ -1626,8 +1264,6 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "SampleAfterValue": "2000003", @@ -1635,8 +1271,6 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "SampleAfterValue": "2000003", @@ -1644,8 +1278,6 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/skylakex/floating-point.json index 09810e3d688c..64dd36387209 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", @@ -31,8 +25,6 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -41,8 +33,6 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -51,8 +41,6 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -61,8 +49,6 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", @@ -71,8 +57,6 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", @@ -81,8 +65,6 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/= perf/pmu-events/arch/x86/skylakex/frontend.json index 8633ee406813..13ccf50db43d 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "PublicDescription": "This event counts the number of the Decode S= tream Buffer (DSB)-to-MITE switches including all misses because of missing= Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking= MITE requires two or three cycles delay.", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE sw= itch true penalty cycles. These cycles do not include uops routed through b= ecause of the switch itself, for example, when Instruction Decode Queue (ID= Q) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full= . SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) re= ceives Decode Stream Buffer (DSB) Sync-indication until receiving the first= MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops= being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Strea= m Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer = (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit follo= wed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which= no uops are delivered to the IDQ. Most often, such switches from the Decod= e Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", @@ -31,8 +25,6 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -40,13 +32,10 @@ "PEBS": "1", "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -54,13 +43,10 @@ "PEBS": "1", "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -68,39 +54,30 @@ "PEBS": "1", "PublicDescription": "Counts retired Instructions that experienced= iTLB (Instruction TLB) true miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", "MSRValue": "0x12", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", "MSRValue": "0x13", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -108,26 +85,20 @@ "PEBS": "2", "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", "MSRValue": "0x408006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -135,39 +106,30 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 16 cycles. During th= is period the front-end delivered no uops.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 2 cycles w= hich was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", "MSRValue": "0x400206", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", "MSRValue": "0x410006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -175,39 +137,30 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 2 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", "MSRIndex": "0x3F7", "MSRValue": "0x200206", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 3 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", "MSRIndex": "0x3F7", "MSRValue": "0x300206", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -215,52 +168,40 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 32 cycles. During th= is period the front-end delivered no uops.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", "MSRValue": "0x400406", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", "MSRValue": "0x420006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", "MSRValue": "0x404006", "PEBS": "1", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -268,13 +209,10 @@ "PEBS": "1", "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 8 cycles. During thi= s period the front-end delivered no uops.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -282,13 +220,10 @@ "PEBS": "1", "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Cycles where a code line fetch is stalled du= e to an L1 instruction cache miss. The legacy decode pipeline works at a 16= Byte granularity.", @@ -297,8 +232,6 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "SampleAfterValue": "200003", @@ -306,8 +239,6 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "SampleAfterValue": "200003", @@ -315,8 +246,6 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "SampleAfterValue": "200003", @@ -324,8 +253,6 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -335,8 +262,6 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -346,8 +271,6 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -357,8 +280,6 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -368,8 +289,6 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -379,8 +298,6 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Countin= g includes uops that may 'bypass' the IDQ.", @@ -389,8 +306,6 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -400,8 +315,6 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. Counting includes uops that m= ay 'bypass' the IDQ. This also means that uops are not being delivered from= the Decode Stream Buffer (DSB).", @@ -410,8 +323,6 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -421,8 +332,6 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -432,8 +341,6 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE = and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenc= er (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -442,8 +349,6 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -454,8 +359,6 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -464,8 +367,6 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to R= esource Allocation Table (RAT) per thread adding 4 x when Resource Allocat= ion Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers = x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). C= ounting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) p= ipe serves the other thread. b. Resource Allocation Table (RAT) is stalled = for the thread (including uop drops and clear BE conditions). c. Instructi= on Decode Queue (IDQ) delivers four uops.", @@ -474,8 +375,6 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -485,8 +384,6 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -496,8 +393,6 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -507,8 +402,6 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -518,8 +411,6 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/memory.json b/tools/pe= rf/pmu-events/arch/x86/skylakex/memory.json index a570fe3e7a2d..2b797dbc75fe 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/memory.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -32,8 +26,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_EVENTS", "SampleAfterValue": "2000003", @@ -41,8 +33,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEM", "SampleAfterValue": "2000003", @@ -50,8 +40,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an HLE execution aborted due= to incompatible memory type.", @@ -60,8 +48,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to hardware timer expiration.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -69,8 +55,6 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "SampleAfterValue": "2000003", @@ -78,8 +62,6 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -88,8 +70,6 @@ }, { "BriefDescription": "Number of times an HLE execution started.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region. Do= es not count nested transactions.", @@ -98,8 +78,6 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL089", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", @@ -109,8 +87,6 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -119,13 +95,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 128 cycles. Reported= latency may be longer than just the memory latency.", "SampleAfterValue": "1009", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -134,13 +107,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 16 cycles. Reported = latency may be longer than just the memory latency.", "SampleAfterValue": "20011", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -149,13 +119,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 256 cycles. Reported= latency may be longer than just the memory latency.", "SampleAfterValue": "503", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -164,13 +131,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 32 cycles. Reported = latency may be longer than just the memory latency.", "SampleAfterValue": "100007", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -179,13 +143,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 4 cycles. Reported l= atency may be longer than just the memory latency.", "SampleAfterValue": "100003", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -194,13 +155,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 512 cycles. Reported= latency may be longer than just the memory latency.", "SampleAfterValue": "101", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -209,13 +167,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 64 cycles. Reported = latency may be longer than just the memory latency.", "SampleAfterValue": "2003", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -224,13 +179,10 @@ "PEBS": "2", "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 8 cycles. Reported l= atency may be longer than just the memory latency.", "SampleAfterValue": "50021", - "TakenAlone": "1", "UMask": "0x1" }, { "BriefDescription": "Demand Data Read requests who miss L3 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", @@ -239,8 +191,6 @@ }, { "BriefDescription": "Cycles with at least 1 Demand Data Read reque= sts who miss L3 cache in the superQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -249,8 +199,6 @@ }, { "BriefDescription": "Counts number of Offcore outstanding Demand D= ata Read requests that miss L3 cache in the superQ every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD"= , "SampleAfterValue": "2000003", @@ -258,8 +206,6 @@ }, { "BriefDescription": "Cycles with at least 6 Demand Data Read reque= sts that miss L3 cache in the superQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", @@ -268,872 +214,654 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the modified data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and clean or shared data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORW= ARD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNO= OP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800491", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that miss in t= he L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the modified data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and clean or shared data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800490", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that miss in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= modified data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and cle= an or shared data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800120", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss i= n the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the modified data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and clean or shared data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_M= ISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800122", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that miss in the= L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the modified data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that miss the L3= and clean or shared data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that miss in the L3.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the modified data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that miss the L3 and= clean or shared data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the modified data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and clean or shared data is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the modified data is= transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and clean or shared data= is transferred from remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the data is returned= from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the data is returned= from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the data is returned= from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the modified data is transferred from remote cac= he.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and clean or shared data is transferred from remote = cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the data is returned from local or remote dram."= , - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the modified data is transferred from remote cache= .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and clean or shared data is transferred from remote ca= che.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the data is returned from local or remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the modified data is transferred from = remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and clean or shared data is transferred fr= om remote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the data is returned from local or rem= ote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the data is returned from local dram."= , - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the data is returned from remote dram.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800080", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss in the L3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3FBC000100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the modified data is transferred from remote= cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103FC00100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and clean or shared data is transferred from rem= ote cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x83FC00100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the data is returned from local or remote dr= am.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63FC00100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the data is returned from local dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x604000100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the data is returned from remote dram.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x63B800100", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -1143,8 +871,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", @@ -1153,8 +879,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", @@ -1163,8 +887,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an RTM execution aborted due= to incompatible memory type.", @@ -1173,8 +895,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to uncommon conditions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -1182,8 +902,6 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Number of times an RTM execution aborted due= to HLE-unfriendly instructions.", @@ -1192,8 +910,6 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -1202,8 +918,6 @@ }, { "BriefDescription": "Number of times an RTM execution started.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region. Do= es not count nested transactions.", @@ -1212,8 +926,6 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -1221,8 +933,6 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupp= er instruction.", @@ -1231,8 +941,6 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -1241,8 +949,6 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -1251,8 +957,6 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "PublicDescription": "Counts the number of times an HLE XACQUIRE i= nstruction was executed inside an RTM transactional region.", @@ -1261,8 +965,6 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional reads or writes."= , - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY", "SampleAfterValue": "2000003", @@ -1270,8 +972,6 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -1280,8 +980,6 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -1290,8 +988,6 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -1300,8 +996,6 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -1310,8 +1004,6 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -1320,8 +1012,6 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/per= f/pmu-events/arch/x86/skylakex/other.json index 403805e7e581..cda8a7a45f0c 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for baseline license level 0. This includes non-AVX codes, = SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 1. This includes high current AVX 256-bit= instructions as well as low current AVX 512-bit instructions.", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server michroarch= tecture). This includes high current AVX 512-bit instructions.", @@ -31,8 +25,6 @@ }, { "BriefDescription": "Core cycles the core was throttled due to a p= ending power level request.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x28", "EventName": "CORE_POWER.THROTTLE", "PublicDescription": "Core cycles the out-of-order engine was thro= ttled due to a pending power level request.", @@ -41,8 +33,6 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "SampleAfterValue": "2000003", @@ -50,8 +40,6 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "SampleAfterValue": "2000003", @@ -59,8 +47,6 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "SampleAfterValue": "2000003", @@ -68,8 +54,6 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", "SampleAfterValue": "2000003", @@ -77,8 +61,6 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "SampleAfterValue": "2000003", @@ -86,8 +68,6 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "SampleAfterValue": "2000003", @@ -95,8 +75,6 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "SampleAfterValue": "2000003", @@ -104,8 +82,6 @@ }, { "BriefDescription": "Number of hardware interrupts received by the= processor.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PublicDescription": "Counts the number of hardware interruptions = received by the processor.", @@ -114,8 +90,6 @@ }, { "BriefDescription": "Counts number of cache lines that are dropped= and not written back to L3 as they are deemed to be less likely to be reus= ed shortly", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xFE", "EventName": "IDI_MISC.WB_DOWNGRADE", "PublicDescription": "Counts number of cache lines that are droppe= d and not written back to L3 as they are deemed to be less likely to be reu= sed shortly.", @@ -124,8 +98,6 @@ }, { "BriefDescription": "Counts number of cache lines that are allocat= ed and written back to L3 with the intention that they are more likely to b= e reused shortly", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xFE", "EventName": "IDI_MISC.WB_UPGRADE", "PublicDescription": "Counts number of cache lines that are alloca= ted and written back to L3 with the intention that they are more likely to = be reused shortly.", @@ -134,8 +106,6 @@ }, { "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x09", "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/skylakex/pipeline.json index f085b9145952..64e1fe351333 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations. Accounts for integer and floating-point oper= ations.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -11,8 +9,6 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", @@ -21,8 +17,6 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -33,8 +27,6 @@ }, { "BriefDescription": "Conditional branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", @@ -45,8 +37,6 @@ }, { "BriefDescription": "Not taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", @@ -56,8 +46,6 @@ }, { "BriefDescription": "Far branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -68,8 +56,6 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", @@ -80,8 +66,6 @@ }, { "BriefDescription": "Return instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", @@ -92,8 +76,6 @@ }, { "BriefDescription": "Taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", @@ -104,8 +86,6 @@ }, { "BriefDescription": "Not taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", @@ -115,8 +95,6 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", @@ -124,8 +102,6 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -135,8 +111,6 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -146,8 +120,6 @@ }, { "BriefDescription": "Mispredicted direct and indirect near call in= structions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -157,8 +129,6 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -167,8 +137,6 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -178,8 +146,6 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -187,8 +153,6 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -197,8 +161,6 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -206,8 +168,6 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -215,8 +175,6 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", - "Counter": "Fixed counter 2", - "CounterHTOff": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the four (eight when Hyperthre= ading is disabled) programmable counters available for other events. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -224,8 +182,6 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -234,8 +190,6 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -243,8 +197,6 @@ }, { "BriefDescription": "Counts when there is a transition from ring 1= , 2 or 3 to ring 0.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x3C", @@ -254,8 +206,6 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the four (eight when Hyperthreading is disabled) programmable counters a= vailable for other events.", "SampleAfterValue": "2000003", @@ -264,16 +214,12 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -282,16 +228,12 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -300,8 +242,6 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -310,8 +250,6 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -320,8 +258,6 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -330,8 +266,6 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -340,8 +274,6 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", "CounterMask": "20", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -350,8 +282,6 @@ }, { "BriefDescription": "Total execution stalls.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -360,8 +290,6 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -370,8 +298,6 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -380,8 +306,6 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -390,8 +314,6 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -400,8 +322,6 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= outstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "SampleAfterValue": "2000003", @@ -409,8 +329,6 @@ }, { "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", @@ -419,8 +337,6 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", @@ -429,8 +345,6 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -439,8 +353,6 @@ }, { "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "CounterHTOff": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "Counts the number of instructions retired fr= om execution. For instructions that consist of multiple micro-ops, Counts t= he retirement of the last micro-op of the instruction. Counting continues d= uring hardware interrupts, traps, and inside interrupt handlers. Notes: INS= T_RETIRED.ANY is counted by a designated fixed counter, leaving the four (e= ight when Hyperthreading is disabled) programmable counters available for o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter and it= is an architectural performance event. Counting: Faulting executions of GE= TSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "SampleAfterValue": "2000003", @@ -448,8 +360,6 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -458,8 +368,6 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.NOP", @@ -469,8 +377,6 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", - "Counter": "1", - "CounterHTOff": "1", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -481,8 +387,6 @@ }, { "BriefDescription": "Number of cycles using always true condition = applied to PEBS instructions retired event.", - "Counter": "0,2,3", - "CounterHTOff": "0,2,3", "CounterMask": "10", "Errata": "SKL091, SKL044", "EventCode": "0xC0", @@ -495,8 +399,6 @@ }, { "BriefDescription": "Cycles the issue-stage is waiting for front-e= nd to fetch from resteered path following branch misprediction or machine c= lear events.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "SampleAfterValue": "2000003", @@ -504,8 +406,6 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Core cycles the Resource allocator was stall= ed due to recovery from an earlier branch misprediction or machine clear ev= ent.", @@ -515,8 +415,6 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", @@ -524,8 +422,6 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -534,8 +430,6 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -544,8 +438,6 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts false dependencies in MOB when the pa= rtial comparison upon loose net check and dependency was resolved by the En= hanced Loose net mechanism. This may not result in high performance penalti= es. Loose net checks can fail when loads and stores are 4k aliased.", @@ -554,8 +446,6 @@ }, { "BriefDescription": "Demand load dispatches that hit L1D fill buff= er (FB) allocated for software prefetch.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -564,8 +454,6 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -575,8 +463,6 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -586,8 +472,6 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA8", "EventName": "LSD.UOPS", "PublicDescription": "Number of uops delivered to the back-end by = the LSD(Loop Stream Detector).", @@ -596,8 +480,6 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -607,8 +489,6 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -617,8 +497,6 @@ }, { "BriefDescription": "Number of times a microcode assist is invoked= by HW other than FP-assist. Examples include AD (page Access Dirty) and AV= X* related assists.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY", "SampleAfterValue": "100003", @@ -626,8 +504,6 @@ }, { "BriefDescription": "Cycles where the pipeline is stalled due to s= erializing operations.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", "PublicDescription": "This event counts cycles during which the mi= crocode scoreboard stalls happen.", @@ -636,8 +512,6 @@ }, { "BriefDescription": "Resource-related stall cycles", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Counts resource-related stall cycles.", @@ -646,8 +520,6 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -656,8 +528,6 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -666,8 +536,6 @@ }, { "BriefDescription": "Number of retired PAUSE instructions (that do= not end up with a VMExit to the VMM; TSX aborted Instructions may be count= ed). This event is not supported on first SKL and KBL products.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.PAUSE_INST", "SampleAfterValue": "2000003", @@ -675,8 +543,6 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for the thread.; Note: In ST-mode, not active thread s= hould drive 0. This is usually caused by severely costly branch mispredicti= ons, or allocator/FE issues.", @@ -685,8 +551,6 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -698,8 +562,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -708,8 +570,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -718,8 +578,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 2.", @@ -728,8 +586,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 3.", @@ -738,8 +594,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 4.", @@ -748,8 +602,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -758,8 +610,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -768,8 +618,6 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 7.", @@ -778,8 +626,6 @@ }, { "BriefDescription": "Number of uops executed on the core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -788,8 +634,6 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -798,8 +642,6 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -808,8 +650,6 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -818,8 +658,6 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -828,8 +666,6 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", @@ -839,8 +675,6 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -850,8 +684,6 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -861,8 +693,6 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -872,8 +702,6 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -883,8 +711,6 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -895,8 +721,6 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -905,8 +729,6 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -915,8 +737,6 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -925,8 +745,6 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -934,8 +752,6 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -946,8 +762,6 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", @@ -956,8 +770,6 @@ }, { "BriefDescription": "Number of macro-fused uops retired. (non prec= ise)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PublicDescription": "Counts the number of macro-fused uops retire= d. (non precise)", @@ -966,8 +778,6 @@ }, { "BriefDescription": "Retirement slots used.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PublicDescription": "Counts the retirement slots used.", @@ -976,8 +786,6 @@ }, { "BriefDescription": "Cycles without actually retired uops.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -988,8 +796,6 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/too= ls/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index bc8e42554096..1f8d60cce3ce 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -1,1513 +1,1497 @@ [ { - "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound. Sample with: FRONTEN= D_RETIRED.LATENCY_GE_4_PS", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "Mispredictions" }, { - "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE= / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound= _group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound /= (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_b= ound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_= hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_boun= d + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k= _aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_load= s + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "Memory_Bandwidth" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", - "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDAT= A_STALL\\,cmask\\=3D1\\,edge@) / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latenc= y_group", - "MetricName": "tma_icache_misses", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore", + "MetricName": "Memory_Latency" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_lat= ency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_= dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fw= d_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound += tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_= false_sharing + tma_split_stores + tma_store_latency)))", + "MetricGroup": "Mem;MemoryTLB;Offcore", + "MetricName": "Memory_Data_TLBs" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_= branches", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fro= ntend delay in fetching operations from corrected path; following all sorts= of miss-predicted branches. For example; branchy code with lots of miss-pr= edictions might get categorized under Branch Resteers. Note the value of th= is node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRA= NCHES", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_R= ETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITION= AL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)"= , + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", - "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.AL= L_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS"= , - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteer= s_group", - "MetricName": "tma_mispredicts_resteers", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIR= ED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES /= CLKS", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteer= s_group", - "MetricName": "tma_clears_resteers", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sa= mple with: INT_MISC.CLEAR_RESTEER_CYCLES", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "Instruction_Fetch_BW" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", - "MetricExpr": "9 * BACLEARS.ANY / CLKS", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_gro= up", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (First fetch or hitt= ing BPU capacity limit). Sample with: BACLEARS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", + "MetricExpr": "INST_RETIRED.ANY / CLKS", + "MetricGroup": "Ret;Summary", + "MetricName": "IPC" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group= ", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "UPI" }, { - "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { - "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_grou= p", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles= when the CPU was stalled due to switches of uop delivery to the Microcode = Sequencer (MS). Commonly used instructions are optimized for delivery by th= e DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Cert= ain operations cannot be handled natively by the execution pipeline; and mu= st be performed by microcode (small programs injected into the execution st= ream). Switching to the MS too often can negatively impact performance. The= MS is designated to deliver long uop flows required by CISC instructions l= ike CPUID; or uncommon conditions like Floating Point Assists when dealing = with Denormals. Sample with: IDQ.MS_SWITCHES", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", + "MetricExpr": "1 / IPC", + "MetricGroup": "Mem;Pipeline", + "MetricName": "CPI" }, { - "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_fronte= nd_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "CLKS" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES= _4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_grou= p", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycl= es in which CPU was likely limited due to the MITE pipeline (the legacy dec= ode pipeline). This pipeline is used for code that was not pre-cached in th= e DSB or LSD. For example; inefficiencies due to asymmetric decoders; use o= f long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sa= mple with: FRONTEND_RETIRED.ANY_DSB_MISS", - "ScaleUnit": "100%" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CORE_CLKS", + "MetricGroup": "tma_L1_group", + "MetricName": "SLOTS" }, { - "BriefDescription": "This metric represents fraction of cycles whe= re decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=3D1@ - cpu@INS= T_DECODED.DECODERS\\,cmask\\=3D2@) / CORE_CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group", - "MetricName": "tma_decoder0_alone", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." }, { - "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4= _UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycl= es in which CPU was likely limited due to DSB (decoded uop cache) fetch pip= eline. For example; inefficient utilization of the DSB cache structure or = bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", + "MetricGroup": "Ret;SMT;tma_L1_group", + "MetricName": "CoreIPC" }, { - "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * = ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLE= S)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INS= T_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SING= LE) / CORE_CLKS", + "MetricGroup": "Flops;Ret", + "MetricName": "FLOPc" }, { - "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", - "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.AL= L_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_b= ad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", - "ScaleUnit": "100%" + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_AR= ITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOU= BLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B= _PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLK= S)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." }, { - "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_b= ad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "ILP" }, { - "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((I= NT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES))= / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma= _core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 els= e 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "Core_Bound_Likely" }, { - "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUN= D_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + = tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) = * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_g= roup", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTE= D.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CP= U_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", + "MetricGroup": "SMT", + "MetricName": "CORE_CLKS" }, { - "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY= .STALLS_L1D_MISS) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_mem= ory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" }, { - "BriefDescription": "This metric roughly estimates the fraction of= cycles where the (first level) DTLB was missed by load accesses, that late= r on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" }, { - "BriefDescription": "This metric estimates the fraction of cycles = where the Second-level TLB (STLB) was missed by load accesses, performing a= hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" }, { - "BriefDescription": "This metric roughly estimates fraction of cyc= les when the memory subsystem had loads blocked since they could not forwar= d data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cy= cles when the memory subsystem had loads blocked since they could not forwa= rd data from earlier (in program order) overlapping stores. To streamline m= emory operations in the pipeline; a load can avoid waiting for memory if a = prior in-flight store is writing the data that the load wants to read (stor= e forwarding process). However; in some cases the load may be blocked for a= significant time pending the store forward. For example; when the prior st= ore is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU spent handling cache misses due to lock operations", - "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS= .ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (= 11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" }, { - "BriefDescription": "This metric estimates fraction of cycles hand= ling memory load split accesses - load that cross 64-byte cache line bounda= ry", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles han= dling memory load split accesses - load that cross 64-byte cache line bound= ary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SI= NGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_I= NST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SI= NGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIR= ED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" }, { - "BriefDescription": "This metric estimates how often memory load a= ccesses were aliased by preceding stores (in program order) with a 4K addre= ss offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load = accesses were aliased by preceding stores (in program order) with a 4K addr= ess offset. False match is possible; which incur a few cycles load re-issue= . However; the short re-issue duration is often hidden by the out-of-order = core and HW optimizations; hence a user may safely ignore a high value of t= his metric unless it manages to propagate up into parent nodes of the hiera= rchy (e.g. to L1_Bound).", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SI= NGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PA= CKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETI= RED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARIT= H_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGL= E))", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." }, { - "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\= \,cmask\\=3D1@ / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory).", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." }, { - "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", - "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.= FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (ME= M_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_= FULL\\,cmask\\=3D1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.S= TALLS_L2_MISS) / CLKS)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_mem= ory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." }, { - "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STA= LLS_L3_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_mem= ory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was = stalled due to loads accesses to L3 cache or contended with a sibling Core.= Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency an= d increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." }, { - "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", - "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRE= D.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OF= FCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEM= AND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (44 * Average_Frequency) * MEM_L= OAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RE= TIRED.L1_MISS) / 2) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_g= roup", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." }, { - "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", - "MetricExpr": "(44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED= .XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OFFCORE_RESPONSE.DEMA= ND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT= .HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FW= D)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CL= KS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." }, { - "BriefDescription": "This metric represents fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited)", - "MetricExpr": "(17 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT = * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles wi= th demand load accesses that hit the L3 cache under unloaded scenarios (pos= sibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L= 3 hits) will improve the latency; reduce contention with sibling physical c= ores and increase performance. Note the value of this node may overlap wit= h its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "IpSWPF" }, { - "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", - "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on e= lse OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). The Super Queue is used for = requests to access the L2 cache or to go out to the Uncore.", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions Sample w= ith: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;tma_L1_group", + "MetricName": "Instructions" }, { - "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACT= IVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bou= nd)", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_gr= oup", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was = stalled on accesses to external memory (DRAM) by loads. Better caching can = improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED= .L3_MISS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "Retire" + }, + { + "BriefDescription": "", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "Execute" }, { - "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory (DRAM). The underlying heuristic assumes that a simi= lar off-core traffic is generated by all IA cores. This metric does not agg= regate non-data-read requests by this logical processor; requests from othe= r IA Logical Processors/Physical Cores/sockets; or other non-IA devices lik= e GPU; hence the maximum external memory bandwidth limits may or may not be= approached when this metric is flagged (see Uncore counters for that).", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" }, { - "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory (DRAM= )", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory (DRA= M). This metric does not aggregate requests from other Logical Processors/= Physical Cores/sockets (see Uncore counters for that).", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" }, { - "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from local memory", - "MetricExpr": "(59.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIR= ED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) /= 2) / CLKS", - "MetricGroup": "Server;TopdownL5;tma_mem_latency_group", - "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM_PS", - "ScaleUnit": "100%" + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHE= S.COUNT", + "MetricGroup": "DSBmiss", + "MetricName": "DSB_Switch_Cost" }, { - "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote memory", - "MetricExpr": "(127 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRE= D.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) /= 2) / CLKS", - "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from remote memory. This is caus= ed often due to non-optimal NUMA allocations. #link to NUMA article Sample = with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS", - "ScaleUnit": "100%" + "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "DSB_Misses" }, { - "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote cache in other socket= s including synchronizations issues", - "MetricExpr": "((89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETI= RED.REMOTE_HITM + (89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REM= OTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) /= CLKS", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_gro= up", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from remote cache in other socke= ts including synchronizations issues. This is caused often due to non-optim= al NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RE= TIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS", - "ScaleUnit": "100%" + "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" }, { - "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_gr= oup", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stal= led due to RFO store memory accesses; RFO store issue a read-for-ownership= request before the write. Even though store accesses do not typically stal= l out-of-order CPUs; there are few cases where stores can lead to actual st= alls. This metric will be flagged should RFO stores be a bottleneck. Sample= with: MEM_INST_RETIRED.ALL_STORES_PS", - "ScaleUnit": "100%" + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" }, { - "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", - "MetricExpr": "((L2_RQSTS.RFO_HIT * 11 * (1 - (MEM_INST_RETIRED.LO= CK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOA= DS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_R= EQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group"= , - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full)", - "ScaleUnit": "100%" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RE= TIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", - "MetricExpr": "((110 * Average_Frequency) * (OFFCORE_RESPONSE.DEMA= ND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM= ) + (47.5 * Average_Frequency) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_O= THER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_boun= d_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT= _RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" }, { - "BriefDescription": "This metric represents rate of split store ac= cesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store a= ccesses. Consider aligning your data to the 64-byte cache line granularity= . Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_= TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" }, { - "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", - "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_R= ETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" }, { - "BriefDescription": "This metric roughly estimates the fraction of= cycles where the TLB was missed by store accesses, hitting in the second-l= evel TLB (STLB)", - "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.COND= ITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_= INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" }, { - "BriefDescription": "This metric estimates the fraction of cycles = where the STLB was missed by store accesses, performing a hardware page wal= k", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS += MEM_LOAD_RETIRED.FB_HIT)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency" }, { - "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend= _bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", - "ScaleUnit": "100%" + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "MLP" }, { - "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", - "ScaleUnit": "100%" + "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L1MPKI" }, { - "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related)", - "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_P= ORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIV= IDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)= ) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTI= L) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the= CPU performance was potentially limited due to Core computation issues (no= n divider-related). Two distinct categories can be attributed into this me= tric: (1) heavy data-dependency among contiguous instructions would manifes= t in this metric - such cases are often referred to as low Instruction Leve= l Parallelism (ILP). (2) Contention on some hardware execution unit other t= han Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%" + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L1MPKI_Load" }, { - "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else= CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CP= U executed no uops on any execution port (Logical Processor cycles since IC= L, Physical Core cycles otherwise). Long-latency instructions like divides = may contribute to this metric.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "L2MPKI" }, { - "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CLKS", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "L2MPKI_All" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentag= e of injected blend uops out of all uops issued", - "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISS= UED.ANY", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percenta= ge of injected blend uops out of all uops issued. Usually a Mixing_Vectors = over 5% is worth investigating. Read more in Appendix B1 of the Optimizatio= ns Guide for this topic.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.A= NY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L2MPKI_Load" }, { - "BriefDescription": "This metric represents fraction of cycles whe= re the CPU executed total of 1 uop per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CO= RE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS"= , - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles wh= ere the CPU executed total of 1 uop per cycle on all execution ports (Logic= al Processor cycles since ICL, Physical Core cycles otherwise). This can be= due to heavy data-dependency among software instructions; or over oversubs= cribing a particular hardware resource. In some other cases with high 1_Por= t_Utilized and L1_Bound; this metric can point to L1 data-cache latency bot= tleneck that may not necessarily manifest with complete execution starvatio= n (due to the short L1 latency e.g. walking a linked list) - looking at the= assembly can be helpful.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L2HPKI_All" }, { - "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 2 uops per cycle on all execution ports (Logical Process= or cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CO= RE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS"= , - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 2 uops per cycle on all execution ports (Logical Proces= sor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization = -most compilers feature auto-Vectorization options today- reduces pressure = on the execution ports as multiple elements are calculated with same uop.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L2HPKI_Load" }, { - "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else= UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "ScaleUnit": "100%" + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "L3MPKI" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT= .PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 *= CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "FB_HPKI" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd b= ranch) Sample with: UOPS_DISPATCHED_PORT.PORT_0", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_P= ENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLK= S)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHE= D_PORT.PORT_1", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] = ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple = ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Load operations Sample with: UO= PS_DISPATCHED.PORT_2_3", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT= .PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 *= CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [= ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_2", - "ScaleUnit": "100%" + "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", + "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "L2_Evictions_Silent_PKI" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [= ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_3", - "ScaleUnit": "100%" + "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", + "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "L2_Evictions_NonSilent_PKI" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Store operations", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "L1D_Cache_Fill_BW", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW_1T" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DI= SPATCHED_PORT.PORT_4", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_4", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "L2_Cache_Fill_BW", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW_1T" }, { - "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Samp= le with: UOPS_DISPATCHED_PORT.PORT_7", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_7", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "L3_Cache_Fill_BW", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW_1T" }, { - "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRE= D.RETIRE_SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "L3_Cache_Access_BW", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "L3_Cache_Access_BW_1T" }, { - "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UPI metri= c) ratio of 1 or less should be expected for decently optimized software ru= nning on Intel Core/Xeon products. While this often indicates efficient X86= instructions were executed; high value does not necessarily mean better pe= rformance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "CPU_Utilization" }, { - "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic fl= oating-point (FP) operations fraction the CPU has executed (retired). Note = this metric's value may exceed its parent due to use of \"Uops\" CountDomai= n and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", + "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "Average_Frequency" }, { - "BriefDescription": "This metric serves as an approximation of leg= acy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.TH= READ", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of le= gacy x87 usage. It accounts for instructions beyond X87 FP arithmetic opera= tions; hence may be used as a thermometer to avoid X87 high usage and prefe= rably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INS= T_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SING= LE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "GFLOPs", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating= -point (FP) scalar uops fraction the CPU has retired. May overcount due to = FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", + "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "Turbo_Utilization" }, { - "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBL= E + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_P= ACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RET= IRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating= -point (FP) vector uops fraction the CPU has retired aggregated across all = vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0", + "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #= SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS)", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." }, { - "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 128-bit wide vectors. May overcount= due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1", + "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #= SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS)", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions." }, { - "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 256-bit wide vectors. May overcount= due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #= SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS)", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions." }, { - "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 512-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_512b", - "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 512-bit wide vectors. May overcount= due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_= UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", - "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_memory_operations", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", + "MetricName": "Kernel_Utilization" }, { - "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", - "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / U= OPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fused_instructions", - "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JC= C are commonly used examples.", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k"= , + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" }, { - "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", - "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_non_fused_branches", - "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e= 9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "MetricName": "DRAM_BW_Use" }, { - "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETI= RED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_= TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" }, { - "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_fused_instructions + tma_non_fused_branches + tma_no= p_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_other_light_ops", - "ScaleUnit": "100%" + "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCC= UPANCY.IA_MISS_DRD@thresh\\=3D1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" }, { - "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or microcoded sequences", - "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUS= ED - INST_RETIRED.ANY) / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or microcoded sequences. This highly-correlates with the= uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to exter= nal DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-= read prefetches", + "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / i= mc_0@event\\=3D0x0@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "MEM_DRAM_Read_Latency" }, { - "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", - "MetricGroup": "TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring instructions that that are decoder into two or up t= o ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number o= f uops in such instructions.", - "ScaleUnit": "100%" + "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Writes [GB / sec]", + "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_D= ATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UN= C_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "IO_Write_BW" }, { - "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ= .MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the= CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The M= S is used for CISC instructions not supported by the default decoders (like= repeat move strings; or CPUID); or by microcode assists used to address so= me operation modes (like in Floating Point assists). These cases can often = be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Reads [GB / sec]", + "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_= DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 += UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "IO_Read_BW" }, { - "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", - "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", - "ScaleUnit": "100%" + "BriefDescription": "Socket actual clocks when any core is active = on that socket", + "MetricExpr": "cha_0@event\\=3D0x0@", + "MetricGroup": "SoC", + "MetricName": "Socket_CLKS" }, { - "BriefDescription": "This metric estimates fraction of cycles the = CPU retired uops originated from CISC (complex instruction set computer) in= struction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the= CPU retired uops originated from CISC (complex instruction set computer) i= nstruction. A CISC instruction has multiple uops that are required to perfo= rm the instruction's functionality as in the case of read-modify-write as a= n example. Since these instructions require multiple uops they may or may n= ot imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" }, { - "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "Total pipeline cost of (external) Memory Band= width related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_boun= d / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_stor= e_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma= _l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1= _bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (= tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_spli= t_loads + tma_store_fwd_blk)) ", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricName": "cpu_utilization", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound = / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_= bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing = + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tm= a_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC = * #SYSTEM_TSC_FREQ / 1e9 / duration_time", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" }, { - "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_boun= d + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + = tma_false_sharing + tma_split_stores + tma_store_latency))) ", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_R= ETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITION= AL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)"= , - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" + "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" + "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" + "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricName": "l1d_mpi", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions ", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricName": "l2_mpi", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12D= 4043300000000@ / INST_RETIRED.ANY", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12C= C023300000000@ / INST_RETIRED.ANY", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARIT= H_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBL= E + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.2= 56B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARI= TH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKE= D_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) in nano seconds", + "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\= \=3D0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043= 300000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_pack= ages)) * duration_time", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", + "ScaleUnit": "1ns" }, { - "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_IN= ST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_= ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_D= OUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.51= 2B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_C= LKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to local m= emory in nano seconds", + "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\= \=3D0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043= 200000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_pack= ages)) * duration_time", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _local_requests", + "ScaleUnit": "1ns" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_= GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to remote = memory in nano seconds", + "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\= \=3D0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043= 100000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_pack= ages)) * duration_time", + "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _remote_requests", + "ScaleUnit": "1ns" }, { - "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", - "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_= core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else= 0", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricName": "itlb_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by a code fetch to the total number of completed in= structions. This implies it missed in the ITLB (Instruction TLB) and furthe= r levels of TLB.", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", - "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHAL= TED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else = (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricName": "itlb_large_page_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total = number of completed instructions. This implies it missed in the Instruction= Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY"= , + "MetricName": "dtlb_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data loads to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricName": "dtlb_2mb_large_page_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte page sizes) caused by demand data loads to the total number of = completed instructions. This implies it missed in the Data Translation Look= aside Buffer (DTLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricName": "dtlb_store_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data stores to the total number of comple= ted instructions. This implies it missed in the DTLB and further levels of = TLB.", + "ScaleUnit": "1per_instr" }, { - "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3200000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404320000000= 0@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000@)", + "MetricName": "numa_reads_addressed_to_local_dram", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3100000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404320000000= 0@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000@)", + "MetricName": "numa_reads_addressed_to_remote_dram", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * = #num_packages) / 1e9 / duration_time", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCAL= AR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRE= D.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_A= RITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PAC= KED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST= _RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e= 6 / duration_time", + "MetricName": "upi_data_transmit_bw", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_S= INGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_= PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RE= TIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_AR= ITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SIN= GLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). May undercount due to FMA doubl= e counting. Approximated prior to BDW." + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). May und= ercount due to FMA double counting." + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e= 6 / duration_time", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). May undercount = due to FMA double counting." + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_D= ATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UN= C_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time", + "MetricName": "io_bandwidth_disk_or_network_writes", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). May undercount due= to FMA double counting." + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO= _PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART= 2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time", + "MetricName": "io_bandwidth_disk_or_network_reads", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX512", - "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). May undercount due = to FMA double counting." + "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricName": "percent_uops_delivered_from_decoded_icache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", + "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline"= , + "ScaleUnit": "100%" }, { - "BriefDescription": "Total number of retired Instructions Sample w= ith: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY", + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE= _SLOTS\\,cmask\\=3D1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", + "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_= time", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", + "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration= _time", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", + "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration= _time", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", + "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group", + "MetricName": "tma_frontend_bound", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Machine_Width uops every c= ycle to the Backend. Frontend Bound denotes unutilized issue-slots when the= re is no Backend stall; i.e. bubbles where Frontend delivered no uops while= Backend could have accepted them. For example; stalls due to instruction-c= ache misses would be categorized under Frontend Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHE= S.COUNT", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE= / SLOTS", + "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_f= rontend_bound_group", + "MetricName": "tma_fetch_latency", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) miss= es - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", + "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDAT= A_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma= _fetch_latency_group", + "MetricName": "tma_icache_misses", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative DS= B miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses.", + "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;= tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.TH= READ + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group", + "MetricName": "tma_branch_resteers", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fro= ntend delay in fetching operations from corrected path; following all sorts= of miss-predicted branches. For example; branchy code with lots of miss-pr= edictions might get categorized under Branch Resteers. Note the value of th= is node may overlap with its siblings.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_= mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache= _misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_R= ETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage. ", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK= _UNHALTED.THREAD", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricName": "tma_mispredicts_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are non-taken condi= tionals", - "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRA= NCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Machine Clears. ", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRE= D.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / C= PU_CLK_UNHALTED.THREAD", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricName": "tma_clears_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are taken condition= als", - "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_= TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", + "MetricExpr": "9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch= _resteers_group", + "MetricName": "tma_unknown_branches", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (First fetch or hitt= ing BPU capacity limit).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_R= ETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED= .THREAD", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group", + "MetricName": "tma_dsb_switches", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.COND= ITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_= INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" + "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group", + "MetricName": "tma_lcp", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS += MEM_LOAD_RETIRED.FB_HIT)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch= _latency_group", + "MetricName": "tma_ms_switches", + "PublicDescription": "This metric estimates the fraction of cycles= when the CPU was stalled due to switches of uop delivery to the Microcode = Sequencer (MS). Commonly used instructions are optimized for delivery by th= e DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Cert= ain operations cannot be handled natively by the execution pipeline; and mu= st be performed by microcode (small programs injected into the execution st= ream). Switching to the MS too often can negatively impact performance. The= MS is designated to deliver long uop flows required by CISC instructions l= ike CPUID; or uncommon conditions like Floating Point Assists when dealing = with Denormals.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss. Per-Logical Proces= sor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_gro= up;tma_frontend_bound_group", + "MetricName": "tma_fetch_bandwidth", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY"= , - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES= _4_UOPS) / CORE_CLKS / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_b= andwidth_group", + "MetricName": "tma_mite", + "PublicDescription": "This metric represents Core fraction of cycl= es in which CPU was likely limited due to the MITE pipeline (the legacy dec= ode pipeline). This pipeline is used for code that was not pre-cached in th= e DSB or LSD. For example; inefficiencies due to asymmetric decoders; use o= f long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.A= NY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" + "BriefDescription": "This metric represents fraction of cycles whe= re decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=3D0x1@ - cpu@I= NST_DECODED.DECODERS\\,cmask\\=3D0x2@) / CORE_CLKS", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_gr= oup", + "MetricName": "tma_decoder0_alone", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY"= , - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4= _UOPS) / CORE_CLKS / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandw= idth_group", + "MetricName": "tma_dsb", + "PublicDescription": "This metric represents Core fraction of cycl= es in which CPU was likely limited due to DSB (decoded uop cache) fetch pip= eline. For example; inefficient utilization of the DSB cache structure or = bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * = (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)= ) / SLOTS", + "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", + "MetricName": "tma_bad_speculation", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.= ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L= 2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST= _RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L= 2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", + "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (IN= T_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) /= SLOTS", + "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", + "MetricName": "tma_backend_bound", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", - "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.A= NY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND= _ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + U= OPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVIT= Y.BOUND_ON_STORES) * tma_backend_bound", + "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_ba= ckend_bound_group", + "MetricName": "tma_memory_bound", + "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY"= , - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY= .STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", - "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" + "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D0= x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYC= LE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_grou= p", + "MetricName": "tma_dtlb_load", + "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_P= ENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLK= S)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric roughly estimates the fraction of= cycles where the (first level) DTLB was missed by load accesses, that late= r on hit in second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_gro= up", + "MetricName": "tma_load_stlb_hit", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric estimates the fraction of cycles = where the Second-level TLB (STLB) was missed by load accesses, performing a= hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THR= EAD", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_gro= up", + "MetricName": "tma_load_stlb_miss", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric roughly estimates fraction of cyc= les when the memory subsystem had loads blocked since they could not forwar= d data from earlier (in program order) overlapping stores", + "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED= .THREAD, 1)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "PublicDescription": "This metric roughly estimates fraction of cy= cles when the memory subsystem had loads blocked since they could not forwa= rd data from earlier (in program order) overlapping stores. To streamline m= emory operations in the pipeline; a load can avoid waiting for memory if a = prior in-flight store is writing the data that the load wants to read (stor= e forwarding process). However; in some cases the load may be blocked for a= significant time pending the store forward. For example; when the prior st= ore is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration= _time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of cycles the= CPU spent handling cache misses due to lock operations", + "MetricExpr": "min((12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_R= QSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES *= (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUT= STANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group"= , + "MetricName": "tma_lock_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / d= uration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "This metric estimates fraction of cycles hand= ling memory load split accesses - load that cross 64-byte cache line bounda= ry. ", + "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_= CLK_UNHALTED.THREAD, 1)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "ScaleUnit": "100%" }, { - "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", - "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_Silent_PKI" + "BriefDescription": "This metric estimates how often memory load a= ccesses were aliased by preceding stores (in program order) with a 4K addre= ss offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.= THREAD", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "PublicDescription": "This metric estimates how often memory load = accesses were aliased by preceding stores (in program order) with a 4K addr= ess offset. False match is possible; which incur a few cycles load re-issue= . However; the short re-issue duration is often hidden by the out-of-order = core and HW optimizations; hence a user may safely ignore a high value of t= his metric unless it manages to propagate up into parent nodes of the hiera= rchy (e.g. to L1_Bound).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", - "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_NonSilent_PKI" + "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", + "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\= \,cmask\\=3D0x1@ / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group= ", + "MetricName": "tma_fb_full", + "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cm= ask\\=3D0x1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2= _MISS) / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STA= LLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "PublicDescription": "This metric estimates how often the CPU was = stalled due to loads accesses to L3 cache or contended with a sibling Core.= Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency an= d increase performance.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", + "MetricExpr": "min(((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNH= ALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5= * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ /= 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM *= (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONS= E.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L= 3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UN= HALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.= 5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ = / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) = * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UN= HALTED.THREAD, 1)", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", + "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHA= LTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 = * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / = 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + M= EM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_= HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + ME= M_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.TH= READ, 1)", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_= group", + "MetricName": "tma_data_sharing", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited)", + "MetricExpr": "min((20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHA= LTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 = * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / = 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LO= AD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD= , 1)", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_grou= p", + "MetricName": "tma_l3_hit_latency", + "PublicDescription": "This metric represents fraction of cycles wi= th demand load accesses that hit the L3 cache under unloaded scenarios (pos= sibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L= 3 hits) will improve the latency; reduce contention with sibling physical c= ores and increase performance. Note the value of this node may overlap wit= h its siblings.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted proce= ssors [GHz]", - "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duratio= n_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bou= nd_group", + "MetricName": "tma_sq_full", + "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). The Super Queue is used for = requests to access the L2 cache or to go out to the Uncore.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARI= TH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUB= LE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.= 256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_AR= ITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACK= ED_SINGLE) / 1000000000) / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine." + "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", + "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTE= D.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS)= / CPU_CLK_UNHALTED.THREAD - tma_l2_bound, 1)", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", + "MetricName": "tma_dram_bound", + "PublicDescription": "This metric estimates how often the CPU was = stalled on accesses to external memory (DRAM) by loads. Better caching can = improve the latency and increase performance.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D0x4@) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group", + "MetricName": "tma_mem_bandwidth", + "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory (DRAM). The underlying heuristic assumes that a simi= lar off-core traffic is generated by all IA cores. This metric does not agg= regate non-data-read requests by this logical processor; requests from othe= r IA Logical Processors/Physical Cores/sockets; or other non-IA devices lik= e GPU; hence the maximum external memory bandwidth limits may or may not be= approached when this metric is flagged (see Uncore counters for that).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for baseline license level 0", - "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #S= MT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License0_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for baseline license level 0. This includes non= -AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory (DRAM= )", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group", + "MetricName": "tma_mem_latency", + "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory (DRA= M). This metric does not aggregate requests from other Logical Processors/= Physical Cores/sockets (see Uncore counters for that).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 1", - "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #S= MT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License1_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 1. This includes high current= AVX 256-bit instructions as well as low current AVX 512-bit instructions." + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from local memory", + "MetricExpr": "min((80 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALT= ED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 *= (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1= e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * = (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHA= LTED.THREAD, 1)", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_grou= p", + "MetricName": "tma_local_dram", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was ru= nning with power-delivery for license level 2 (introduced in SKX)", - "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #S= MT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License2_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was r= unning with power-delivery for license level 2 (introduced in SKX). This i= ncludes high current AVX 512-bit instructions." + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote memory", + "MetricExpr": "min((147.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNH= ALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.= 5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ = / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRA= M * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_= UNHALTED.THREAD, 1)", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latenc= y_group", + "MetricName": "tma_remote_dram", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from remote memory. This is caus= ed often due to non-optimal NUMA allocations. #link to NUMA article", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_U= NHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote cache in other socket= s including synchronizations issues", + "MetricExpr": "min(((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHA= LTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5= * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ /= 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM= + (110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC= _FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREA= D / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e= 3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_me= m_latency_group", + "MetricName": "tma_remote_cache", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from remote cache in other socke= ts including synchronizations issues. This is caused often due to non-optim= al NUMA allocations. #link to NUMA article", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THR= EAD", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", + "MetricName": "tma_store_bound", + "PublicDescription": "This metric estimates how often CPU was stal= led due to RFO store memory accesses; RFO store issue a read-for-ownership= request before the write. Even though store accesses do not typically stal= l out-of-order CPUs; there are few cases where stores can lead to actual st= alls. This metric will be flagged should RFO stores be a bottleneck.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k"= , - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK= _LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / = MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUEST= S_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store= _bound_group", + "MetricName": "tma_store_latency", + "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full)", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", - "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_= count_write@) / 1000000000) / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", + "MetricExpr": "min((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHAL= TED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFC= ORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3= _MISS.REMOTE_HITM) + 47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF= _TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFCORE_RES= PONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT= .HITM_OTHER_CORE)) / CPU_CLK_UNHALTED.THREAD, 1)", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_store_bound_group", + "MetricName": "tma_false_sharing", + "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. ", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches= ", - "MetricExpr": "1000000000 * (cha@event\\=3D0x36\\,umask\\=3D0x21\\= ,config\\=3D0x40433@ / cha@event\\=3D0x35\\,umask\\=3D0x21\\,config\\=3D0x4= 0433@) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "This metric represents rate of split store ac= cesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", + "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", + "MetricName": "tma_split_stores", + "PublicDescription": "This metric represents rate of split store a= ccesses. Consider aligning your data to the 64-byte cache line granularity= .", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel data read requests= to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "cha@event\\=3D0x36\\,umask\\=3D0x21\\,config\\=3D0x= 40433@ / cha@event\\=3D0x36\\,umask\\=3D0x21\\,config\\=3D0x40433\\,thresh\= \=3D1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", + "MetricExpr": "min((9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\= =3D0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS, 1)", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_g= roup", + "MetricName": "tma_dtlb_store", + "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of data read request to exter= nal DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-= read prefetches", - "MetricExpr": "1000000000 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSER= TS) / imc_0@event\\=3D0x0@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_DRAM_Read_Latency" + "BriefDescription": "This metric roughly estimates the fraction of= cycles where the TLB was missed by store accesses, hitting in the second-l= evel TLB (STLB)", + "MetricExpr": "tma_dtlb_store - DTLB_STORE_MISSES.WALK_ACTIVE / CO= RE_CLKS", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_gr= oup", + "MetricName": "tma_store_stlb_hit", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Writes [GB / sec]", - "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_D= ATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UN= C_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1000000000 / duration_time", - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Write_BW" + "BriefDescription": "This metric estimates the fraction of cycles = where the STLB was missed by store accesses, performing a hardware page wal= k", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_gr= oup", + "MetricName": "tma_store_stlb_miss", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Reads [GB / sec]", - "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_= DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 += UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1000000000 / duration_time"= , - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Read_BW" + "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_grou= p;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active = on that socket", - "MetricExpr": "cha_0@event\\=3D0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", + "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related)", + "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_= PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL)= ) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS= _TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + UO= PS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHA= LTED.THREAD)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup", + "MetricName": "tma_ports_utilization", + "PublicDescription": "This metric estimates fraction of cycles the= CPU performance was potentially limited due to Core computation issues (no= n divider-related). Two distinct categories can be attributed into this me= tric: (1) heavy data-dependency among contiguous instructions would manifes= t in this metric - such cases are often referred to as low Instruction Leve= l Parallelism (ILP). (2) Contention on some hardware execution unit other t= han Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency" + "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else= CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricName": "tma_ports_utilized_0", + "PublicDescription": "This metric represents fraction of cycles CP= U executed no uops on any execution port (Logical Processor cycles since IC= L, Physical Core cycles otherwise). Long-latency instructions like divides = may contribute to this metric.", + "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency" + "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.TH= READ", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group"= , + "MetricName": "tma_serializing_operation", + "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance.", + "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency" + "BriefDescription": "The Mixing_Vectors metric gives the percentag= e of injected blend uops out of all uops issued", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WI= DTH_MISMATCH / UOPS_ISSUED.ANY, 1)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group"= , + "MetricName": "tma_mixing_vectors", + "PublicDescription": "The Mixing_Vectors metric gives the percenta= ge of injected blend uops out of all uops issued. Usually a Mixing_Vectors = over 5% is worth investigating. Read more in Appendix B1 of the Optimizatio= ns Guide for this topic.", + "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency" + "BriefDescription": "This metric represents fraction of cycles whe= re the CPU executed total of 1 uop per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CO= RE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS"= , + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricName": "tma_ports_utilized_1", + "PublicDescription": "This metric represents fraction of cycles wh= ere the CPU executed total of 1 uop per cycle on all execution ports (Logic= al Processor cycles since ICL, Physical Core cycles otherwise). This can be= due to heavy data-dependency among software instructions; or over oversubs= cribing a particular hardware resource. In some other cases with high 1_Por= t_Utilized and L1_Bound; this metric can point to L1 data-cache latency bot= tleneck that may not necessarily manifest with complete execution starvatio= n (due to the short L1 latency e.g. walking a linked list) - looking at the= assembly can be helpful.", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency" + "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 2 uops per cycle on all execution ports (Logical Process= or cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CO= RE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS"= , + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricName": "tma_ports_utilized_2", + "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 2 uops per cycle on all execution ports (Logical Proces= sor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization = -most compilers feature auto-Vectorization options today- reduces pressure = on the execution ports as multiple elements are calculated with same uop.", + "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency" + "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else= UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricName": "tma_ports_utilized_3m", + "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT= .PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOT= S", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", + "MetricName": "tma_alu_op_utilization", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 100000000= 0", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd b= ranch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilizat= ion_group", + "MetricName": "tma_port_0", + "ScaleUnit": "100%" }, { - "BriefDescription": "CPU operating frequency (in GHz)", - "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_T= SC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time", - "MetricGroup": "", - "MetricName": "cpu_operating_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_grou= p", + "MetricName": "tma_port_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "loads_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] = ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_grou= p", + "MetricName": "tma_port_5", + "ScaleUnit": "100%" }, { - "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "stores_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple = ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_grou= p", + "MetricName": "tma_port_6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", - "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "l1d_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Load operations", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT= .PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 *= CORE_CLKS)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", + "MetricName": "tma_load_op_utilization", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "l1d_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [= ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_gro= up", + "MetricName": "tma_port_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", - "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [= ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_gro= up", + "MetricName": "tma_port_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "l2_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", + "MetricName": "tma_store_op_utilization", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", - "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "l2_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_gr= oup", + "MetricName": "tma_port_4", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "l2_demand_data_read_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_gr= oup", + "MetricName": "tma_port_7", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "l2_demand_code_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", + "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", + "MetricName": "tma_retiring", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. ", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12D= 4043300000000@ / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "llc_data_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RE= TIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS", + "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_ret= iring_group", + "MetricName": "tma_light_operations", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UPI metri= c) ratio of 1 or less should be expected for decently optimized software ru= nning on Intel Core/Xeon products. While this often indicates efficient X86= instructions were executed; high value does not necessarily mean better pe= rformance cannot be achieved.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x12C= C023300000000@ / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "llc_code_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.TH= READ + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", + "MetricName": "tma_fp_arith", + "PublicDescription": "This metric represents overall arithmetic fl= oating-point (FP) operations fraction the CPU has executed (retired). Note = this metric's value may exceed its parent due to use of \"Uops\" CountDomai= n and FMA double-counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) in nano seconds", - "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\= \,config1\\=3D0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\= \=3D0x4043300000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_package= s * #num_packages ) ) ) * duration_time", - "MetricGroup": "", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", - "ScaleUnit": "1ns" + "BriefDescription": "This metric serves as an approximation of leg= acy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.TH= READ", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group"= , + "MetricName": "tma_x87_use", + "PublicDescription": "This metric serves as an approximation of le= gacy x87 usage. It accounts for instructions beyond X87 FP arithmetic opera= tions; hence may be used as a thermometer to avoid X87 high usage and prefe= rably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to local m= emory in nano seconds", - "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\= \,config1\\=3D0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\= \=3D0x4043200000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_package= s * #num_packages ) ) ) * duration_time", - "MetricGroup": "", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _local_requests", - "ScaleUnit": "1ns" + "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group", + "MetricName": "tma_fp_scalar", + "PublicDescription": "This metric approximates arithmetic floating= -point (FP) scalar uops fraction the CPU has retired. May overcount due to = FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of a last level cache (LLC) d= emand and prefetch data read miss (read memory access) addressed to remote = memory in nano seconds", - "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\= \,config1\\=3D0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\= \=3D0x4043100000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_package= s * #num_packages ) ) ) * duration_time", - "MetricGroup": "", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for= _remote_requests", - "ScaleUnit": "1ns" + "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", + "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_= ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_D= OUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.51= 2B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED= .RETIRE_SLOTS, 1)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group", + "MetricName": "tma_fp_vector", + "PublicDescription": "This metric approximates arithmetic floating= -point (FP) vector uops fraction the CPU has retired aggregated across all = vector widths. May overcount due to FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions. This implies it missed in the ITLB (Instruction TLB) and further= levels of TLB.", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricGroup": "", - "MetricName": "itlb_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_= ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group", + "MetricName": "tma_fp_vector_128b", + "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 128-bit wide vectors. May overcount= due to FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions. This implies it missed in the Instruction = Translation Lookaside Buffer (ITLB) and further levels of TLB.", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", - "MetricGroup": "", - "MetricName": "itlb_large_page_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_= ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group", + "MetricName": "tma_fp_vector_256b", + "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 256-bit wide vectors. May overcount= due to FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions. This implies it missed in the DTLB and further levels of TL= B.", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY"= , - "MetricGroup": "", - "MetricName": "dtlb_load_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_= ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group", + "MetricName": "tma_fp_vector_512b", + "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 512-bit wide vectors. May overcount= due to FMA double counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions. This implies it missed in the Data Translation Looka= side Buffer (DTLB) and further levels of TLB.", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", - "MetricGroup": "", - "MetricName": "dtlb_2mb_large_page_load_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_memory_operations", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", - "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", - "MetricGroup": "", - "MetricName": "dtlb_store_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", + "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / U= OPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_fused_instructions", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JC= C are commonly used examples.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", - "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\= =3D0x4043200000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000= @ )", - "MetricGroup": "", - "MetricName": "numa_reads_addressed_to_local_dram", - "ScaleUnit": "1%" + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_non_fused_branches", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", - "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\= =3D0x4043100000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x404= 3200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=3D0x4043100000000= @ )", - "MetricGroup": "", - "MetricName": "numa_reads_addressed_to_remote_dram", - "ScaleUnit": "1%" + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETI= RED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_nop_instructions", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore operating frequency in GHz", - "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages= * #num_packages ) / 1000000000) / duration_time", - "MetricGroup": "", - "MetricName": "uncore_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes. May undercount due to FMA double counting", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_fused_instructions + tma_non_fused_branches + tma_no= p_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_other_light_ops", + "ScaleUnit": "100%" }, { - "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", - "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000= ) / duration_time", - "MetricGroup": "", - "MetricName": "upi_data_transmit_bw", - "ScaleUnit": "1MB/s" + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or microcoded sequences", + "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUS= ED - INST_RETIRED.ANY) / SLOTS", + "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_ret= iring_group", + "MetricName": "tma_heavy_operations", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or microcoded sequences. This highly-correlates with the= uop length of these instructions/sequences.", + "ScaleUnit": "100%" }, { - "BriefDescription": "DDR memory read bandwidth (MB/sec)", - "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_tim= e", - "MetricGroup": "", - "MetricName": "memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "tma_heavy_operations - UOPS_RETIRED.RETIRE_SLOTS / = UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group"= , + "MetricName": "tma_few_uops_instructions", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring instructions that that are decoder into two or up t= o ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number o= f uops in such instructions.", + "ScaleUnit": "100%" }, { - "BriefDescription": "DDR memory write bandwidth (MB/sec)", - "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_tim= e", - "MetricGroup": "", - "MetricName": "memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.M= S_UOPS / SLOTS", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operatio= ns_group", + "MetricName": "tma_microcode_sequencer", + "PublicDescription": "This metric represents fraction of slots the= CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The M= S is used for CISC instructions not supported by the default decoders (like= repeat move strings; or CPUID); or by microcode assists used to address so= me operation modes (like in Floating Point assists). These cases can often = be avoided.", + "ScaleUnit": "100%" }, { - "BriefDescription": "DDR memory bandwidth (MB/sec)", - "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 /= 1000000) / duration_time", - "MetricGroup": "", - "MetricName": "memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", + "MetricExpr": "min(100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLO= TS, 1)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricName": "tma_assists", + "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", - "MetricExpr": "(( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO= _DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000) / duration_time", - "MetricGroup": "", - "MetricName": "io_bandwidth_disk_or_network_writes", - "ScaleUnit": "1MB/s" + "BriefDescription": "This metric estimates fraction of cycles the = CPU retired uops originated from CISC (complex instruction set computer) in= struction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricName": "tma_cisc", + "PublicDescription": "This metric estimates fraction of cycles the= CPU retired uops originated from CISC (complex instruction set computer) i= nstruction. A CISC instruction has multiple uops that are required to perfo= rm the instruction's functionality as in the case of read-modify-write as a= n example. Since these instructions require multiple uops they may or may n= ot imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", - "MetricExpr": "(( UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_I= IO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PA= RT2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 ) * 4 / 1000000) / duration_= time", - "MetricGroup": "", - "MetricName": "io_bandwidth_disk_or_network_reads", - "ScaleUnit": "1MB/s" + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", - "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )", - "MetricGroup": "", - "MetricName": "percent_uops_delivered_from_decoded_icache", - "ScaleUnit": "1%" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", - "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )", - "MetricGroup": "", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline"= , - "ScaleUnit": "1%" + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )", - "MetricGroup": "", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", - "ScaleUnit": "1%" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", - "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / du= ration_time", - "MetricGroup": "", - "MetricName": "llc_miss_local_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", - "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / d= uration_time", - "MetricGroup": "", - "MetricName": "llc_miss_local_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", - "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / d= uration_time", - "MetricGroup": "", - "MetricName": "llc_miss_remote_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json index 62941146e396..8784118123b4 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json @@ -1,540 +1,514 @@ [ - { - "BriefDescription": "DRAM Page Activate commands sent due to a wri= te request", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_M_ACT_COUNT.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "iMC" - }, - { - "BriefDescription": "All DRAM Read CAS Commands issued (does not i= nclude underfills)", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_REG", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "iMC" - }, - { - "BriefDescription": "DRAM Underfill Read CAS Commands issued", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "iMC" - }, - { - "BriefDescription": "All DRAM Read CAS Commands issued (including = underfills)", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "iMC" - }, { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", - "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", + "PublicDescription": "Counts all CAS (Column Access Select) read c= ommands issued to DRAM on a per channel basis. CAS commands are issued to = specify the address to read or write on DRAM, and this event increments for= every read. This event includes underfill reads due to partial write requ= ests. This event counts whether AutoPrecharge (which closes the DRAM Page = automatically after a read/write) is enabled or not.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "iMC" }, - { - "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; D= RAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.WR_WMM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "iMC" - }, - { - "BriefDescription": "All DRAM Write CAS commands issued", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.WR", - "PerPkg": "1", - "UMask": "0xC", - "Unit": "iMC" - }, { "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", - "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", + "PublicDescription": "Counts all CAS (Column Address Select) comma= nds issued to DRAM per memory channel. CAS commands are issued to specify = the address to read or write on DRAM, and this event increments for every w= rite. This event counts whether AutoPrecharge (which closes the DRAM Page a= utomatically after a read/write) is enabled or not.", "ScaleUnit": "64Bytes", - "UMask": "0xC", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "All DRAM CAS Commands issued", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.ALL", + "BriefDescription": "DRAM Activate Count; Activate due to Bypass", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.BYP", "PerPkg": "1", - "UMask": "0xF", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Memory controller clock ticks", - "Counter": "0,1,2,3", - "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "DRAM Activate Count; Activate due to Read", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.RD", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", - "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "UNC_M_POWER_CHANNEL_PPD", - "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.= ", - "MetricName": "power_channel_ppd %", + "BriefDescription": "DRAM Page Activate commands sent due to a wri= te request", + "EventCode": "0x1", + "EventName": "UNC_M_ACT_COUNT.WR", "PerPkg": "1", + "PublicDescription": "Counts DRAM Page Activate commands sent on t= his channel due to a write request to the iMC (Memory Controller). Activat= e commands are issued to open up a page on the DRAM devices so that it can = be read or written to with a CAS (Column Access Select) command.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Cycles Memory is in self refresh power mode", - "Counter": "0,1,2,3", - "EventCode": "0x43", - "EventName": "UNC_M_POWER_SELF_REFRESH", - "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= .", - "MetricName": "power_self_refresh %", + "BriefDescription": "ACT command issued by 2 cycle bypass", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Pre-charges due to page misses", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", + "BriefDescription": "CAS command issued by 2 cycle bypass", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Pre-charge for reads", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M_PRE_COUNT.RD", + "BriefDescription": "PRE command issued by 2 cycle bypass", + "EventCode": "0xA1", + "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x10", - "EventName": "UNC_M_RPQ_INSERTS", + "BriefDescription": "All DRAM CAS Commands issued", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", + "PublicDescription": "Counts all CAS (Column Address Select) comma= nds issued to DRAM per memory channel. CAS commands are issued to specify = the address to read or write on DRAM, so this event increments for every re= ad and write. This event counts whether AutoPrecharge (which closes the DRA= M Page automatically after a read/write) is enabled or not.", + "UMask": "0xf", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M_RPQ_OCCUPANCY", + "BriefDescription": "All DRAM Read CAS Commands issued (including = underfills)", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", + "PublicDescription": "Counts all CAS (Column Access Select) read c= ommands issued to DRAM on a per channel basis. CAS commands are issued to = specify the address to read or write on DRAM, and this event increments for= every read. This event includes underfill reads due to partial write requ= ests. This event counts whether AutoPrecharge (which closes the DRAM Page = automatically after a read/write) is enabled or not.", + "UMask": "0x3", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_M_WPQ_INSERTS", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Read ISOCH Mode", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", "PerPkg": "1", + "UMask": "0x40", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x81", - "EventName": "UNC_M_WPQ_OCCUPANCY", + "BriefDescription": "All DRAM Read CAS Commands issued (does not i= nclude underfills)", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", + "PublicDescription": "Counts CAS (Column Access Select) regular re= ad commands issued to DRAM on a per channel basis. CAS commands are issued= to specify the address to read or write on DRAM, and this event increments= for every regular read. This event only counts regular reads and does not= includes underfill reads due to partial write requests. This event counts= whether AutoPrecharge (which closes the DRAM Page automatically after a re= ad/write) is enabled or not.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "DRAM Activate Count; Activate due to Read", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_M_ACT_COUNT.RD", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in RMM", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_RMM", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x20", "Unit": "iMC" }, { - "BriefDescription": "DRAM Activate Count; Activate due to Bypass", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_M_ACT_COUNT.BYP", + "BriefDescription": "DRAM Underfill Read CAS Commands issued", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "Counts CAS (Column Access Select) underfill = read commands issued to DRAM due to a partial write, on a per channel basis= . CAS commands are issued to specify the address to read or write on DRAM,= and this command counts underfill reads. Partial writes must be completed= by first reading in the underfill from DRAM and then merging in the partia= l write data before writing the full line back to DRAM. This event will gen= erally count about the same as the number of partial writes, but may be sli= ghtly less because of partials hitting in the WPQ (due to a previous write = request).", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "ACT command issued by 2 cycle bypass", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_M_BYP_CMDS.ACT", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in WMM", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.RD_WMM", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "CAS command issued by 2 cycle bypass", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_M_BYP_CMDS.CAS", + "BriefDescription": "All DRAM Write CAS commands issued", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Counts all CAS (Column Address Select) comma= nds issued to DRAM per memory channel. CAS commands are issued to specify = the address to read or write on DRAM, and this event increments for every w= rite. This event counts whether AutoPrecharge (which closes the DRAM Page a= utomatically after a read/write) is enabled or not.", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "PRE command issued by 2 cycle bypass", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_M_BYP_CMDS.PRE", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Write ISOCH Mode", + "EventCode": "0x4", + "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", "PerPkg": "1", - "UMask": "0x4", + "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; D= RAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", - "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", + "PublicDescription": "Counts the total number of Opportunistic DRA= M Write CAS commands issued on this channel while in Read-Major-Mode.", "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in WMM", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_WMM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "iMC" - }, - { - "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in RMM", - "Counter": "0,1,2,3", + "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; D= RAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_RMM", + "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the total number or DRAM Write CAS co= mmands issued on this channel while in Write-Major-Mode.", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Read ISOCH Mode", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", + "BriefDescription": "Memory controller clock ticks", + "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts clockticks of the fixed frequency clo= ck of the memory controller using one of the programmable counters.", "Unit": "iMC" }, { - "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Write ISOCH Mode", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", + "BriefDescription": "Clockticks in the Memory Controller using a d= edicated 48-bit Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_M_CLOCKTICKS_F", "PerPkg": "1", - "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge All Commands", - "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", + "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", "Unit": "iMC" }, { "BriefDescription": "Number of DRAM Refreshes Issued", - "Counter": "0,1,2,3", "EventCode": "0x5", - "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Number of DRAM Refreshes Issued", - "Counter": "0,1,2,3", "EventCode": "0x5", - "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Counts the number of refreshes issued.", + "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "ECC Correctable Errors", - "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", + "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { - "BriefDescription": "Cycles in a Major Mode; Read Major Mode", - "Counter": "0,1,2,3", + "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", "EventCode": "0x7", - "EventName": "UNC_M_MAJOR_MODES.READ", + "EventName": "UNC_M_MAJOR_MODES.ISOCH", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; We group these tw= o modes together so that we can use four counters to track each of the majo= r modes at one time. These major modes are used whenever there is an ISOCH= txn in the memory controller. In these mode, only ISOCH transactions are = processed.", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Cycles in a Major Mode; Write Major Mode", - "Counter": "0,1,2,3", + "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", "EventCode": "0x7", - "EventName": "UNC_M_MAJOR_MODES.WRITE", + "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode i= s used to drain starved underfill reads. Regular reads and writes are bloc= ked and only underfill reads will be processed.", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", - "Counter": "0,1,2,3", + "BriefDescription": "Cycles in a Major Mode; Read Major Mode", "EventCode": "0x7", - "EventName": "UNC_M_MAJOR_MODES.PARTIAL", + "EventName": "UNC_M_MAJOR_MODES.READ", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode i= s the default mode for the iMC, as reads are generally more critical to for= ward progress than writes.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", - "Counter": "0,1,2,3", + "BriefDescription": "Cycles in a Major Mode; Write Major Mode", "EventCode": "0x7", - "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is trig= gered when the WPQ hits high occupancy and causes writes to be higher prior= ity than reads. This can cause blips in the available read bandwidth in th= e system and temporarily increase read latencies in order to achieve better= bus utilizations and higher bandwidth.", + "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Channel DLLOFF Cycles", - "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", "PerPkg": "1", + "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in CKE Slow (DLLOFF) mode.", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "EventCode": "0x85", + "EventName": "UNC_M_POWER_CHANNEL_PPD", + "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100"= , + "MetricName": "power_channel_ppd", + "PerPkg": "1", + "PublicDescription": "Counts cycles when all the ranks in the chan= nel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminator= s)=3Doff is enabled, then this event counts the cycles in PPD mode. If IBT= =3Doff is not enabled, then this event counts the number of cycles when bei= ng in PPD mode could have been taken advantage of.", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", "PerPkg": "1", + "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Critical Throttle Cycles", - "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC is = in critical thermal throttling. When this happens, all traffic is blocked.= This should be rare unless something bad is going on in the platform. Th= ere is no filtering by rank for this event.", "Unit": "iMC" }, { "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", - "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", "PerPkg": "1", "Unit": "iMC" }, + { + "BriefDescription": "Cycles Memory is in self refresh power mode", + "EventCode": "0x43", + "EventName": "UNC_M_POWER_SELF_REFRESH", + "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= ", + "MetricName": "power_self_refresh", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the iMC (me= mory controller) is in self-refresh and has a clock. This happens in some A= CPI CPU package C-states for the sleep levels. For example, the PCU (Power = Control Unit) may ask the iMC to enter self-refresh even though some of the= cores are still processing. One use of this is for Intel? Dynamic Power Te= chnology. Self-refresh is required during package C3 and C6, but there is = no clock in the iMC at this time, so it is not possible to count these case= s.", + "Unit": "iMC" + }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.; Thermal throttling is performed= per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by= ID.", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", - "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts another read.", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", "PerPkg": "1", + "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts a write.", "UMask": "0x2", "Unit": "iMC" }, + { + "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.BYP", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", + "UMask": "0x10", + "Unit": "iMC" + }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", - "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.; Counts the number of DRAM Precharge commands sent o= n this channel as a result of the page close counter expiring. This does n= ot include implicit precharge commands sent in auto-precharge mode.", "UMask": "0x2", "Unit": "iMC" }, + { + "BriefDescription": "Pre-charges due to page misses", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of explicit DRAM Precharge= commands sent on this channel as a result of a DRAM page miss. This does n= ot include the implicit precharge commands sent with CAS commands in Auto-P= recharge mode. This does not include Precharge commands sent as a result of= a page close counter expiration.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Pre-charge for reads", + "EventCode": "0x2", + "EventName": "UNC_M_PRE_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of explicit DRAM Precharge= commands issued on a per channel basis due to a read, so as to close the p= revious DRAM page, before opening the requested page.", + "UMask": "0x4", + "Unit": "iMC" + }, { "BriefDescription": "Pre-charge for writes", - "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", + "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M_PRE_COUNT.BYP", + "BriefDescription": "Read CAS issued with HIGH priority", + "EventCode": "0xA0", + "EventName": "UNC_M_RD_CAS_PRIO.HIGH", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Read CAS issued with LOW priority", - "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", "PerPkg": "1", @@ -543,7 +517,6 @@ }, { "BriefDescription": "Read CAS issued with MEDIUM priority", - "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", "PerPkg": "1", @@ -551,26 +524,23 @@ "Unit": "iMC" }, { - "BriefDescription": "Read CAS issued with HIGH priority", - "Counter": "0,1,2,3", + "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", "EventCode": "0xA0", - "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "EventName": "UNC_M_RD_CAS_PRIO.PANIC", "PerPkg": "1", - "UMask": "0x4", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "EventCode": "0xB0", + "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", - "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", @@ -578,7 +548,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", - "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", @@ -586,143 +555,119 @@ "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", - "UMask": "0x2", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", - "UMask": "0x3", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", - "UMask": "0x4", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", - "UMask": "0x5", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", - "UMask": "0x6", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK7", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK8", + "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0xf", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK9", + "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", - "UMask": "0x9", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK10", + "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x3", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK11", + "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK12", + "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x5", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK13", + "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x6", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK14", + "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x7", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.BANK15", + "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", - "UMask": "0xF", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 0; All Banks", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", "EventCode": "0xB0", - "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -731,7 +676,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -740,7 +684,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -749,16 +692,22 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, + { + "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", @@ -766,16 +715,62 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "PerPkg": "1", + "UMask": "0xb", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "PerPkg": "1", + "UMask": "0xd", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "PerPkg": "1", + "UMask": "0xe", + "Unit": "iMC" + }, + { + "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "EventCode": "0xB1", + "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "iMC" + }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", @@ -784,7 +779,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", @@ -793,7 +787,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", @@ -802,7 +795,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", @@ -811,7 +803,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", @@ -820,7 +811,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", @@ -829,7 +819,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", @@ -838,7 +827,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", @@ -846,124 +834,110 @@ "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "BriefDescription": "RD_CAS Access to Rank 2; All Banks", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", + "EventCode": "0xB2", + "EventName": "UNC_M_RD_CAS_RANK2.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "EventName": "UNC_M_RD_CAS_RANK2.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK1", + "EventName": "UNC_M_RD_CAS_RANK2.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK2", "PerPkg": "1", @@ -972,7 +946,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK3", "PerPkg": "1", @@ -981,7 +954,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK4", "PerPkg": "1", @@ -990,7 +962,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK5", "PerPkg": "1", @@ -999,7 +970,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK6", "PerPkg": "1", @@ -1008,7 +978,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK7", "PerPkg": "1", @@ -1017,7 +986,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK8", "PerPkg": "1", @@ -1026,7 +994,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK9", "PerPkg": "1", @@ -1034,124 +1001,110 @@ "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK10", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK11", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK12", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK13", + "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK14", + "BriefDescription": "RD_CAS Access to Rank 3; All Banks", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANK15", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", + "EventCode": "0xB3", + "EventName": "UNC_M_RD_CAS_RANK3.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK0", + "EventName": "UNC_M_RD_CAS_RANK3.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK1", + "EventName": "UNC_M_RD_CAS_RANK3.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK2", "PerPkg": "1", @@ -1160,7 +1113,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK3", "PerPkg": "1", @@ -1169,7 +1121,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK4", "PerPkg": "1", @@ -1178,7 +1129,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK5", "PerPkg": "1", @@ -1187,7 +1137,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK6", "PerPkg": "1", @@ -1196,7 +1145,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK7", "PerPkg": "1", @@ -1205,7 +1153,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK8", "PerPkg": "1", @@ -1214,7 +1161,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK9", "PerPkg": "1", @@ -1222,124 +1168,110 @@ "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK10", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK11", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK12", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK13", + "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK14", + "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANK15", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "EventCode": "0xB4", + "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", @@ -1348,7 +1280,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", @@ -1357,7 +1288,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", @@ -1366,7 +1296,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", @@ -1375,7 +1304,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", @@ -1384,7 +1312,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", @@ -1393,7 +1320,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", @@ -1402,7 +1328,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", @@ -1410,124 +1335,110 @@ "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK10", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK11", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK12", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK13", + "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK14", + "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANK15", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "EventCode": "0xB5", + "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", @@ -1536,7 +1447,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", @@ -1545,7 +1455,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", @@ -1554,7 +1463,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", @@ -1563,7 +1471,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", @@ -1572,7 +1479,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", @@ -1581,7 +1487,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", @@ -1590,7 +1495,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", @@ -1598,124 +1502,110 @@ "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK10", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK11", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK12", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK13", + "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK14", + "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANK15", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xB5", - "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "EventCode": "0xB6", + "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", @@ -1724,7 +1614,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", @@ -1733,7 +1622,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", @@ -1742,7 +1630,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", @@ -1751,7 +1638,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", @@ -1760,7 +1646,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", @@ -1769,7 +1654,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", @@ -1778,7 +1662,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", @@ -1786,124 +1669,110 @@ "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK10", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK11", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK12", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK13", + "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK14", + "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANK15", + "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", + "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", + "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", + "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xB6", - "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", + }, + { + "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "EventCode": "0xB7", + "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", @@ -1912,7 +1781,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", @@ -1921,7 +1789,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", @@ -1930,7 +1797,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", @@ -1939,7 +1805,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", @@ -1948,7 +1813,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", @@ -1957,7 +1821,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", @@ -1966,79 +1829,14 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, - { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", - "Counter": "0,1,2,3", - "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK10", - "PerPkg": "1", - "UMask": "0xA", - "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", - "Counter": "0,1,2,3", - "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK11", - "PerPkg": "1", - "UMask": "0xB", - "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", - "Counter": "0,1,2,3", - "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK12", - "PerPkg": "1", - "UMask": "0xC", - "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", - "Counter": "0,1,2,3", - "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK13", - "PerPkg": "1", - "UMask": "0xD", - "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK14", - "PerPkg": "1", - "UMask": "0xE", - "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.BANK15", - "PerPkg": "1", - "UMask": "0xF", - "Unit": "iMC" - }, - { - "BriefDescription": "RD_CAS Access to Rank 7; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xB7", - "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "iMC" - }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -2047,7 +1845,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -2056,7 +1853,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -2065,7 +1861,6 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", @@ -2074,23 +1869,38 @@ }, { "BriefDescription": "Read Pending Queue Full Cycles", - "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M_RPQ_CYCLES_FULL", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the Read Pe= nding Queue is full. When the RPQ is full, the HA will not be able to issu= e any additional read requests into the iMC. This count should be similar = count in the HA which tracks the number of cycles that the HA has no RPQ cr= edits, just somewhat smaller to account for the credit return overhead. We= generally do not expect to see RPQ become full except for potentially duri= ng Write Major Mode or while running with slow DRAM. This event only track= s non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Not Empty", - "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Read Pe= nding Queue is not empty. This can then be used to calculate the average o= ccupancy (in conjunction with the Read Pending Queue Occupancy count). The= RPQ is used to schedule reads out to the memory controller and to track th= e requests. Requests allocate into the RPQ soon after they enter the memor= y controller, and need credits for an entry in this buffer before being sen= t from the HA to the iMC. They deallocate after the CAS command has been i= ssued to memory. This filter is to be used in conjunction with the occupan= cy filter so that one can correctly track the average occupancies for sched= ulable entries and scheduled requests.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of read requests allocated= into the Read Pending Queue (RPQ). This queue is used to schedule reads o= ut to the memory controller and to track the requests. Requests allocate i= nto the RPQ soon after they enter the memory controller, and need credits f= or an entry in this buffer before being sent from the CHA to the iMC. The = requests deallocate after the read CAS command has been issued to DRAM. Th= is event counts both Isochronous and non-Isochronous requests which were is= sued to the RPQ.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries in the Read Pen= ding Queue (RPQ) at each cycle. This can then be used to calculate both th= e average occupancy of the queue (in conjunction with the number of cycles = not empty) and the average latency in the queue (in conjunction with the nu= mber of allocations). The RPQ is used to schedule reads out to the memory = controller and to track the requests. Requests allocate into the RPQ soon = after they enter the memory controller, and need credits for an entry in th= is buffer before being sent from the CHA to the iMC. They deallocate from t= he RPQ after the CAS command has been issued to memory.", "Unit": "iMC" }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", - "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", "PerPkg": "1", @@ -2099,7 +1909,6 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", - "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", "PerPkg": "1", @@ -2108,7 +1917,6 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", - "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "PerPkg": "1", @@ -2117,199 +1925,196 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", - "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the Write P= ending Queue is full. When the WPQ is full, the HA will not be able to iss= ue any additional write requests into the iMC. This count should be simila= r count in the CHA which tracks the number of cycles that the CHA has no WP= Q credits, just somewhat smaller to account for the credit return overhead.= ", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Not Empty", - "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Write P= ending Queue is not empty. This can then be used to calculate the average = queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).= The WPQ is used to schedule write out to the memory controller and to tra= ck the writes. Requests allocate into the WPQ soon after they enter the me= mory controller, and need credits for an entry in this buffer before being = sent from the CHA to the iMC. They deallocate after being issued to DRAM. = Write requests themselves are able to complete (from the perspective of th= e rest of the system) as soon they have posted to the iMC. This is not to = be confused with actually performing the write to DRAM. Therefore, the ave= rage latency for this queue is actually not useful for deconstruction inter= mediate write latencies.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of writes requests allocat= ed into the Write Pending Queue (WPQ). The WPQ is used to schedule writes = out to the memory controller and to track the requests. Requests allocate = into the WPQ soon after they enter the memory controller, and need credits = for an entry in this buffer before being sent from the CHA to the iMC (Memo= ry Controller). The write requests deallocate after being issued to DRAM. = Write requests themselves are able to complete (from the perspective of th= e rest of the system) as soon they have 'posted' to the iMC.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "EventCode": "0x81", + "EventName": "UNC_M_WPQ_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries in the Write Pe= nding Queue (WPQ) at each cycle. This can then be used to calculate both t= he average queue occupancy (in conjunction with the number of cycles not em= pty) and the average latency (in conjunction with the number of allocations= ). The WPQ is used to schedule writes out to the memory controller and to = track the requests. Requests allocate into the WPQ soon after they enter t= he memory controller, and need credits for an entry in this buffer before b= eing sent from the CHA to the iMC (memory controller). They deallocate aft= er being issued to DRAM. Write requests themselves are able to complete (f= rom the perspective of the rest of the system) as soon they have 'posted' t= o the iMC. This is not to be confused with actually performing the write t= o DRAM. Therefore, the average latency for this queue is actually not usef= ul for deconstruction intermediate write latencies. So, we provide filteri= ng based on if the request has posted or not. By using the 'not posted' fi= lter, we can track how long writes spent in the iMC before completions were= sent to the HA. The 'posted' filter, on the other hand, provides informat= ion about how much queueing is actually happenning in the iMC for writes be= fore they are actually issued to memory. High average occupancies will gen= erally coincide with high write major mode counts. Is there a filter of sor= ts???", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue CAM Match", - "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue CAM Match", - "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", "PerPkg": "1", + "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", "Unit": "iMC" }, { "BriefDescription": "Not getting the requested Major Mode", - "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", "PerPkg": "1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; All Banks", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", - "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", - "UMask": "0x2", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", - "UMask": "0x3", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", - "UMask": "0x4", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", - "UMask": "0x5", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", - "UMask": "0x6", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", - "UMask": "0x7", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK8", + "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0xf", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK9", + "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", - "UMask": "0x9", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK10", + "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x3", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK11", + "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK12", + "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x5", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK13", + "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x6", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK14", + "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x7", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.BANK15", + "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", - "UMask": "0xF", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 0; All Banks", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", "EventCode": "0xB8", - "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -2318,7 +2123,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -2327,7 +2131,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -2336,7 +2139,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", @@ -2344,160 +2146,142 @@ "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; All Banks", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", - "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", - "UMask": "0x2", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", - "UMask": "0x3", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", - "UMask": "0x4", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", - "UMask": "0x5", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", - "UMask": "0x6", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", - "UMask": "0x7", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK8", + "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0xf", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK9", + "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", - "UMask": "0x9", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK10", + "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x3", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK11", + "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK12", + "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x5", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK13", + "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x6", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK14", + "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x7", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.BANK15", + "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", - "UMask": "0xF", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 1; All Banks", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", "EventCode": "0xB9", - "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", @@ -2506,7 +2290,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", @@ -2515,7 +2298,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", @@ -2524,16 +2306,22 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, + { + "BriefDescription": "WR_CAS Access to Rank 2; All Banks", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK0", "PerPkg": "1", @@ -2541,16 +2329,62 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 10", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK10", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 11", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK11", + "PerPkg": "1", + "UMask": "0xb", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 12", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK12", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 13", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK13", + "PerPkg": "1", + "UMask": "0xd", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 14", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK14", + "PerPkg": "1", + "UMask": "0xe", + "Unit": "iMC" + }, + { + "BriefDescription": "WR_CAS Access to Rank 2; Bank 15", + "EventCode": "0xBA", + "EventName": "UNC_M_WR_CAS_RANK2.BANK15", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "iMC" + }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK2", "PerPkg": "1", @@ -2559,7 +2393,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK3", "PerPkg": "1", @@ -2568,7 +2401,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK4", "PerPkg": "1", @@ -2577,7 +2409,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK5", "PerPkg": "1", @@ -2586,7 +2417,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK6", "PerPkg": "1", @@ -2595,7 +2425,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK7", "PerPkg": "1", @@ -2604,7 +2433,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK8", "PerPkg": "1", @@ -2613,7 +2441,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK9", "PerPkg": "1", @@ -2621,124 +2448,110 @@ "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANK10", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANK11", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANK12", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANK13", + "EventName": "UNC_M_WR_CAS_RANK2.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANK14", + "BriefDescription": "WR_CAS Access to Rank 3; All Banks", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANK15", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANKG0", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 10", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANKG1", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 11", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANKG2", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 12", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xBA", - "EventName": "UNC_M_WR_CAS_RANK2.BANKG3", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 13", + "EventCode": "0xBB", + "EventName": "UNC_M_WR_CAS_RANK3.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 14", "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK0", + "EventName": "UNC_M_WR_CAS_RANK3.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 3; Bank 15", "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK1", + "EventName": "UNC_M_WR_CAS_RANK3.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK2", "PerPkg": "1", @@ -2747,7 +2560,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK3", "PerPkg": "1", @@ -2756,7 +2568,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK4", "PerPkg": "1", @@ -2765,7 +2576,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK5", "PerPkg": "1", @@ -2774,7 +2584,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK6", "PerPkg": "1", @@ -2783,7 +2592,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK7", "PerPkg": "1", @@ -2792,7 +2600,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK8", "PerPkg": "1", @@ -2801,7 +2608,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK9", "PerPkg": "1", @@ -2809,124 +2615,110 @@ "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK10", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK11", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK12", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK13", + "EventName": "UNC_M_WR_CAS_RANK3.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK14", + "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANK15", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANKG0", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANKG1", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANKG2", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xBB", - "EventName": "UNC_M_WR_CAS_RANK3.BANKG3", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "EventCode": "0xBC", + "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", @@ -2935,7 +2727,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", @@ -2944,7 +2735,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", @@ -2953,7 +2743,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", @@ -2962,7 +2751,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", @@ -2971,7 +2759,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", @@ -2980,7 +2767,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", @@ -2989,7 +2775,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", @@ -2997,124 +2782,110 @@ "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK10", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK11", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK12", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK13", + "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK14", + "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANK15", + "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, - { - "BriefDescription": "WR_CAS Access to Rank 4; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", + { + "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", + "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", + "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", + "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xBC", - "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", + "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "EventCode": "0xBD", + "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", @@ -3123,7 +2894,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", @@ -3132,7 +2902,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", @@ -3141,7 +2910,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", @@ -3150,7 +2918,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", @@ -3159,7 +2926,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", @@ -3168,7 +2934,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", @@ -3177,7 +2942,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", @@ -3185,124 +2949,110 @@ "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK10", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK11", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK12", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK13", + "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK14", + "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANK15", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "EventCode": "0xBE", + "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK0", + "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK1", + "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", @@ -3311,7 +3061,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", @@ -3320,7 +3069,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", @@ -3329,7 +3077,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", @@ -3338,7 +3085,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", @@ -3347,7 +3093,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", @@ -3356,7 +3101,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", @@ -3365,7 +3109,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", @@ -3373,124 +3116,110 @@ "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK10", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", - "UMask": "0xA", + "UMask": "0x11", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK11", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", - "UMask": "0xB", + "UMask": "0x12", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK12", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", - "UMask": "0xC", + "UMask": "0x13", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK13", + "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", - "UMask": "0xD", + "UMask": "0x14", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK14", + "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", - "UMask": "0xE", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANK15", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", - "UMask": "0xF", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", - "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0xa", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", - "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", - "UMask": "0x12", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", - "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", - "UMask": "0x13", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", - "EventCode": "0xBE", - "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "EventCode": "0xBF", + "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0xd", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", + "UMask": "0xe", "Unit": "iMC" }, { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", - "Counter": "0,1,2,3", + "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", @@ -3499,7 +3228,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", @@ -3508,7 +3236,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", @@ -3517,7 +3244,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", @@ -3526,7 +3252,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", @@ -3535,7 +3260,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", @@ -3544,7 +3268,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", @@ -3553,79 +3276,14 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, - { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", - "Counter": "0,1,2,3", - "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK10", - "PerPkg": "1", - "UMask": "0xA", - "Unit": "iMC" - }, - { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", - "Counter": "0,1,2,3", - "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK11", - "PerPkg": "1", - "UMask": "0xB", - "Unit": "iMC" - }, - { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", - "Counter": "0,1,2,3", - "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK12", - "PerPkg": "1", - "UMask": "0xC", - "Unit": "iMC" - }, - { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", - "Counter": "0,1,2,3", - "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK13", - "PerPkg": "1", - "UMask": "0xD", - "Unit": "iMC" - }, - { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", - "Counter": "0,1,2,3", - "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK14", - "PerPkg": "1", - "UMask": "0xE", - "Unit": "iMC" - }, - { - "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", - "Counter": "0,1,2,3", - "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.BANK15", - "PerPkg": "1", - "UMask": "0xF", - "Unit": "iMC" - }, - { - "BriefDescription": "WR_CAS Access to Rank 7; All Banks", - "Counter": "0,1,2,3", - "EventCode": "0xBF", - "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "iMC" - }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -3634,7 +3292,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -3643,7 +3300,6 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -3652,19 +3308,10 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", - "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" - }, - { - "BriefDescription": "Clockticks in the Memory Controller using a d= edicated 48-bit Fixed Counter", - "Counter": "FIXED", - "EventCode": "0xff", - "EventName": "UNC_M_CLOCKTICKS_F", - "PerPkg": "1", - "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/to= ols/perf/pmu-events/arch/x86/skylakex/uncore-other.json index 0d106fe7aae3..3cf8b7c458ba 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json @@ -1,8248 +1,12229 @@ [ { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CLOCKTICKS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventName": "UNC_C_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple Core Reque= sts", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", - "PerPkg": "1", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=3D0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DA= TA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC= _IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", "PerPkg": "1", - "UMask": "0x82", - "Unit": "CHA" + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by IIO Part0 to a unit on the main die (generally memory). In the ge= neral case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) th= at is plugged directly into one of the PCIe slots. Part0 could also refer t= o any device plugged into the first slot of a PCIe riser card or to a devic= e attached to the IIO unit which starts its use of the bus using lane 0 of = the 16 lanes supported by the bus.", + "ScaleUnit": "4Bytes", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Needed", - "Counter": "0,1,2,3", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_WRITE", + "FCMask": "0x07", + "Filter": "ch_mask=3D0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_D= ATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", "PerPkg": "1", - "UMask": "0x01", - "Unit": "CHA" + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made by IIO Part0 to a unit on the main die (generally memory). In the ge= neral case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) th= at is plugged directly into one of the PCIe slots. Part0 could also refer t= o any device plugged into the first slot of a PCIe riser card or to a devic= e attached to the IIO unit which starts its use of the bus using lane 0 of = the 16 lanes supported by the bus.", + "ScaleUnit": "4Bytes", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Not Needed", - "Counter": "0,1,2,3", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from the HA pipe", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.HA", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from TOR pipe", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Read request from a remote socket which hit i= n the HitMe Cache to a line In the E state", - "Counter": "0,1,2,3", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x3", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x9", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.S_STATE", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Number of times that an RFO hit in S state", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "read requests from home agent", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "write requests from home agent", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x0C", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "read requests from local home agent", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "write requests from local home agent", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "RspIFwd Snoop Responses Received", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "RspSFwd Snoop Responses Received", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x31", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x31", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.REM_ALL", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x30", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_FAST_ASSERTED.HORZ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0xA5", - "EventName": "UNC_C_FAST_ASSERTED", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_HIT", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_HIT", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x14", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_MISS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x24", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; Hits from Local IO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x14", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; Misses from Local IO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x24", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; All from Local iA", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x31", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; Hits from Local iA", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; All from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x31", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Hits from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Misses from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0= Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "FaST wire asserted; Horizontal", - "Counter": "0,1,2,3", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the uncore caching & home agent= (CHA)", - "Counter": "0,1,2,3", - "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", - "Counter": "0,1,2,3", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line= Non-ISOCH", - "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Read requests from a remote socket", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken"= , + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that succeeded in taking the intermediate bypass.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "RspI Snoop Responses Received", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "BriefDescription": "CHA to iMC Bypass; Not Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that could not take the bypass, and issues a read to memory.= Note that transactions that did not take the bypass but did not issue read= to memory will not be counted.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Rsp*WB Snoop Responses Received", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", + "BriefDescription": "CHA to iMC Bypass; Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that succeeded in taking the full bypass.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "RspCnflct* Snoop Responses Received", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "BriefDescription": "Clockticks of the uncore caching & home agent= (CHA)", + "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts clockticks of the clock controlling t= he uncore caching and home agent (CHA).", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries", - "Counter": "0,1,2,3", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries", - "Counter": "0,1,2,3", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "BriefDescription": "Core PMA Events; C1 State", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_STATE", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries", - "Counter": "0,1,2,3", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "BriefDescription": "Core PMA Events; C1 Transition", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "BriefDescription": "Core PMA Events; C6 State", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_STATE", "PerPkg": "1", - "UMask": "0x30", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in M state", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "BriefDescription": "Core PMA Events; C6 Transition", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in E state", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "BriefDescription": "Core PMA Events; GV", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.GV", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in S State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Mult= iple Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0xe2", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Lines in F State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", + "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0xe1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hi= t the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", - "Filter": "config1=3D0x40433", + "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote= Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0xe4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", - "Filter": "config1=3D0x40233", + "BriefDescription": "Core Cross Snoops Issued; Multiple Core Reque= sts", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x42", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "Filter": "config1=3D0x40033", + "BriefDescription": "Core Cross Snoops Issued; Single Core Request= s", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x41", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "Filter": "config1=3D0x4b433", + "BriefDescription": "Core Cross Snoops Issued; Core Request to Rem= ote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "Filter": "config1=3D0x4b233", + "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x82", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat hit the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", - "Filter": "config1=3D0x4b033", + "BriefDescription": "Core Cross Snoops Issued; Single Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x81", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "Filter": "config1=3D0x40433", + "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote = Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x84", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", - "Filter": "config1=3D0x40233", + "BriefDescription": "Core Cross Snoops Issued; Multiple External S= noops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x22", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "Filter": "config1=3D0x40033", + "BriefDescription": "Core Cross Snoops Issued; Single External Sno= ops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", - "Filter": "config1=3D0x4b433", + "BriefDescription": "Core Cross Snoops Issued; External Snoop to R= emote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "Filter": "config1=3D0x4b233", + "BriefDescription": "Counter 0 Occupancy", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Since occupancy counts can only be captured = in the Cbo's 0 counter, this event allows a user to capture occupancy relat= ed information by filtering the Cb0 occupancy count captured in Counter 0. = The filtering available is found in the control register - threshold, inv= ert and edge detect. E.g. setting threshold to 1 can effectively monitor = how many cycles the monitored queue has an entry.", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat missed the LLC", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", - "Filter": "config1=3D0x4b033", + "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Not Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Counts transactions that looked into the mul= ti-socket cacheline Directory state, and therefore did not send a snoop bec= ause the Directory indicated it was not needed", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "Filter": "config1=3D0x40433", + "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts transactions that looked into the mu= lti-socket cacheline Directory state, and sent one or more snoops, because = the Directory indicated it was needed", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "Filter": "config1=3D0x40233", + "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from the HA pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts only multi-socket cacheline Directory= state updates memory writes issued from the HA pipe. This does not include= memory write requests which are for I (Invalid) or E (Exclusive) cacheline= s.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "Filter": "config1=3D0x40033", + "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from TOR pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts only multi-socket cacheline Directory= state updates due to memory writes issued from the TOR pipe which are the = result of remote transaction hitting the SF/LLC and returning data Core2Cor= e. This does not include memory write requests which are for I (Invalid) or= E (Exclusive) cachelines.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "Filter": "config1=3D0x4b433", + "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "Filter": "config1=3D0x4b233", + "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", - "Filter": "config1=3D0x4b033", + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "Filter": "config1=3D0x40433", + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.VERT", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "Filter": "config1=3D0x40233", + "BriefDescription": "Read request from a remote socket which hit i= n the HitMe Cache to a line In the E state", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.EX_RDS", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Counts read requests from a remote socket wh= ich hit in the HitME cache (used to cache the multi-socket Directory state)= to a line in the E(Exclusive) state. This includes the following read opc= odes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "Filter": "config1=3D0x40033", + "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared = hit and op is RdInvOwn, RdInv, Inv*", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "Filter": "config1=3D0x4b433", + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "Filter": "config1=3D0x4b233", + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "Filter": "config1=3D0x4b033", + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the IIO Traffic Controller", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", - "FCMask": "0x7", + "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF= /LLC HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", - "FCMask": "0x7", + "BriefDescription": "Counts Number of Misses in HitMe Cache; op is= RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", - "FCMask": "0x7", + "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LL= C HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", - "FCMask": "0x7", + "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Deallocate HtiME$ on Reads without RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", - "FCMask": "0x7", + "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a local request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" + "PublicDescription": "Received RspFwdI* for a local request, but c= onverted HitME$ to SF entry", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", - "FCMask": "0x7", + "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", - "FCMask": "0x7", + "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a remote request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" + "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E r= eceived for a remote request", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", - "FCMask": "0x7", + "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache to SHARed", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", "PerPkg": "1", - "PortMask": "0x8", "UMask": "0x4", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part0 by= the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part1 by= the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part2 by= the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Write request of 4 bytes made to IIO Part3 by= the CPU", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part1 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part2 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part3 by a different IIO unit", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part1", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part2", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part3", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part1", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part2", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts when a normal (Non-Isochronous) read = is issued to any of the memory controller channels from the CHA.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part3", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "HA to iMC Reads Issued; ISOCH", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Count of the number of reads issued to any o= f the memory controller channels. This can be filtered by the priority of = the reads.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 0"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line= Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts when a normal (Non-Isochronous) full = line write is issued from the CHA to the any of the memory controller chann= els.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 1"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Writes Issued to the iMC by the HA; Full Line= MIG", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 2"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Ful= l Line", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" - }, + "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x4", + "Unit": "CHA" + }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 3"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Writes Issued to the iMC by the HA; Partial N= on-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=3D0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_D= ATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", + "BriefDescription": "Writes Issued to the iMC by the HA; Partial M= IG", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory c= ontroller 5 only.", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Par= tial", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations dropped due to IODC Full", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IDOC allocation dropped due to OSB gate", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 0"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to any reason", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.ALL", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 1"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to conflicting transaction", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 2"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoE", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 3"= , - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoI", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", - "FCMask": "0x07", - "Filter": "ch_mask=3D0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DA= TA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC= _IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", + "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbPushMtoI", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Moved to Cbo section", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part0 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", + "UMask": "0x11", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part1 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Read transactions", + "UMask": "0x3", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part2 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Cache and Snoop Filter Lookups; Local", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.", + "UMask": "0x31", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part3 to an IIO target", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "Cache and Snoop Filter Lookups; Remote", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.", + "UMask": "0x91", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part0 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "Cache and Snoop Filter Lookups; External Snoo= p Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for only snoop requests c= oming from the remote socket(s) through the IPQ.", + "UMask": "0x9", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part1 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Cache and Snoop Filter Lookups; Write Request= s", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to= the LLC This includes all write transactions -- both Cacheable and UC.", + "UMask": "0x5", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part2 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part3 by the CPU", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part0 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part1 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Local - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2f", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part2 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Local - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x22", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part3 by a different IIO unit", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Local - Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x28", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Local - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part1", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Local - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x24", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part2", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part3", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part0", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Remote - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8f", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part1", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Remote - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x82", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part2", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Remote - Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x88", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part3", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Remote - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x81", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part0 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Remote - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x84", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part1 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part2 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Lines in E state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part3 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part0 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Lines in M state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part1 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "Lines Victimized; Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part2 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part3 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part0 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "Number of times that an RFO hit in S state.", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts when a RFO (the Read for Ownership is= sued before a write) request hit a cacheline in the S (Shared) state.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part1 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times when a Snoop hit in FSE states and triggered a silent evic= tion. This is useful because this information is lost in the PRE encodings= .", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part2 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times that a USWC write (WCIL(F)) transaction hit in the LLC in = M state, triggering a WBMtoI followed by the USWC write. This occurs when = there is WC aliasing.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part3 to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "OSB Snoop Broadcast", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part0 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part1 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part2 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x08", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part3 to an IIO target", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x08", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x4", + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x4", + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x4", + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x4", + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", + "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the total number of requests coming f= rom a unit on this socket for exclusive ownership of a cache line without r= eceiving data (INVITOE) to the CHA.", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 1", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", + "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the total number of requests coming f= rom a remote socket for exclusive ownership of a cache line without receivi= ng data (INVITOE) to the CHA.", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 2", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", + "BriefDescription": "Read requests", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts read requests made into this CHA. Rea= ds include all read opcodes (including RFO: the Read for Ownership issued b= efore a write) .", + "UMask": "0x3", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 3", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", + "BriefDescription": "Read requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counts read requests coming from a unit on t= his socket made into this CHA. Reads include all read opcodes (including RF= O: the Read for Ownership issued before a write).", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-3", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x4", + "BriefDescription": "Read requests from a remote socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", - "PortMask": "0x0f", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Counts read requests coming from a remote so= cket made into the CHA. Reads include all read opcodes (including RFO: the = Read for Ownership issued before a write).", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0-3", - "Counter": "2,3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", + "BriefDescription": "Write requests", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", - "UMask": "0x0f", - "Unit": "IIO" + "PublicDescription": "Counts write requests made into the CHA, inc= luding streaming, evictions, HitM (Reads from another core to a Modified ca= cheline), etc.", + "UMask": "0xc", + "Unit": "CHA" }, { - "BriefDescription": "Total IRP occupancy of inbound read and write= requests", - "Counter": "0,1", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "BriefDescription": "Write Requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", + "PublicDescription": "Counts write requests coming from a unit on= this socket made into this CHA, including streaming, evictions, HitM (Read= s from another core to a Modified cacheline), etc.", "UMask": "0x4", - "Unit": "IRP" + "Unit": "CHA" }, { - "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", + "BriefDescription": "Read and Write Requests; Writes Remote", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests mad= e into the Home Agent. Reads include all read opcodes (including RFO). Wri= tes include all writes (streaming, evictions, HitM, etc).", "UMask": "0x8", - "Unit": "IRP" + "Unit": "CHA" }, { - "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue", - "Counter": "0,1", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Occupancy of the IRP FAF queue", - "Counter": "0,1", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Inbound write (fast path) requests received b= y the IRP", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (= UPI)", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_UPI_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "Data Response packets that go direct to core"= , - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_DIRECT_ATTEMPTS.D2U", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x2", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdow= n)", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p powe= r mode", - "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", - "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", - "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", - "Counter": "0,1,2,3", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.ALL_NULL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NULL", + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Cycles in which the Tx of the Intel Ultra Pat= h Interconnect (UPI) is in L0p power mode", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", "PerPkg": "1", - "Unit": "UPI LL" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "FLITs that bypassed the TxL Buffer", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_UPI_TxL_BYPASSED", + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", "PerPkg": "1", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Valid Flits Sent; Data", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.DATA", + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.ALL_NULL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NULL", + "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Protocol header and credit FLITs received fro= m any slot", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", "PerPkg": "1", - "UMask": "0x97", - "Unit": "UPI LL" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Protocol header and credit FLITs transmitted = across any slot", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_CHA_RING_SRC_THRTL", "PerPkg": "1", - "UMask": "0x97", - "Unit": "UPI LL" + "Unit": "CHA" }, { - "BriefDescription": "Idle FLITs transmitted", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "BriefDescription": "Ingress (from CMS) Allocations; IPQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", "PerPkg": "1", - "UMask": "0x47", - "Unit": "UPI LL" + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Null FLITs transmitted from any slot", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", "PerPkg": "1", - "UMask": "0x27", - "Unit": "UPI LL" + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Null FLITs received from any slot", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected"= , + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", "PerPkg": "1", - "UMask": "0x27", - "Unit": "UPI LL" + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Valid data FLITs received from any slot", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", "PerPkg": "1", - "UMask": "0x0F", - "Unit": "UPI LL" + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Valid data FLITs transmitted via any slot", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", "PerPkg": "1", - "UMask": "0x0F", - "Unit": "UPI LL" + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "UPI interconnect send bandwidth for payload. = Derived from unc_upi_txl_flits.all_data", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UPI_DATA_BANDWIDTH_TX", + "BriefDescription": "Ingress (from CMS) Allocations; RRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", "PerPkg": "1", - "ScaleUnit": "7.11E-06Bytes", - "UMask": "0xf", - "Unit": "UPI LL" + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Data Response packets that go direct to Intel= UPI", - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", + "BriefDescription": "Ingress (from CMS) Allocations; WBQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" + "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Traffic in which the M2M to iMC Bypass was no= t taken", - "Counter": "0,1,2,3", + "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", "UMask": "0x2", - "Unit": "M2M" + "Unit": "CHA" }, { - "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Reque= st", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Messages sent direct to core (bypassing the C= HA)", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", + "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Number of reads in which direct to core trans= action were overridden", - "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Reque= st", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Ingress Probe Queue Rejects; ANY0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", "PerPkg": "1", "UMask": "0x1", - "Unit": "M2M" + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory update from = I to S", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "BriefDescription": "Ingress Probe Queue Rejects; HA", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", "PerPkg": "1", "UMask": "0x2", - "Unit": "M2M" + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory update from = I to A", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "BriefDescription": "Ingress Probe Queue Rejects; Merging these tw= o together to make room for ANY_REJECT_*0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory update from = S to I", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory update from = S to A", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory update from = A to I", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Multi-socket cacheline Directory update from = A to S", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "BriefDescription": "Ingress Probe Queue Rejects; Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Reads to iMC issued at Normal Priority (Non-I= sochronous)", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", "UMask": "0x1", - "Unit": "M2M" + "Unit": "CHA" }, { - "BriefDescription": "Reads to iMC issued", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Partial Non-Isochronous writes to the iMC", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Writes to iMC issued", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", "UMask": "0x10", - "Unit": "M2M" + "Unit": "CHA" }, { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Prefetch requests that got turn into a demand= request", - "Counter": "0,1,2,3", - "EventCode": "0x56", - "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Inserts into the Memory Controller Prefetch Q= ueue", - "Counter": "0,1,2,3", - "EventCode": "0x57", - "EventName": "UNC_M2M_PREFCAM_INSERTS", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "AD Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "EventCode": "0x1", - "EventName": "UNC_M2M_RxC_AD_INSERTS", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_M2M_RxC_BL_INSERTS", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x6", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA"= , + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "AD Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x9", - "EventName": "UNC_M2M_TxC_AD_INSERTS", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Mer= ging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0xA", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "BL Egress (to CMS) Allocations; All", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "UMask": "0x03", - "Unit": "M2M" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "BL Egress (to CMS) Occupancy; All", - "Counter": "0,1,2,3", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", "PerPkg": "1", - "UMask": "0x03", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Number of reads in which direct to Intel UPI = transactions were overridden", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Cycles when direct to Intel UPI was disabled"= , - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "BriefDescription": "ISMQ Rejects; AD REQ on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Messages sent direct to the Intel UPI", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "BriefDescription": "ISMQ Rejects; AD RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Number of reads that a message sent direct2 I= ntel UPI was overridden", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "BriefDescription": "ISMQ Rejects; Non UPI AK Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Prefetches generated by the flow control queu= e of the M3UPI unit", - "Counter": "0,1,2", - "EventCode": "0x29", - "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "BriefDescription": "ISMQ Rejects; BL NCB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", - "Unit": "M3UPI" + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Bypass; Taken", - "Counter": "0,1,2,3", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "BriefDescription": "ISMQ Rejects; BL NCS on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken"= , - "Counter": "0,1,2,3", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "BriefDescription": "ISMQ Rejects; BL RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Bypass; Not Taken", - "Counter": "0,1,2,3", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "BriefDescription": "ISMQ Rejects; BL WB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Single External Sno= ops", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "BriefDescription": "ISMQ Rejects; Non UPI IV Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Single Core Request= s", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "BriefDescription": "ISMQ Retries; AD REQ on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x41", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Single Eviction", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "BriefDescription": "ISMQ Retries; AD RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x81", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "BriefDescription": "ISMQ Retries; Non UPI AK Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", "PerPkg": "1", - "UMask": "0xE1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Multiple External S= noops", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "BriefDescription": "ISMQ Retries; BL NCB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", "PerPkg": "1", - "UMask": "0x22", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Mult= iple Snoops", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "BriefDescription": "ISMQ Retries; BL NCS on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0xE2", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; External Snoop to R= emote Node", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", + "BriefDescription": "ISMQ Retries; BL RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x24", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Core Request to Rem= ote Node", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", - "PerPkg": "1", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote = Node", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", + "BriefDescription": "ISMQ Retries; BL WB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x84", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote= Node", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", + "BriefDescription": "ISMQ Retries; Non UPI IV Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", "PerPkg": "1", - "UMask": "0xE4", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Counter 0 Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x1F", - "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "BriefDescription": "ISMQ Rejects; ANY0", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared = hit and op is RdInvOwn, RdInv, Inv*", - "Counter": "0,1,2,3", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "BriefDescription": "ISMQ Rejects; HA", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE", - "Counter": "0,1,2,3", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "BriefDescription": "ISMQ Retries; ANY0", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "Counter": "0,1,2,3", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "BriefDescription": "ISMQ Retries; HA", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", - "Counter": "0,1,2,3", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "Counter": "0,1,2,3", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LL= C HitS/F and op is RdInvOwn", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF= /LLC HitS/F and op is RdInvOwn", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of Misses in HitMe Cache; op is= RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "BriefDescription": "Other Retries; AD REQ on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a local request", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "BriefDescription": "Other Retries; AD RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a remote request", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "BriefDescription": "Other Retries; Non UPI AK Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache to SHARed", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "BriefDescription": "Other Retries; BL NCB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "BriefDescription": "Other Retries; BL NCS on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Deallocate HtiME$ on Reads without RspFwdI*", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "BriefDescription": "Other Retries; BL RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "HA to iMC Reads Issued; ISOCH", - "Counter": "0,1,2,3", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "BriefDescription": "Other Retries; BL WB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Writes Issued to the iMC by the HA; Partial N= on-ISOCH", - "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "BriefDescription": "Other Retries; Non UPI IV Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Ful= l Line", - "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "BriefDescription": "Other Retries; Allow Snoop", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Par= tial", - "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "BriefDescription": "Other Retries; ANY0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Writes Issued to the iMC by the HA; Full Line= MIG", - "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "BriefDescription": "Other Retries; HA", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Writes Issued to the iMC by the HA; Partial M= IG", - "Counter": "0,1,2,3", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "BriefDescription": "Other Retries; Merging these two together to = make room for ANY_REJECT_*0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations", - "Counter": "0,1,2,3", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", + "BriefDescription": "Other Retries; LLC Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations dropped due to IODC Full", - "Counter": "0,1,2,3", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", + "BriefDescription": "Other Retries; PhyAddr Match", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IDOC allocation dropped due to OSB gate", - "Counter": "0,1,2,3", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", + "BriefDescription": "Other Retries; SF Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoE", - "Counter": "0,1,2,3", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", + "BriefDescription": "Other Retries; Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoI", - "Counter": "0,1,2,3", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbPushMtoI", - "Counter": "0,1,2,3", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to conflicting transaction", - "Counter": "0,1,2,3", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to any reason", - "Counter": "0,1,2,3", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.ALL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.WRITE", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0x5", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.ANY", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.ANY", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.LOCAL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x31", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.REMOTE", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x91", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.LOCAL_ALL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x2f", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.REMOTE", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc; Silent Snoop Eviction", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA"= , + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc; Write Combining Aliasing", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.WC_ALIASING", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= OR SF Way", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "OSB Snoop Broadcast", - "Counter": "0,1,2,3", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", "PerPkg": "1", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", - "Counter": "0,1,2,3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", - "Counter": "0,1,2,3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "BriefDescription": "Request Queue Retries; AD REQ on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", - "Counter": "0,1,2,3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "BriefDescription": "Request Queue Retries; AD RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", - "Counter": "0,1,2,3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "BriefDescription": "Request Queue Retries; Non UPI AK Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", - "Counter": "0,1,2,3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "BriefDescription": "Request Queue Retries; BL NCB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", - "Counter": "0,1,2,3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "BriefDescription": "Request Queue Retries; BL NCS on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "write requests from remote home agent", - "Counter": "0,1,2,3", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "BriefDescription": "Request Queue Retries; BL RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.ALL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.", + "BriefDescription": "Request Queue Retries; BL WB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Local Requests", - "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "BriefDescription": "Request Queue Retries; Non UPI IV Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Remote Requests", - "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "BriefDescription": "Request Queue Retries; Allow Snoop", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "BriefDescription": "Request Queue Retries; ANY0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_REMOTE", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "BriefDescription": "Request Queue Retries; HA", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Merging these two toge= ther to make room for ANY_REJECT_*0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "BriefDescription": "Request Queue Retries; LLC Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "BriefDescription": "Request Queue Retries; PhyAddr Match", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received : RspS", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "BriefDescription": "Request Queue Retries; SF Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_WBWB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "BriefDescription": "Request Queue Retries; Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received; RspFwd", - "Counter": "0,1,2,3", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "BriefDescription": "RRQ Rejects; AD REQ on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPI", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "BriefDescription": "RRQ Rejects; AD RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "BriefDescription": "RRQ Rejects; Non UPI AK Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "BriefDescription": "RRQ Rejects; BL NCB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "BriefDescription": "RRQ Rejects; BL NCS on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "BriefDescription": "RRQ Rejects; BL RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "BriefDescription": "RRQ Rejects; BL WB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "BriefDescription": "RRQ Rejects; Non UPI IV Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "BriefDescription": "RRQ Rejects; Allow Snoop", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.EVICT", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.EVICT", + "BriefDescription": "RRQ Rejects; ANY0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.PRQ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ", + "BriefDescription": "RRQ Rejects; HA", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IPQ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ", + "BriefDescription": "RRQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.HIT", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.HIT", + "BriefDescription": "RRQ Rejects; LLC Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.MISS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS", + "BriefDescription": "RRQ Rejects; PhyAddr Match", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.EVICT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", + "BriefDescription": "RRQ Rejects; SF Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.PRQ", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", + "BriefDescription": "RRQ Rejects; Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IPQ", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", + "BriefDescription": "WBQ Rejects; AD REQ on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.HIT", + "BriefDescription": "WBQ Rejects; AD RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.MISS", + "BriefDescription": "WBQ Rejects; Non UPI AK Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "WbPushMtoI; Pushed to LLC", - "Counter": "0,1,2,3", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "BriefDescription": "WBQ Rejects; BL NCB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "WbPushMtoI; Pushed to Memory", - "Counter": "0,1,2,3", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "BriefDescription": "WBQ Rejects; BL NCS on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", - "Counter": "0,1,2,3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "BriefDescription": "WBQ Rejects; BL RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", - "Counter": "0,1,2,3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "BriefDescription": "WBQ Rejects; BL WB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", - "Counter": "0,1,2,3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "BriefDescription": "WBQ Rejects; Non UPI IV Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", - "Counter": "0,1,2,3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "BriefDescription": "WBQ Rejects; Allow Snoop", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", - "Counter": "0,1,2,3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "BriefDescription": "WBQ Rejects; ANY0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", - "Counter": "0,1,2,3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "BriefDescription": "WBQ Rejects; HA", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_IO", + "BriefDescription": "WBQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", "PerPkg": "1", - "UMask": "0x34", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_IA", + "BriefDescription": "WBQ Rejects; LLC Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x31", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "BriefDescription": "WBQ Rejects; PhyAddr Match", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", "PerPkg": "1", - "UMask": "0x37", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", + "BriefDescription": "WBQ Rejects; SF Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", "PerPkg": "1", - "UMask": "0x34", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", + "BriefDescription": "WBQ Rejects; Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", "PerPkg": "1", - "UMask": "0x31", + "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", + "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x37", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core PMA Events; C1 State", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C1_STATE", + "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Core PMA Events; C1 Transition", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", + "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Core PMA Events; C6 State", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C6_STATE", + "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Core PMA Events; C6 Transition", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core PMA Events; GV", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.GV", + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Transgress Injection Starvation; AK - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Transgress Injection Starvation; IV - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking exclusive lines in the cores cache. Snoop filter capacity e= victions occur when the snoop filter is full and evicts an existing entry t= o track a new entry. Does not count clean evictions such as when a cores ca= che replaces a tracked cacheline with a new cacheline.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking modified lines in the cores cache. Snoop filter capacity ev= ictions occur when the snoop filter is full and evicts an existing entry to= track a new entry. Does not count clean evictions such as when a cores cac= he replaces a tracked cacheline with a new cacheline.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking shared lines in the cores cache. Snoop filter capacity evic= tions occur when the snoop filter is full and evicts an existing entry to t= rack a new entry. Does not count clean evictions such as when a cores cache= replaces a tracked cacheline with a new cacheline.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "BriefDescription": "Snoops Sent; All", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of snoops issued by the HA= .", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "BriefDescription": "Snoops Sent; Broadcast snoop for Local Reques= ts", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast snoops issued by the HA. This filter incl= udes only requests coming from local sockets.", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requ= ests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast snoops issued by the HA.This filter inclu= des only requests coming from remote sockets.", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Snoops Sent; Directed snoops for Local Reques= ts", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of directed snoops issued by the HA. This filter inclu= des only requests coming from local sockets.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Snoops Sent; Directed snoops for Remote Reque= sts", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of directed snoops issued by the HA. This filter inclu= des only requests coming from remote sockets.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast or directed snoops issued by the HA per r= equest. This filter includes only requests coming from the local socket.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast or directed snoops issued by the HA per r= equest. This filter includes only requests coming from the remote socket.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "BriefDescription": "RspCnflct* Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts when a a transaction with the opcode = type RspCnflct* Snoop Response was received. This is returned when a snoop = finds an existing outstanding transaction in a remote caching agent. This t= riggers conflict resolution hardware. This covers both the opcode RspCnflct= and RspCnflctWbI.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Snoop Responses Received; RspFwd", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspFwd to a CA request. This snoop response = is only possible for RdCur when a snoop HITM/E in a remote caching agent an= d it directly forwards data to a requestor without changing the requestor's= cache line state.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "BriefDescription": "RspI Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode ty= pe RspI Snoop Response was received which indicates the remote cache does n= ot have the data, or when the remote cache silently evicts data (such as wh= en an RFO: the Read for Ownership issued before a write hits non-modified d= ata).", "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "BriefDescription": "RspIFwd Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Counts when a a transaction with the opcode = type RspIFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data and the requesting agent is able to acquire the dat= a in E (Exclusive) or M (modified) states. This is commonly returned with = RFO (the Read for Ownership issued before a write) transactions. The snoop= could have either been to a cacheline in the M,E,F (Modified, Exclusive or= Forward) states.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Snoop Responses Received : RspS", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Snoop Responses Received : RspS : Counts the= total number of RspI snoop responses received. Whenever a snoops are issu= ed, one or more snoop responses will be returned depending on the topology = of the system. In systems larger than 2s, when multiple snoops are return= ed this will count all the snoops that are received. For example, if 3 sno= ops were issued and returned RspI, RspS, and RspSFwd; then each of these su= b-events would increment by 1. : Filters for snoop responses of RspS. RspS= is returned when a remote cache has data but is not forwarding it. It is = a way to let the requesting socket know that it cannot allocate the data in= E state. No data is sent with S RspS.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "BriefDescription": "RspSFwd Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode = type RspSFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data but held on to its current copy. This is common fo= r data and code reads that hit in a remote socket in E (Exclusive) or F (Fo= rward) state.", "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts when a transaction with the opcode ty= pe Rsp*Fwd*WB Snoop Response was received which indicates the data was writ= ten back to its home socket, and the cacheline was forwarded to the request= or socket. This snoop response is only used in >=3D 4 socket systems. = It is used when a snoop HITM's in a remote caching agent and it directly fo= rwards data to a requestor, and simultaneously returns data to its home soc= ket to be written back to memory.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Rsp*WB Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts when a transaction with the opcode ty= pe Rsp*WB Snoop Response was received which indicates which indicates the d= ata was written back to its home. This is returned when a non-RFO request = hits a cacheline in the Modified state. The Cache can either downgrade the = cacheline to a S (Shared) or I (Invalid) state depending on how the system = has been configured. This response will also be sent when a cache requests= E (Exclusive) ownership of a cache line without receiving data, because th= e cache must acquire ownership.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspConflict to local CA reques= ts. This is returned when a snoop finds an existing outstanding transactio= n in a remote caching agent when it CAMs that caching agent. This triggers= conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI= .", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "BriefDescription": "Snoop Responses Received Local; RspFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspFwd to local CA requests. = This snoop response is only possible for RdCur when a snoop HITM/E in a rem= ote caching agent and it directly forwards data to a requestor without chan= ging the requestor's cache line state.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "BriefDescription": "Snoop Responses Received Local; RspI", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspI to local CA requests. Rs= pI is returned when the remote cache does not have the data, or when the re= mote cache silently evicts data (such as when an RFO hits non-modified data= ).", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspIFwd to local CA requests. = This is returned when a remote caching agent forwards data and the requesti= ng agent is able to acquire the data in E or M states. This is commonly re= turned with RFO transactions. It can be either a HitM or a HitFE.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "BriefDescription": "Snoop Responses Received Local; RspS", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspS to local CA requests. Rsp= S is returned when a remote cache has data but is not forwarding it. It is= a way to let the requesting socket know that it cannot allocate the data i= n E state. No data is sent with S RspS.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd to local CA requests. = This is returned when a remote caching agent forwards data but holds on to= its current copy. This is common for data and code reads that hit in a re= mote socket in E or F state.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CMS_CLOCKTICKS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_H_CLOCK", + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of Rsp*Fwd*WB to local CA request= s. This snoop response is only used in 4s systems. It is used when a snoo= p HITM's in a remote caching agent and it directly forwards data to a reque= stor, and simultaneously returns data to the home to be written back to mem= ory.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", - "Counter": "0,1,2,3", - "EventCode": "0xAE", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspIWB or RspSWB to local CA r= equests. This is returned when a non-RFO request hits in M state. Data an= d Code Reads can return either RspIWB or RspSWB depending on how the system= has been configured. InvItoE transactions will also return RspIWB because= they must acquire ownership.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", - "Counter": "0,1,2,3", - "EventCode": "0xAE", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "Counter": "0,1,2,3", - "EventCode": "0xAD", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "Counter": "0,1,2,3", - "EventCode": "0xAD", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "BriefDescription": "TOR Inserts; Hits from Local", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x15", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "BriefDescription": "TOR Inserts; All from Local iA and IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; A= ll locally initiated requests", + "UMask": "0x35", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "BriefDescription": "TOR Inserts; Misses from Local", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x25", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "BriefDescription": "TOR Inserts; SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; T= OR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)= ", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "BriefDescription": "TOR Inserts; Hit (Not a Miss)", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; H= ITs (hit is defined to be not a miss [see below], as a result for any reque= st allocated into the TOR, one of either HIT or MISS must be true)", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "BriefDescription": "TOR Inserts; All from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; A= ll locally initiated requests from iA Cores", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "BriefDescription": "TOR Inserts; Hits from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "Filter": "config1=3D0x40233", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SRC_THRTL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0xA4", - "EventName": "UNC_C_RING_SRC_THRTL", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hi= t the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "Filter": "config1=3D0x40433", "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected"= , - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Filter": "config1=3D0x4b233", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; IPQ", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Filter": "config1=3D0x4b433", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; PRQ", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", + "Filter": "config1=3D0x4b033", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that hit the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; PRQ", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "Filter": "config1=3D0x40033", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; RRQ", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations; WBQ", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Filter": "config1=3D0x40233", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Filter": "config1=3D0x40433", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Filter": "config1=3D0x4b233", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Filter": "config1=3D0x4b433", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", + "Filter": "config1=3D0x4b033", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that missed the LLC : Counts the number of entries successfully inserted in= to the TOR that match qualifications specified by the subevent. Does not = include addressless requests such as locks and interrupts.", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "Filter": "config1=3D0x40033", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "TOR Inserts; All from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; A= ll locally generated IO traffic", + "UMask": "0x34", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.ANY0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "BriefDescription": "TOR Inserts; Hits from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x14", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; HA", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "BriefDescription": "TOR Inserts; Misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "BriefDescription": "TOR Inserts; ItoM misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Filter": "config1=3D0x49033", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO ItoM requests that mis= s the LLC. An ItoM request is used by IIO to request a data write without f= irst reading the data for ownership.", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "BriefDescription": "TOR Inserts; RdCur misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", + "Filter": "config1=3D0x43C33", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO RdCur requests and mis= s the LLC. A RdCur request is used by IIO to read data without changing sta= te.", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; Victim", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "BriefDescription": "TOR Inserts; RFO misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Filter": "config1=3D0x40033", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO RFO requests that miss= the LLC. A read for ownership (RFO) requests a cache line to be cached in = E state with the intent to modify.", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; Merging these tw= o together to make room for ANY_REJECT_*0", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "BriefDescription": "TOR Inserts; IPQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x18", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x28", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "TOR Inserts; IRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x37", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "TOR Inserts; Miss", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; M= isses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IP= Q or (in the victim case) the ISMQ, that required the CHA to spawn a new UP= I/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to = a local memory controller, in the event that the CHA is the home node)). B= asically, if the LLC/SF/MLC complex were not able to service the request wi= thout involving another agent...it is a miss. If only IDI snoops were requ= ired, it is not a miss (that means the SF/MLC com", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "BriefDescription": "TOR Inserts; PRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x30", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.ANY0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x50", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA"= , - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x60", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x90", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0xa0", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "BriefDescription": "TOR Occupancy; All from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely= generated requests", + "UMask": "0x37", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Mer= ging these two together to make room for ANY_REJECT_*0", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "BriefDescription": "TOR Occupancy; Hits from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x17", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "BriefDescription": "TOR Occupancy; Misses from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x27", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; AD REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "TOR Occupancy; SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; TOR allocation occurred as a result of SF/LLC evictions (c= ame from the ISMQ)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; AD RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; HITs (hit is defined to be not a miss [see below], as a re= sult for any request allocated into the TOR, one of either HIT or MISS must= be true)", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; BL RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "TOR Occupancy; All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; All locally initiated requests from iA Cores", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; BL WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "BriefDescription": "TOR Occupancy; Hits from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; BL NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Filter": "config1=3D0x40233", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; BL NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Filter": "config1=3D0x40433", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; AD REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Filter": "config1=3D0x4b233", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; AD RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Filter": "config1=3D0x4b433", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; BL RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "Filter": "config1=3D0x4b033", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; BL WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Filter": "config1=3D0x40033", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; BL NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "BriefDescription": "TOR Occupancy; Misses from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; BL NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "Filter": "config1=3D0x40233", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_REJECT.ANY0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x25", - "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Filter": "config1=3D0x40433", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; HA", - "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Filter": "config1=3D0x4b233", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_RETRY.ANY0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x2D", - "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Filter": "config1=3D0x4b433", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; HA", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "Filter": "config1=3D0x4b033", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "Filter": "config1=3D0x40033", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "BriefDescription": "TOR Occupancy; All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; All locally generated IO traffic", + "UMask": "0x34", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "BriefDescription": "TOR Occupancy; Hits from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x14", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; AD REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "BriefDescription": "TOR Occupancy; Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; AD RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Filter": "config1=3D0x49033", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO ItoM req= uests that miss the LLC. An ItoM is used by IIO to request a data write wit= hout first reading the data for ownership.", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; BL RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", + "Filter": "config1=3D0x43C33", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO RdCur re= quests that miss the LLC. A RdCur request is used by IIO to read data witho= ut changing state.", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; BL WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "BriefDescription": "TOR Occupancy; RFO misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Filter": "config1=3D0x40033", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO RFO requ= ests that miss the LLC. A read for ownership (RFO) requests data to be cach= ed in E state with the intent to modify.", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; BL NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "BriefDescription": "TOR Occupancy; IPQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; BL NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x18", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.ANY0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x28", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; HA", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "BriefDescription": "TOR Occupancy; IRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; LLC Victim", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x37", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; SF Victim", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "BriefDescription": "TOR Occupancy; Miss", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; Misses. (a miss is defined to be any transaction from the= IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA= to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops an= d/or any RD/WR to a local memory controller, in the event that the CHA is t= he home node)). Basically, if the LLC/SF/MLC complex were not able to serv= ice the request without involving another agent...it is a miss. If only ID= I snoops were required, it is not a miss (that means the SF/MLC com", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; Victim", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "BriefDescription": "TOR Occupancy; PRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; Merging these two together to = make room for ANY_REJECT_*0", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; Allow Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; PhyAddr Match", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.ANY0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA"= , - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= OR SF Way", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; AD REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; AD RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; BL RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; BL WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; BL NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; BL NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; HA", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; LLC Victim", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; SF Victim", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; Victim", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; Merging these two toge= ther to make room for ANY_REJECT_*0", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; Allow Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; PhyAddr Match", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; AD REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; AD RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; BL RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; BL WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; BL NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; BL NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit"= , + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.ANY0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; HA", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; LLC Victim", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit"= , + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; SF Victim", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; Victim", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; Allow Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; PhyAddr Match", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; AD REQ on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; AD RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; BL RSP on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; BL WB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; BL NCB on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; BL NCS on VN0", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.ANY0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; HA", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; LLC Victim", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; SF Victim", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; Victim", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; Allow Snoop", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; PhyAddr Match", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV"= , + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.IV", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV"= , + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credit= s", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Cr= edits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credit= s", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credit= s", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credit= s", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credit= s", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time."= , + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0= Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0= Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0= Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0= Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0= Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0= Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Cre= dits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Cre= dits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "BriefDescription": "WbPushMtoI; Pushed to LLC", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of times when the CHA was = received WbPushMtoI; Counts the number of times when the CHA was able to pu= sh WbPushMToI to LLC", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "BriefDescription": "WbPushMtoI; Pushed to Memory", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of times when the CHA was = received WbPushMtoI; Counts the number of times when the CHA was unable to = push WbPushMToI to LLC (hence pushed it to MEM)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 2 only.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 3 only.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 4 only.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 5 only.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 0 only.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 1 only.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response I to Fwd F/E", + "UMask": "0xe4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "BriefDescription": "Core Cross Snoop Responses", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response I to Fwd M", + "UMask": "0xf0", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response S to Fwd F/E", + "UMask": "0xe2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response S to Fwd M", + "UMask": "0xe8", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response any to Hit F/S/E= ", + "UMask": "0xe1", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response I to Fwd F/E", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response I to Fwd M", + "UMask": "0x50", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response S to Fwd F/E", + "UMask": "0x42", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response S to Fwd M", + "UMask": "0x48", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response any to Hit F/S/= E", + "UMask": "0x41", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response I to Fwd F/= E", + "UMask": "0x84", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response I to Fwd M"= , + "UMask": "0x90", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response S to Fwd F/= E", + "UMask": "0x82", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response S to Fwd M"= , + "UMask": "0x88", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response any to Hit = F/S/E", + "UMask": "0x81", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdF= E", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response I to Fwd F/= E", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM= ", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response I to Fwd M"= , + "UMask": "0x30", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdF= E", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response S to Fwd F/= E", + "UMask": "0x22", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM= ", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response S to Fwd M"= , + "UMask": "0x28", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "BriefDescription": "Core Cross Snoop Responses; External RspHitFS= E", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response any to Hit = F/S/E", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CLOCKTICKS", + "Deprecated": "1", + "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x02", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_FAST_ASSERTED.HORZ", + "Deprecated": "1", + "EventCode": "0xA5", + "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.ANY", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.ANY", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x3", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.LOCAL", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x91", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x9", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.WRITE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x5", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.IV", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x2f", + "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.REMOTE", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SRC_THRTL", + "Deprecated": "1", + "EventCode": "0xA4", + "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "UMask": "0x04", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.IV", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.EVICT", "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICT", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.HIT", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IPQ", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x18", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x28", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.IV", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS", "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x37", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IA", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IO", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x34", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.MISS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.PRQ", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x14", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.IV", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_MISS", "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REM_ALL", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x30", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x50", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x60", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x90", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0xa0", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.EVICT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.IV", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.HIT", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x18", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x28", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.IV", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0x37", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x31", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x34", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.PRQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x14", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV"= , - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Vertical IV Ring in Use; Up", - "Counter": "0,1,2,3", - "EventCode": "0xAC", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Vertical IV Ring in Use; Down", - "Counter": "0,1,2,3", - "EventCode": "0xAC", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; External RspHitFS= E", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x21", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x41", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x81", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0xE1", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; External RspSFwdF= E", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x22", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x42", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x82", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0xE2", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; External RspIFwdF= E", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x24", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x44", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x84", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0xE4", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM= ", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x28", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x48", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x88", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0xE8", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM= ", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x30", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x50", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x90", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoop Responses", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0xF0", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x18", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x28", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x50", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x60", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x90", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0xA0", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x24", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x18", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x28", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; All from Local IO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE", "PerPkg": "1", - "UMask": "0x34", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; All from Local iA and IO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN", "PerPkg": "1", - "UMask": "0x35", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; Hits from Local", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN", "PerPkg": "1", - "UMask": "0x15", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; Misses from Local", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CMS_CLOCKTICKS", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_H_CLOCK", "PerPkg": "1", - "UMask": "0x25", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; All from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C1_STATE", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C1_STATE", "PerPkg": "1", - "UMask": "0x34", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Hits from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C1_TRANSITION", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C1_TRANSITION", "PerPkg": "1", - "UMask": "0x14", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C6_STATE", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C6_STATE", "PerPkg": "1", - "UMask": "0x24", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Hits from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C6_TRANSITION", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C6_TRANSITION", "PerPkg": "1", - "UMask": "0x17", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Misses from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.GV", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.GV", "PerPkg": "1", - "UMask": "0x27", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_GTONE", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0xe2", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_ONE", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0xe1", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credit= s", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_REMOTE", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0xe4", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Cr= edits", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_GTONE", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x42", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credit= s", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_ONE", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x41", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credit= s", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_REMOTE", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credit= s", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x82", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credit= s", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_ONE", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x81", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Cre= dits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x84", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Cre= dits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_GTONE", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x22", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0= Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_ONE", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0= Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_REMOTE", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x24", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0= Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_COUNTER0_OCCUPANCY", + "Deprecated": "1", + "EventCode": "0x1F", + "EventName": "UNC_H_COUNTER0_OCCUPANCY", "PerPkg": "1", - "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0= Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", - "PerPkg": "1", - "UMask": "0x20", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.NO_SNP", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0= Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.SNP", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.SNP", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Reque= st", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.HA", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.HA", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Reque= st", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.TOR", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.TOR", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Deprecated": "1", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Deprecated": "1", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; Non UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.EX_RDS", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.EX_RDS", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; Non UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; Non UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.WBMTOE", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.WBMTOE", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; Non UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; Non UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_LOOKUP.READ", + "Deprecated": "1", + "EventCode": "0x5E", + "EventName": "UNC_H_HITME_LOOKUP.READ", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; Non UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_LOOKUP.WRITE", + "Deprecated": "1", + "EventCode": "0x5E", + "EventName": "UNC_H_HITME_LOOKUP.WRITE", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.READ_OR_INV", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.READ_OR_INV", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; Non UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; Non UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; Non UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; Non UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.RDINVOWN", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.RDINVOWN", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; Non UPI AK Request", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; Non UPI IV Request", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.SHARED", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.SHARED", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries; ANY0", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent; All", - "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent; Broadcast snoop for Local Reques= ts", - "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requ= ests", - "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent; Directed snoops for Local Reques= ts", - "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent; Directed snoops for Remote Reque= sts", - "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; RspI", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; RspS", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; RspIFwd", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; RspSFwd", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; Rsp*WB", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; RspCnflct", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Deprecated": "1", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local; RspFwd", - "Counter": "0,1,2,3", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Deprecated": "1", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Clockticks", - "Counter": "0,1,2,3", - "EventCode": "0xC0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_READS_COUNT.NORMAL", + "Deprecated": "1", + "EventCode": "0x59", + "EventName": "UNC_H_IMC_READS_COUNT.NORMAL", "PerPkg": "1", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", - "Counter": "0,1,2,3", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Deprecated": "1", + "EventCode": "0x59", + "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY", "PerPkg": "1", - "UMask": "0x03", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; Write Request= s", - "Counter": "0,1,2,3", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL", "PerPkg": "1", - "UMask": "0x05", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; External Snoo= p Request", - "Counter": "0,1,2,3", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG", "PerPkg": "1", - "UMask": "0x09", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", - "Counter": "0,1,2,3", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ANY", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; Local", - "Counter": "0,1,2,3", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL", "PerPkg": "1", - "UMask": "0x31", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; Remote", - "Counter": "0,1,2,3", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG", "PerPkg": "1", - "UMask": "0x91", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.INVITOM", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.INVITOM", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.IODCFULL", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.IODCFULL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.OSBGATED", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.OSBGATED", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized; Local - All Lines", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.ALL", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.ALL", "PerPkg": "1", - "UMask": "0x2F", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.SNPOUT", "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.SNPOUT", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; IRQ", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBMTOE", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBMTOE", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; SF/LLC Evictions", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBMTOI", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBMTOI", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; PRQ", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; IPQ", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.CV0_PREF_MISS", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_MISS", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; Hit (Not a Miss)", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.CV0_PREF_VIC", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_VIC", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; Miss", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RFO_HIT_S", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RSPI_WAS_FSE", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RSPI_WAS_FSE", "PerPkg": "1", - "UMask": "0x37", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.WC_ALIASING", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.WC_ALIASING", "PerPkg": "1", - "UMask": "0x18", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_OSB", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", + "EventCode": "0x55", + "EventName": "UNC_H_OSB", "PerPkg": "1", - "UMask": "0x28", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2", "PerPkg": "1", - "UMask": "0x50", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3", "PerPkg": "1", - "UMask": "0x60", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4", "PerPkg": "1", - "UMask": "0x90", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5", "PerPkg": "1", - "UMask": "0xA0", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; IRQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; SF/LLC Evictions", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; PRQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_LOCAL", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; IPQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_REMOTE", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "BriefDescription": "read requests from home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x3", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; Miss", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "BriefDescription": "read requests from local home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "BriefDescription": "read requests from remote home agent", "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_REMOTE", "PerPkg": "1", - "UMask": "0x37", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", + "BriefDescription": "write requests from home agent", "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", - "UMask": "0x18", + "UMask": "0xc", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. ", + "BriefDescription": "write requests from local home agent", "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", - "UMask": "0x28", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Source Throttle", - "Counter": "0,1,2,3", - "EventCode": "0xA4", - "EventName": "UNC_CHA_RING_SRC_THRTL", + "BriefDescription": "write requests from remote home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", "PerPkg": "1", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Ingress Probe Queue Rejects; ANY0", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.AD", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.AK", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects; ANY0", - "Counter": "0,1,2,3", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.BL", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries; ANY0", - "Counter": "0,1,2,3", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.IV", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Other Retries; ANY0", - "Counter": "0,1,2,3", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.AD", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AD", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.AK", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AK", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "RRQ Rejects; ANY0", - "Counter": "0,1,2,3", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.BL", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.BL", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "WBQ Rejects; ANY0", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.IV", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.IV", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used; IV", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", - "PerPkg": "1", - "UMask": "0x08", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV"= , - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IPQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.PRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.RRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.WBQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.RRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.WBQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.IFV", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.E_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.M_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.S_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.ALL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPI", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPIFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPS", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPSFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_WBWB", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.IV", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.IV", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AD_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AD_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AK_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AK_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.BL_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.BL_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.IV", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.IV", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Deprecated": "1", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Deprecated": "1", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WB_PUSH_MTOI.LLC", + "Deprecated": "1", + "EventCode": "0x56", + "EventName": "UNC_H_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WB_PUSH_MTOI.MEM", + "Deprecated": "1", + "EventCode": "0x56", + "EventName": "UNC_H_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0xf0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0xe8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x48", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Clockticks of the IIO Traffic Controller", + "EventCode": "0x1", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts clockticks of the 1GHz trafiic contro= ller clock in the IIO unit.", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0-3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 1", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 2", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x16 card plugged in to stac= k, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x8 card plugged in to Lane = 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x16 card plugged in to stac= k, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x8 card plugged in to Lane = 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x16 card plugged in to stac= k, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x8 card plugged in to Lane = 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x16 card plugged in to stac= k, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x8 card plugged in to Lane = 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; x4 card is plugged in to sl= ot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by a unit on the main die (generally a core) or by another IIO unit = to the MMIO space of a card on IIO Part0. In the general case, Part0 refers= to a standard PCIe card of any size (x16,x8,x4) that is plugged directly i= nto one of the PCIe slots. Part0 could also refer to any device plugged int= o the first slot of a PCIe riser card or to a device attached to the IIO un= it which starts its use of the bus using lane 0 of the 16 lanes supported b= y the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by a unit on the main die (generally a core) or by another IIO unit = to the MMIO space of a card on IIO Part1. In the general case, Part1 refers= to a x4 PCIe card plugged into the second slot of a PCIe riser card, but i= t could refer to any x4 device attached to the IIO unit using lanes startin= g at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by a unit on the main die (generally a core) or by another IIO unit = to the MMIO space of a card on IIO Part2. In the general case, Part2 refers= to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, = but it could refer to any x4 or x8 device attached to the IIO unit and usin= g lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by a unit on the main die (generally a core) or by another IIO unit = to the MMIO space of a card on IIO Part3. In the general case, Part3 refers= to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but i= t could brefer to any device attached to the IIO unit using the lanes star= ting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part0 by= the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made to the MMIO space of a card on IIO Part0 by a unit on the main die (= generally a core) or by another IIO unit. In the general case, Part0 refers= to a standard PCIe card of any size (x16,x8,x4) that is plugged directly i= nto one of the PCIe slots. Part0 could also refer to any device plugged int= o the first slot of a PCIe riser card or to a device attached to the IIO un= it which starts its use of the bus using lane 0 of the 16 lanes supported b= y the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part1 by= the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made to the MMIO space of a card on IIO Part1 by a unit on the main die (= generally a core) or by another IIO unit. In the general case, Part1 refers= to a x4 PCIe card plugged into the second slot of a PCIe riser card, but i= t could refer to any x4 device attached to the IIO unit using lanes startin= g at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part2 by= the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made to the MMIO space of a card on IIO Part2 by a unit on the main die = (generally a core) or by another IIO unit. In the general case, Part2 refer= s to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card,= but it could refer to any x4 or x8 device attached to the IIO unit and usi= ng lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part3 by= the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made to the MMIO space of a card on IIO Part3 by a unit on the main die = (generally a core) or by another IIO unit. In the general case, Part3 refer= s to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but = it could brefer to any device attached to the IIO unit using the lanes star= ting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts ever peer to peer read request for 4 = bytes of data made by a different IIO unit to the MMIO space of a card on I= IO Part0. Does not include requests made by the same IIO unit. In the gener= al case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that = is plugged directly into one of the PCIe slots. Part0 could also refer to a= ny device plugged into the first slot of a PCIe riser card or to a device a= ttached to the IIO unit which starts its use of the bus using lane 0 of the= 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts ever peer to peer read request for 4 = bytes of data made by a different IIO unit to the MMIO space of a card on I= IO Part1. Does not include requests made by the same IIO unit. In the gener= al case, Part1 refers to a x4 PCIe card plugged into the second slot of a P= CIe riser card, but it could refer to any x4 device attached to the IIO uni= t using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts ever peer to peer read request for 4 = bytes of data made by a different IIO unit to the MMIO space of a card on I= IO Part2. Does not include requests made by the same IIO unit. In the gener= al case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot o= f a PCIe riser card, but it could refer to any x4 or x8 device attached to = the IIO unit and using lanes starting at lane 8 of the 16 lanes supported b= y the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts ever peer to peer read request for 4 = bytes of data made by a different IIO unit to the MMIO space of a card on I= IO Part3. Does not include requests made by the same IIO unit. In the gener= al case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a P= CIe riser card, but it could brefer to any device attached to the IIO unit= using the lanes starting at lane 12 of the 16 lanes supported by the bus."= , + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made to the MMIO space of a card on IIO Part0 by a different= IIO unit. Does not include requests made by the same IIO unit. In the gen= eral case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) tha= t is plugged directly into one of the PCIe slots. Part0 could also refer to= any device plugged into the first slot of a PCIe riser card or to a device= attached to the IIO unit which starts its use of the bus using lane 0 of t= he 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part1 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made to the MMIO space of a card on IIO Part1 by a different= IIO unit. Does not include requests made by the same IIO unit. In the gene= ral case, Part1 refers to a x4 PCIe card plugged into the second slot of a = PCIe riser card, but it could refer to any x4 device attached to the IIO un= it using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part2 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made to the MMIO space of a card on IIO Part2 by a different= IIO unit. Does not include requests made by the same IIO unit. In the gene= ral case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot = of a PCIe riser card, but it could refer to any x4 or x8 device attached to= the IIO unit and using lanes starting at lane 8 of the 16 lanes supported = by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part3 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made to the MMIO space of a card on IIO Part3 by a different= IIO unit. Does not include requests made by the same IIO unit. In the gene= ral case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a = PCIe riser card, but it could brefer to any device attached to the IIO unit= using the lanes starting at lane 12 of the 16 lanes supported by the bus."= , + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests ini= tiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x16 card plugged in to stack, Or x8= card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x8 card plugged in to Lane 2/3, Or = x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x16 card plugged in to stack, Or x8= card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x8 card plugged in to Lane 2/3, Or = x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by IIO Part0 to a unit on the main die (generally memory). In the ge= neral case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) th= at is plugged directly into one of the PCIe slots. Part0 could also refer t= o any device plugged into the first slot of a PCIe riser card or to a devic= e attached to the IIO unit which starts its use of the bus using lane 0 of = the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 1"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by IIO Part1 to a unit on the main die (generally memory). In the ge= neral case, Part1 refers to a x4 PCIe card plugged into the second slot of = a PCIe riser card, but it could refer to any x4 device attached to the IIO = unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 2"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by IIO Part2 to a unit on the main die (generally memory). In the ge= neral case, Part2 refers to a x4 or x8 PCIe card plugged into the third slo= t of a PCIe riser card, but it could refer to any x4 or x8 device attached = to the IIO unit and using lanes starting at lane 8 of the 16 lanes supporte= d by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 3"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for 4 bytes of dat= a made by IIO Part3 to a unit on the main die (generally memory). In the ge= neral case, Part3 refers to a x4 PCIe card plugged into the fourth slot of = a PCIe riser card, but it could brefer to any device attached to the IIO u= nit using the lanes starting at lane 12 of the 16 lanes supported by the bu= s.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made by IIO Part0 to a unit on the main die (generally memory). In the ge= neral case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) th= at is plugged directly into one of the PCIe slots. Part0 could also refer t= o any device plugged into the first slot of a PCIe riser card or to a devic= e attached to the IIO unit which starts its use of the bus using lane 0 of = the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 1"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made by IIO Part1 to a unit on the main die (generally memory). In the ge= neral case, Part1 refers to a x4 PCIe card plugged into the second slot of = a PCIe riser card, but it could refer to any x4 device attached to the IIO = unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 2"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made by IIO Part2 to a unit on the main die (generally memory). In the ge= neral case, Part2 refers to a x4 or x8 PCIe card plugged into the third slo= t of a PCIe riser card, but it could refer to any x4 or x8 device attached = to the IIO unit and using lanes starting at lane 8 of the 16 lanes supporte= d by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 3"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of 4 bytes of dat= a made by IIO Part3 to a unit on the main die (generally memory). In the ge= neral case, Part3 refers to a x4 PCIe card plugged into the fourth slot of = a PCIe riser card, but it could brefer to any device attached to the IIO u= nit using the lanes starting at lane 12 of the 16 lanes supported by the bu= s.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x16 card plugged in to stack, Or x8= card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x8 card plugged in to Lane 2/3, Or = x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request for 4= bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the= general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4)= that is plugged directly into one of the PCIe slots. Part0 could also refe= r to any device plugged into the first slot of a PCIe riser card or to a de= vice attached to the IIO unit which starts its use of the bus using lane 0 = of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part1 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request for 4= bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the= general case, Part1 refers to a x4 PCIe card plugged into the second slot = of a PCIe riser card, but it could refer to any x4 device attached to the I= IO unit using lanes starting at lane 4 of the 16 lanes supported by the bus= .", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part2 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request for 4= bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the= general case, Part2 refers to a x4 or x8 PCIe card plugged into the third = slot of a PCIe riser card, but it could refer to any x4 or x8 device attach= ed to the IIO unit and using lanes starting at lane 8 of the 16 lanes suppo= rted by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part3 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request for 4= bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the= general case, Part3 refers to a x4 PCIe card plugged into the fourth slot = of a PCIe riser card, but it could brefer to any device attached to the IIO= unit using the lanes starting at lane 12 of the 16 lanes supported by the = bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the= general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4)= that is plugged directly into one of the PCIe slots. Part0 could also refe= r to any device plugged into the first slot of a PCIe riser card or to a de= vice attached to the IIO unit which starts its use of the bus using lane 0 = of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the= general case, Part1 refers to a x4 PCIe card plugged into the second slot = of a PCIe riser card, but it could refer to any x4 device attached to the I= IO unit using lanes starting at lane 4 of the 16 lanes supported by the bus= .", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the= general case, Part2 refers to a x4 or x8 PCIe card plugged into the third = slot of a PCIe riser card, but it could refer to any x4 or x8 device attach= ed to the IIO unit and using lanes starting at lane 8 of the 16 lanes suppo= rted by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of 4= bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the= general case, Part3 refers to a x4 PCIe card plugged into the fourth slot = of a PCIe riser card, but it could brefer to any device attached to the II= O unit using the lanes starting at lane 12 of the 16 lanes supported by the= bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", - "Unit": "CHA" + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", - "Unit": "CHA" + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the= attached device made of the main die.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", + "BriefDescription": "Num Link Correctable Errors", + "EventCode": "0xF", + "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", "PerPkg": "1", - "UMask": "0x08", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "BriefDescription": "Num Link Retries", + "EventCode": "0xE", + "EventName": "UNC_IIO_LINK_NUM_RETRIES", "PerPkg": "1", - "UMask": "0x08", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "FaST wire asserted; Vertical", - "Counter": "0,1,2,3", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.VERT", + "BriefDescription": "Number packets that passed the Mask/Match Fil= ter", + "EventCode": "0x21", + "EventName": "UNC_IIO_MASK_MATCH", "PerPkg": "1", - "UMask": "0x01", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" + "PublicDescription": "Asserted if all bits specified by mask match= ", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Local - Lines in M State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" + "PublicDescription": "Asserted if all bits specified by mask match= ", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Local - Lines in E State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d !(PCIE bus)", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", "PerPkg": "1", - "UMask": "0x22", - "Unit": "CHA" + "PublicDescription": "Asserted if all bits specified by mask match= ", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Local - Lines in S State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "BriefDescription": "AND Mask/match for debug bus; PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" + "PublicDescription": "Asserted if all bits specified by mask match= ", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Local - Lines in F State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus)= and PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" + "PublicDescription": "Asserted if all bits specified by mask match= ", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Remote - Lines in M State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "BriefDescription": "AND Mask/match for debug bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", "PerPkg": "1", - "UMask": "0x81", - "Unit": "CHA" + "PublicDescription": "Asserted if all bits specified by mask match= ", + "UMask": "0x20", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Remote - Lines in E State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", "PerPkg": "1", - "UMask": "0x82", - "Unit": "CHA" + "PublicDescription": "Asserted if any bits specified by mask match= ", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Remote - Lines in S State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", "PerPkg": "1", - "UMask": "0x84", - "Unit": "CHA" + "PublicDescription": "Asserted if any bits specified by mask match= ", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Remote - Lines in F State", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= !(PCIE bus)", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", "PerPkg": "1", - "UMask": "0x88", - "Unit": "CHA" + "PublicDescription": "Asserted if any bits specified by mask match= ", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized; Remote - All Lines", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "BriefDescription": "OR Mask/match for debug bus; PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", "PerPkg": "1", - "UMask": "0x8F", - "Unit": "CHA" + "PublicDescription": "Asserted if any bits specified by mask match= ", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy; All from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" + "PublicDescription": "Asserted if any bits specified by mask match= ", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts; RdCur misses from Local IO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", - "Filter": "config1=3D0x43C33", + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and !(PCIE bus)", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" + "PublicDescription": "Asserted if any bits specified by mask match= ", + "UMask": "0x20", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts; RFO misses from Local IO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", - "Filter": "config1=3D0x40033", + "BriefDescription": "UNC_IIO_NOTHING", + "EventName": "UNC_IIO_NOTHING", "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts; ItoM misses from Local IO", - "Counter": "0,1,2,3", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", - "Filter": "config1=3D0x49033", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", - "Filter": "config1=3D0x49033", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", - "Filter": "config1=3D0x43C33", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy; RFO misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", - "Filter": "config1=3D0x40033", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", + "PortMask": "0x10", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", + "PortMask": "0x20", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", + "PortMask": "0x1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", - "Counter": "0,1,2,3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", + "PortMask": "0x2", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Num Link Correctable Errors", - "Counter": "0,1,2,3", - "EventCode": "0xF", - "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "FCMask": "0x7", "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Num Link Retries", - "Counter": "0,1,2,3", - "EventCode": "0xE", - "EventName": "UNC_IIO_LINK_NUM_RETRIES", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "FCMask": "0x7", "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number packets that passed the Mask/Match Fil= ter", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_IIO_MASK_MATCH", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", + "FCMask": "0x7", "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x1", + "PortMask": "0x2", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus; PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x2", + "PortMask": "0x4", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d !(PCIE bus)", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", + "FCMask": "0x7", "PerPkg": "1", + "PortMask": "0x8", "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x8", + "PortMask": "0x10", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus)= and PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x10", + "PortMask": "0x20", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x20", + "PortMask": "0x1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", + "FCMask": "0x7", "PerPkg": "1", + "PortMask": "0x2", "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus; PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x2", + "PortMask": "0x4", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= !(PCIE bus)", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x4", + "PortMask": "0x8", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x8", + "PortMask": "0x10", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and PCIE bus", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x10", + "PortMask": "0x20", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and !(PCIE bus)", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "FCMask": "0x7", "PerPkg": "1", - "UMask": "0x20", + "PortMask": "0x1", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "UNC_IIO_NOTHING", - "Counter": "0,1,2,3", - "EventName": "UNC_IIO_NOTHING", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "FCMask": "0x7", "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", + "PortMask": "0x4", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", + "PortMask": "0x8", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", + "PortMask": "0x10", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", + "PortMask": "0x20", + "UMask": "0x40", "Unit": "IIO" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", @@ -8254,7 +12235,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", @@ -8266,7 +12246,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", @@ -8278,7 +12257,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", @@ -8289,784 +12267,697 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", - "Counter": "0,1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", + "PortMask": "0x10", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", + "PortMask": "0x20", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", - "UMask": "0x20", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", - "UMask": "0x20", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", - "UMask": "0x20", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", - "UMask": "0x20", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", + "PortMask": "0x10", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", "Deprecated": "1", "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", + "PortMask": "0x20", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", + "PortMask": "0x1", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", + "PortMask": "0x2", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", + "PortMask": "0x4", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", + "PortMask": "0x8", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", + "PortMask": "0x10", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", + "PortMask": "0x20", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", - "UMask": "0x2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", - "UMask": "0x2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", - "UMask": "0x2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", - "UMask": "0x2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", + "PortMask": "0x10", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", + "PortMask": "0x20", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", + "PortMask": "0x1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", + "PortMask": "0x2", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", + "PortMask": "0x4", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", + "PortMask": "0x8", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", + "PortMask": "0x10", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", + "PortMask": "0x20", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", - "UMask": "0x10", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", - "UMask": "0x10", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", - "UMask": "0x10", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", - "UMask": "0x10", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", + "PortMask": "0x10", "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", + "PortMask": "0x20", "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", + "PortMask": "0x1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", + "PortMask": "0x2", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", + "PortMask": "0x4", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", + "PortMask": "0x8", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", + "PortMask": "0x10", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", + "PortMask": "0x20", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", - "UMask": "0x80", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", - "UMask": "0x80", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "Deprecated": "1", "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Symbol Times on Link", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_IIO_SYMBOL_TIMES", - "PerPkg": "1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", + "PortMask": "0x10", "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", + "PortMask": "0x20", "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", + "PortMask": "0x1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", + "PortMask": "0x2", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", + "PortMask": "0x4", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", + "PortMask": "0x8", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", + "PortMask": "0x10", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", + "PortMask": "0x20", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", - "UMask": "0x4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", - "UMask": "0x4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", - "UMask": "0x4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", - "UMask": "0x4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", + "PortMask": "0x10", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - incr= ement once every 2nS, Gen3 - increment once every 1nS", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", + "PortMask": "0x1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", + "PortMask": "0x2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", + "PortMask": "0x4", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", + "PortMask": "0x8", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", + "PortMask": "0x10", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", + "PortMask": "0x20", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", @@ -9077,8 +12968,7 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", @@ -9089,8 +12979,7 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", @@ -9101,8 +12990,7 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", @@ -9113,59 +13001,76 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART0", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", - "UMask": "0x40", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART1", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", - "UMask": "0x40", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART2", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", - "UMask": "0x40", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART3", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", - "UMask": "0x40", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -9173,11 +13078,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -9185,11 +13089,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -9197,11 +13100,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -9209,107 +13111,98 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", + "PortMask": "0x10", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", + "PortMask": "0x20", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", + "PortMask": "0x1", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", + "PortMask": "0x2", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", + "PortMask": "0x4", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", + "PortMask": "0x8", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", + "PortMask": "0x10", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", + "PortMask": "0x20", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -9317,11 +13210,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -9329,11 +13221,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -9341,11 +13232,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -9353,104 +13243,95 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", + "PortMask": "0x10", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", + "PortMask": "0x20", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", + "PortMask": "0x1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", + "PortMask": "0x2", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", + "PortMask": "0x4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", + "PortMask": "0x8", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", + "PortMask": "0x10", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", + "PortMask": "0x20", + "UMask": "0x2", "Unit": "IIO" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", - "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", @@ -9462,7 +13343,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", - "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", @@ -9474,7 +13354,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", @@ -9486,7 +13365,6 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", @@ -9497,379 +13375,263 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", "Deprecated": "1", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x80", + "PortMask": "0x10", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", "Deprecated": "1", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x80", + "PortMask": "0x20", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", "Deprecated": "1", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; Vtd hit", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; context cache miss", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L1 miss", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L2 miss", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L3 miss", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", - "PerPkg": "1", + "PortMask": "0x1", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "VTd Access; TLB miss", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB is full", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB miss", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x40", - "EventName": "UNC_IIO_VTD_OCCUPANCY", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", + "PortMask": "0x2", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", + "PortMask": "0x4", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", + "PortMask": "0x8", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", + "PortMask": "0x10", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", + "PortMask": "0x1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", + "PortMask": "0x2", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", + "PortMask": "0x4", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", + "PortMask": "0x8", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x8", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x8", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", + "PortMask": "0x1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", - "Counter": "0,1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", + "PortMask": "0x2", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", + "PortMask": "0x4", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", + "PortMask": "0x8", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x10", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x10", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", + "PortMask": "0x1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", + "PortMask": "0x2", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", + "PortMask": "0x4", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", + "PortMask": "0x8", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -9877,11 +13639,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -9889,203 +13650,186 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", + "PortMask": "0x1", "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", + "PortMask": "0x2", "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", + "PortMask": "0x4", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", + "PortMask": "0x8", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x2", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", - "Counter": "2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x2", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", + "PortMask": "0x1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", + "PortMask": "0x2", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", + "PortMask": "0x4", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", + "PortMask": "0x8", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", + "PortMask": "0x1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", + "PortMask": "0x2", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", + "PortMask": "0x4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", "FCMask": "0x7", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", + "PortMask": "0x8", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -10093,11 +13837,10 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -10105,12643 +13848,12288 @@ "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x16 card plugged in to= stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 1", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x8 card plugged in to = Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x80", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x80", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x16 card plugged in to= stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x8 card plugged in to = Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 3", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x1", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x1", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x16 card plugged in to= stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x8 card plugged in to = Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 3", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x2", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", - "Counter": "0,1,2,3", - "Deprecated": "1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", - "FCMask": "0x7", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x2", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x16 card plugged in to= stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x8 card plugged in to = Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; x4 card is plugged in = to slot 3", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x20", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by a unit on the main die (generally a core) or = by another IIO unit to the MMIO space of a card on IIO Part0. In the genera= l case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that i= s plugged directly into one of the PCIe slots. Part0 could also refer to an= y device plugged into the first slot of a PCIe riser card or to a device at= tached to the IIO unit which starts its use of the bus using lane 0 of the = 16 lanes supported by the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x20", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by a unit on the main die (generally a core) or = by another IIO unit to the MMIO space of a card on IIO Part1. In the genera= l case, Part1 refers to a x4 PCIe card plugged into the second slot of a PC= Ie riser card, but it could refer to any x4 device attached to the IIO unit= using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part2", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by a unit on the main die (generally a core) or = by another IIO unit to the MMIO space of a card on IIO Part2. In the genera= l case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of= a PCIe riser card, but it could refer to any x4 or x8 device attached to t= he IIO unit and using lanes starting at lane 8 of the 16 lanes supported by= the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by a unit on the main die (generally a core) or = by another IIO unit to the MMIO space of a card on IIO Part3. In the genera= l case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PC= Ie riser card, but it could brefer to any device attached to the IIO unit = using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part0 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x80", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made to the MMIO space of a card on IIO Part0 by a un= it on the main die (generally a core) or by another IIO unit. In the genera= l case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that i= s plugged directly into one of the PCIe slots. Part0 could also refer to an= y device plugged into the first slot of a PCIe riser card or to a device at= tached to the IIO unit which starts its use of the bus using lane 0 of the = 16 lanes supported by the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part1 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x80", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made to the MMIO space of a card on IIO Part1 by a un= it on the main die (generally a core) or by another IIO unit. In the genera= l case, Part1 refers to a x4 PCIe card plugged into the second slot of a PC= Ie riser card, but it could refer to any x4 device attached to the IIO unit= using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part2 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x80", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made to the MMIO space of a card on IIO Part2 by a un= it on the main die (generally a core) or by another IIO unit. In the genera= l case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of= a PCIe riser card, but it could refer to any x4 or x8 device attached to t= he IIO unit and using lanes starting at lane 8 of the 16 lanes supported by= the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part3 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x80", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made to the MMIO space of a card on IIO Part3 by a un= it on the main die (generally a core) or by another IIO unit. In the genera= l case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PC= Ie riser card, but it could brefer to any device attached to the IIO unit = using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x40", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x40", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request for u= p to a 64 byte transaction of data made by a different IIO unit to the MMIO= space of a card on IIO Part0. Does not include requests made by the same I= IO unit. In the general case, part0 refers to a standard PCIe card of any s= ize (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 = could also refer to any device plugged into the first slot of a PCIe riser = card or to a device attached to the IIO unit which starts its use of the bu= s using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request for u= p to a 64 byte transaction of data made by a different IIO unit to the MMIO= space of a card on IIO Part1. Does not include requests made by the same I= IO unit. In the general case, Part1 refers to a x4 PCIe card plugged into t= he second slot of a PCIe riser card, but it could refer to any x4 device at= tached to the IIO unit using lanes starting at lane 4 of the 16 lanes suppo= rted by the bus.", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part2", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request for u= p to a 64 byte transaction of data made by a different IIO unit to the MMIO= space of a card on IIO Part2. Does not include requests made by the same I= IO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged = into the third slot of a PCIe riser card, but it could refer to any x4 or x= 8 device attached to the IIO unit and using lanes starting at lane 8 of the= 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request for u= p to a 64 byte transaction of data made by a different IIO unit to the MMIO= space of a card on IIO Part3. Does not include requests made by the same I= IO unit. In the general case, Part3 refers to a x4 PCIe card plugged into t= he fourth slot of a PCIe riser card, but it could brefer to any device att= ached to the IIO unit using the lanes starting at lane 12 of the 16 lanes s= upported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x80", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x80", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part0 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made to the MMIO space of a card on IIO = Part0 by a different IIO unit. Does not include requests made by the same I= IO unit. In the general case, Part0 refers to a standard PCIe card of any s= ize (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 = could also refer to any device plugged into the first slot of a PCIe riser = card or to a device attached to the IIO unit which starts its use of the bu= s using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part1 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made to the MMIO space of a card on IIO = Part1 by a different IIO unit. Does not include requests made by the same I= IO unit. In the general case, Part1 refers to a x4 PCIe card plugged into t= he second slot of a PCIe riser card, but it could refer to any x4 device at= tached to the IIO unit using lanes starting at lane 4 of the 16 lanes suppo= rted by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part2 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made to the MMIO space of a card on IIO = Part2 by a different IIO unit. Does not include requests made by the same I= IO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged = into the third slot of a PCIe riser card, but it could refer to any x4 or x= 8 device attached to the IIO unit and using lanes starting at lane 8 of the= 16 lanes supported by the bus.", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part3 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made to the MMIO space of a card on IIO = Part3 by a different IIO unit. Does not include requests made by the same I= IO unit. In the general case, Part3 refers to a x4 PCIe card plugged into t= he fourth slot of a PCIe riser card, but it could brefer to any device att= ached to the IIO unit using the lanes starting at lane 12 of the 16 lanes s= upported by the bus.", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests,= to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x16 card plugged in to= stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x4 card is plugged in = to slot 1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x08", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x8 card plugged in to = Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x08", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x4 card is plugged in = to slot 3", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card", - "Counter": "2,3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x16 card plugged in to= stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x4 card is plugged in = to slot 1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x8 card plugged in to = Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x4 card is plugged in = to slot 3", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x20", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by IIO Part0 to a unit on the main die (generall= y memory). In the general case, Part0 refers to a standard PCIe card of any= size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part= 0 could also refer to any device plugged into the first slot of a PCIe rise= r card or to a device attached to the IIO unit which starts its use of the = bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x20", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by IIO Part1 to a unit on the main die (generall= y memory). In the general case, Part1 refers to a x4 PCIe card plugged into= the second slot of a PCIe riser card, but it could refer to any x4 device = attached to the IIO unit using lanes starting at lane 4 of the 16 lanes sup= ported by the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x20", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by IIO Part2 to a unit on the main die (generall= y memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugge= d into the third slot of a PCIe riser card, but it could refer to any x4 or= x8 device attached to the IIO unit and using lanes starting at lane 8 of t= he 16 lanes supported by the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x20", + "PublicDescription": "Counts every read request for up to a 64 byt= e transaction of data made by IIO Part3 to a unit on the main die (generall= y memory). In the general case, Part3 refers to a x4 PCIe card plugged into= the fourth slot of a PCIe riser card, but it could brefer to any device a= ttached to the IIO unit using the lanes starting at lane 12 of the 16 lanes= supported by the bus.", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Messages", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Messages", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Messages", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made by IIO Part0 to a unit on the main die (generall= y memory). In the general case, Part0 refers to a standard PCIe card of any= size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part= 0 could also refer to any device plugged into the first slot of a PCIe rise= r card or to a device attached to the IIO unit which starts its use of the = bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Messages", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made by IIO Part1 to a unit on the main die (generall= y memory). In the general case, Part1 refers to a x4 PCIe card plugged into= the second slot of a PCIe riser card, but it could refer to any x4 device = attached to the IIO unit using lanes starting at lane 4 of the 16 lanes sup= ported by the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made by IIO Part2 to a unit on the main die (generall= y memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugge= d into the third slot of a PCIe riser card, but it could refer to any x4 or= x8 device attached to the IIO unit and using lanes starting at lane 8 of t= he 16 lanes supported by the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of up to a 64 byt= e transaction of data made by IIO Part3 to a unit on the main die (generall= y memory). In the general case, Part3 refers to a x4 PCIe card plugged into= the fourth slot of a PCIe riser card, but it could brefer to any device a= ttached to the IIO unit using the lanes starting at lane 12 of the 16 lanes= supported by the bus.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x16 card plugged in to= stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x4 card is plugged in = to slot 1", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Messages", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x8 card plugged in to = Lane 2/3, Or x4 card is plugged in to slot 2", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Messages", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; x4 card is plugged in = to slot 3", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part0 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x02", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request of up= to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO tar= get. In the general case, Part0 refers to a standard PCIe card of any size = (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 coul= d also refer to any device plugged into the first slot of a PCIe riser card= or to a device attached to the IIO unit which starts its use of the bus us= ing lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", - "Counter": "0,1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part1 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x02", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request of up= to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO tar= get. In the general case, Part1 refers to a x4 PCIe card plugged into the s= econd slot of a PCIe riser card, but it could refer to any x4 device attach= ed to the IIO unit using lanes starting at lane 4 of the 16 lanes supported= by the bus.", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part2 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x10", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request of up= to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO tar= get. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into= the third slot of a PCIe riser card, but it could refer to any x4 or x8 de= vice attached to the IIO unit and using lanes starting at lane 8 of the 16 = lanes supported by the bus.", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part3 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x10", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request of up= to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO tar= get. In the general case, Part3 refers to a x4 PCIe card plugged into the f= ourth slot of a PCIe riser card, but it could brefer to any device attached= to the IIO unit using the lanes starting at lane 12 of the 16 lanes suppor= ted by the bus.", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x10", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x10", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part0 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x20", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made by IIO Part0 to the MMIO space of a= n IIO target. In the general case, Part0 refers to a standard PCIe card of = any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. P= art0 could also refer to any device plugged into the first slot of a PCIe r= iser card or to a device attached to the IIO unit which starts its use of t= he bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part1 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x20", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made by IIO Part1 to the MMIO space of a= n IIO target.In the general case, Part1 refers to a x4 PCIe card plugged in= to the second slot of a PCIe riser card, but it could refer to any x4 devic= e attached to the IIO unit using lanes starting at lane 4 of the 16 lanes s= upported by the bus.", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part2 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x20", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made by IIO Part2 to the MMIO space of a= n IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plu= gged into the third slot of a PCIe riser card, but it could refer to any x4= or x8 device attached to the IIO unit and using lanes starting at lane 8 o= f the 16 lanes supported by the bus.", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part3 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x20", + "PublicDescription": "Counts every peer to peer write request of u= p to a 64 byte transaction of data made by IIO Part3 to the MMIO space of a= n IIO target. In the general case, Part3 refers to a x4 PCIe card plugged i= nto the fourth slot of a PCIe riser card, but it could brefer to any devic= e attached to the IIO unit using the lanes starting at lane 12 of the 16 la= nes supported by the bus.", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte ca= che line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "VTd Access; context cache miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "VTd Access; L1 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", + "BriefDescription": "VTd Access; L2 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x80", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", + "BriefDescription": "VTd Access; L3 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x80", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", + "BriefDescription": "VTd Access; Vtd hit", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x80", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", + "BriefDescription": "VTd Access; TLB miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", "PerPkg": "1", - "PortMask": "0x08", "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", - "FCMask": "0x07", + "BriefDescription": "VTd Access; TLB is full", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", "PerPkg": "1", - "PortMask": "0x10", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", - "FCMask": "0x07", + "BriefDescription": "VTd Access; TLB miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", - "FCMask": "0x07", + "BriefDescription": "VTd Occupancy", + "EventCode": "0x40", + "EventName": "UNC_IIO_VTD_OCCUPANCY", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", - "FCMask": "0x07", + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests f= rom any source port.", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", - "FCMask": "0x07", + "BriefDescription": "Total Write Cache Occupancy; Snoops", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" + "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", - "FCMask": "0x07", + "BriefDescription": "Total IRP occupancy of inbound read and write= requests.", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", - "Unit": "IIO" + "PublicDescription": "Total IRP occupancy of inbound read and writ= e requests. This is effectively the sum of read occupancy and write occupa= ncy.", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", - "FCMask": "0x07", + "BriefDescription": "IRP Clocks", + "EventCode": "0x1", + "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", - "Unit": "IIO" + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", - "FCMask": "0x07", + "BriefDescription": "Coherent Ops; CLFlush", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CRD", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", - "FCMask": "0x07", + "BriefDescription": "Coherent Ops; DRd", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.DRD", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", + "BriefDescription": "Coherent Ops; PCIRdCur", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", - "FCMask": "0x07", + "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "PCIITOM request issued by the IRP unit to th= e mesh with the intention of writing a full cacheline to coherent memory, w= ithout a RFO. PCIITOM is a speculative Invalidate to Modified command that= requests ownership of the cacheline and does not move data from the mesh t= o IRP cache.", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", - "FCMask": "0x07", + "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "RFO request issued by the IRP unit to the me= sh with the intention of writing a partial cacheline to coherent memory. R= FO is a Read For Ownership command that requests ownership of the cacheline= and moves data from the mesh to IRP cache.", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", + "BriefDescription": "Coherent Ops; WbMtoI", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x02", - "Unit": "IIO" + "PublicDescription": "Counts the number of coherency related opera= tions servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", + "BriefDescription": "FAF RF full", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x02", - "Unit": "IIO" + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", - "FCMask": "0x07", + "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" + "PublicDescription": "Inbound read requests to coherent memory, re= ceived by the IRP and inserted into the Fire and Forget queue (FAF), a queu= e used for processing inbound reads in the IRP.", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", + "BriefDescription": "Occupancy of the IRP FAF queue.", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) q= ueue, a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", + "BriefDescription": "FAF allocation -- sent to ADQ", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", + "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", + "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x08", - "Unit": "IIO" + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x10", - "Unit": "IIO" + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x10", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x10", - "Unit": "IIO" + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 0", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.UNKNOWN", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x10", - "Unit": "IIO" + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 1; Lost Forward", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", - "PortMask": "0x10", + "PublicDescription": "Snoop pulled away ownership before a write w= as committed", "UMask": "0x10", - "Unit": "IIO" + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" + "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 1; Received Valid", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x20", - "Unit": "IIO" + "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line"= , + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_E", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x20", - "Unit": "IIO" + "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line"= , + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_I", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x20", - "Unit": "IIO" + "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line"= , + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_M", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x20", - "Unit": "IIO" + "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line"= , + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_S", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", - "Unit": "IIO" + "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", + "BriefDescription": "P2P Requests", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", - "Unit": "IIO" + "PublicDescription": "P2P requests from the ITC", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", + "BriefDescription": "P2P Occupancy", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", - "Unit": "IIO" + "PublicDescription": "P2P B & S Queue Occupancy", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", + "BriefDescription": "P2P Transactions; P2P completions", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", - "Unit": "IIO" + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", - "FCMask": "0x07", + "BriefDescription": "P2P Transactions; match if local only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", "PerPkg": "1", - "PortMask": "0x10", "UMask": "0x40", - "Unit": "IIO" + "Unit": "IRP" }, { - "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", - "FCMask": "0x07", + "BriefDescription": "P2P Transactions; match if local and target m= atches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "Counter": "0,1", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "BriefDescription": "P2P Transactions; P2P Message", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x4", "Unit": "IRP" }, { - "BriefDescription": "Total Write Cache Occupancy; Snoops", - "Counter": "0,1", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "BriefDescription": "P2P Transactions; P2P reads", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", "PerPkg": "1", - "UMask": "0x2", + "UMask": "0x1", "Unit": "IRP" }, { - "BriefDescription": "IRP Clocks", - "Counter": "0,1", - "EventCode": "0x1", - "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "P2P Transactions; Match if remote only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", "PerPkg": "1", + "UMask": "0x10", "Unit": "IRP" }, { - "BriefDescription": "Coherent Ops; PCIRdCur", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "BriefDescription": "P2P Transactions; match if remote and target = matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x20", "Unit": "IRP" }, { - "BriefDescription": "Coherent Ops; CRd", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CRD", + "BriefDescription": "P2P Transactions; P2P Writes", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { - "BriefDescription": "Coherent Ops; DRd", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.DRD", + "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", + "UMask": "0x7e", "Unit": "IRP" }, { - "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", + "UMask": "0x74", "Unit": "IRP" }, { - "BriefDescription": "Coherent Ops; WbMtoI", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", + "UMask": "0x72", "Unit": "IRP" }, { - "BriefDescription": "Coherent Ops; CLFlush", - "Counter": "0,1", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M line in the IIO cache", + "UMask": "0x78", "Unit": "IRP" }, { - "BriefDescription": "FAF RF full", - "Counter": "0,1", - "EventCode": "0x17", - "EventName": "UNC_I_FAF_FULL", + "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", + "UMask": "0x71", "Unit": "IRP" }, { - "BriefDescription": "FAF allocation -- sent to ADQ", - "Counter": "0,1", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", + "BriefDescription": "Snoop Responses; Hit E or S", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", + "UMask": "0x4", "Unit": "IRP" }, { - "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", - "Counter": "0,1", - "EventCode": "0x1E", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "BriefDescription": "Snoop Responses; Hit I", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", - "UMask": "0x1", + "UMask": "0x2", "Unit": "IRP" }, { - "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", - "Counter": "0,1", - "EventCode": "0x1E", - "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "BriefDescription": "Snoop Responses; Hit M", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", - "UMask": "0x2", + "UMask": "0x8", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0; Fastpath Requests", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_REQ", + "BriefDescription": "Snoop Responses; Miss", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_REJ", + "BriefDescription": "Snoop Responses; SnpCode", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", - "UMask": "0x2", + "UMask": "0x10", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "BriefDescription": "Snoop Responses; SnpData", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", - "UMask": "0x4", + "UMask": "0x20", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "BriefDescription": "Snoop Responses; SnpInv", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", - "UMask": "0x8", + "UMask": "0x40", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "BriefDescription": "Inbound Transaction Count; Atomic", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of atomic = transactions", "UMask": "0x10", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_XFER", + "BriefDescription": "Inbound Transaction Count; Other", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of 'other'= kinds of transactions.", "UMask": "0x20", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of read pr= efetches.", + "UMask": "0x4", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 0", - "Counter": "0,1", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.UNKNOWN", + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.READS", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only read requests (n= ot including read prefetches).", + "UMask": "0x1", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line"= , - "Counter": "0,1", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_I", + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Trackes only write requests.= Each write request should have a prefetch, so there is no need to explici= tly track these requests. For writes that are tickled and have to retry, t= he counter will be incremented for each retry.", + "UMask": "0x2", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line"= , - "Counter": "0,1", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_S", + "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Inbound write (fast path) requests to cohere= nt memory, received by the IRP resulting in write ownership requests issued= by IRP to the mesh.", + "UMask": "0x8", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line"= , - "Counter": "0,1", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_E", + "BriefDescription": "AK Egress Allocations", + "EventCode": "0xB", + "EventName": "UNC_I_TxC_AK_INSERTS", "PerPkg": "1", - "UMask": "0x4", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line"= , - "Counter": "0,1", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_M", + "BriefDescription": "BL DRS Egress Cycles Full", + "EventCode": "0x5", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x8", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1; Lost Forward", - "Counter": "0,1", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.LOST_FWD", + "BriefDescription": "BL DRS Egress Inserts", + "EventCode": "0x2", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", "PerPkg": "1", - "UMask": "0x10", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1; Received Invalid", - "Counter": "0,1", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "BriefDescription": "BL DRS Egress Occupancy", + "EventCode": "0x8", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", "PerPkg": "1", - "UMask": "0x20", "Unit": "IRP" }, { - "BriefDescription": "Misc Events - Set 1; Received Valid", - "Counter": "0,1", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "BriefDescription": "BL NCB Egress Cycles Full", + "EventCode": "0x6", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x40", "Unit": "IRP" }, { - "BriefDescription": "P2P Requests", - "Counter": "0,1", - "EventCode": "0x14", - "EventName": "UNC_I_P2P_INSERTS", + "BriefDescription": "BL NCB Egress Inserts", + "EventCode": "0x3", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", "PerPkg": "1", "Unit": "IRP" }, { - "BriefDescription": "P2P Occupancy", - "Counter": "0,1", - "EventCode": "0x15", - "EventName": "UNC_I_P2P_OCCUPANCY", + "BriefDescription": "BL NCB Egress Occupancy", + "EventCode": "0x9", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", "PerPkg": "1", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; P2P reads", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "BriefDescription": "BL NCS Egress Cycles Full", + "EventCode": "0x7", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x1", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; P2P Writes", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "BriefDescription": "BL NCS Egress Inserts", + "EventCode": "0x4", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", "PerPkg": "1", - "UMask": "0x2", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; P2P Message", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "BriefDescription": "BL NCS Egress Occupancy", + "EventCode": "0xA", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", "PerPkg": "1", - "UMask": "0x4", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; P2P completions", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "Counts the number times when it is not possi= ble to issue a request to the R2PCIe because there are no AD Egress Credits= available.", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; Match if remote only", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number times when it is not possi= ble to issue data to the R2PCIe because there are no BL Egress Credits avai= lable.", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; match if remote and target = matches", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xD", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; match if local only", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xE", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", "Unit": "IRP" }, { - "BriefDescription": "P2P Transactions; match if local and target m= atches", - "Counter": "0,1", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xC", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Accumultes the number of outstanding outboun= d requests from the IRP to the switch (towards the devices). This can be u= sed in conjuection with the allocations event in order to calculate average= latency of outbound requests.", "Unit": "IRP" }, { - "BriefDescription": "Snoop Responses; Miss", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.MISS", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Snoop Responses; Hit I", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Snoop Responses; Hit E or S", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Snoop Responses; Hit M", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Snoop Responses; SnpCode", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Snoop Responses; SnpData", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpInv", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Inbound Transaction Count; Reads", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.READS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Inbound Transaction Count; Writes", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WRITES", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Atomic", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" + "Unit": "M2M" }, { - "BriefDescription": "Inbound Transaction Count; Other", - "Counter": "0,1", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.OTHER", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "No AD Egress Credit Stalls", - "Counter": "0,1", - "EventCode": "0x1A", - "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "AK Egress Allocations", - "Counter": "0,1", - "EventCode": "0xB", - "EventName": "UNC_I_TxC_AK_INSERTS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "BL DRS Egress Cycles Full", - "Counter": "0,1", - "EventCode": "0x5", - "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "BL DRS Egress Inserts", - "Counter": "0,1", - "EventCode": "0x2", - "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "BL DRS Egress Occupancy", - "Counter": "0,1", - "EventCode": "0x8", - "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "BL NCB Egress Cycles Full", - "Counter": "0,1", - "EventCode": "0x6", - "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "BL NCB Egress Inserts", - "Counter": "0,1", - "EventCode": "0x3", - "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "BL NCB Egress Occupancy", - "Counter": "0,1", - "EventCode": "0x9", - "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "BL NCS Egress Cycles Full", - "Counter": "0,1", - "EventCode": "0x7", - "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "BL NCS Egress Inserts", - "Counter": "0,1", - "EventCode": "0x4", - "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "BL NCS Egress Occupancy", - "Counter": "0,1", - "EventCode": "0xA", - "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "No BL Egress Credit Stalls", - "Counter": "0,1", - "EventCode": "0x1B", - "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Outbound Read Requests", - "Counter": "0,1", - "EventCode": "0xD", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "Outbound Read Requests", - "Counter": "0,1", - "EventCode": "0xE", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "Outbound Request Queue Occupancy", - "Counter": "0,1", - "EventCode": "0xC", - "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x72", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x74", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x78", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x7e", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", - "Counter": "0,1", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x71", - "Unit": "IRP" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x02", - "Unit": "UPI LL" + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x04", - "Unit": "UPI LL" + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", - "Counter": "0,1,2,3", - "EventCode": "0x16", - "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THR= ESH", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THR= ESH", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_UPI_PHY_INIT_CYCLES", - "PerPkg": "1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "L1 Req Nack", - "Counter": "0,1,2,3", - "EventCode": "0x23", - "EventName": "UNC_UPI_POWER_L1_NACK", + "BriefDescription": "Traffic in which the M2M to iMC Bypass was no= t taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts traffic in which the M2M (Mesh to Mem= ory) to iMC (Memory Controller) bypass was not taken", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "L1 Req (same as L1 Ack)", - "Counter": "0,1,2,3", + "BriefDescription": "M2M to iMC Bypass; Taken", "EventCode": "0x22", - "EventName": "UNC_UPI_POWER_L1_REQ", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", "PerPkg": "1", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", - "Counter": "0,1,2,3", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "BriefDescription": "M2M to iMC Bypass; Not Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", - "Counter": "0,1,2,3", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "BriefDescription": "M2M to iMC Bypass; Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", - "Counter": "0,1,2,3", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "BriefDescription": "Cycles - at UCLK", + "EventName": "UNC_M2M_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", - "Counter": "0,1,2,3", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Cycles in L0. Receive side", - "Counter": "0,1,2,3", + "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", "EventCode": "0x24", - "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts cycles when direct to core mode (whic= h bypasses the CHA) was disabled", + "Unit": "M2M" }, { - "BriefDescription": "CRC Errors Detected", - "Counter": "0,1,2,3", - "EventCode": "0xB", - "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "BriefDescription": "Messages sent direct to core (bypassing the C= HA)", + "EventCode": "0x23", + "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts when messages were sent direct to cor= e (bypassing the CHA)", + "Unit": "M2M" }, { - "BriefDescription": "LLR Requests Sent", - "Counter": "0,1,2,3", - "EventCode": "0x8", - "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "BriefDescription": "Number of reads in which direct to core trans= action were overridden", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts reads in which direct to core transac= tions (which would have bypassed the CHA) were overridden", + "Unit": "M2M" }, { - "BriefDescription": "VN0 Credit Consumed", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "BriefDescription": "Number of reads in which direct to Intel UPI = transactions were overridden", + "EventCode": "0x28", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts reads in which direct to Intel Ultra = Path Interconnect (UPI) transactions (which would have bypassed the CHA) we= re overridden", + "Unit": "M2M" }, { - "BriefDescription": "VN1 Credit Consumed", - "Counter": "0,1,2,3", - "EventCode": "0x3A", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "BriefDescription": "Cycles when direct to Intel UPI was disabled"= , + "EventCode": "0x27", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts cycles when the ability to send messa= ges direct to the Intel Ultra Path Interconnect (bypassing the CHA) was dis= abled", + "Unit": "M2M" }, { - "BriefDescription": "VNA Credit Consumed", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "BriefDescription": "Messages sent direct to the Intel UPI", + "EventCode": "0x26", + "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts when messages were sent direct to the= Intel Ultra Path Interconnect (bypassing the CHA)", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; Slot 0", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "BriefDescription": "Number of reads that a message sent direct2 I= ntel UPI was overridden", + "EventCode": "0x29", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" + "PublicDescription": "Counts when a read message that was sent dir= ect to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden= ", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; Slot 1", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "BriefDescription": "Directory Hit; On NonDirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" + "UMask": "0x80", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; Slot 2", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "BriefDescription": "Directory Hit; On NonDirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; Data", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.DATA", + "BriefDescription": "Directory Hit; On NonDirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" + "UMask": "0x40", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; LLCRD Not Empty", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "BriefDescription": "Directory Hit; On NonDirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; LLCTRL", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "BriefDescription": "Directory Hit; On Dirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.PROTHDR", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", + "BriefDescription": "Directory Hit; On Dirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", + "BriefDescription": "Directory Hit; On Dirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "BriefDescription": "Directory Hit; On Dirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", "PerPkg": "1", - "UMask": "0x9", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", + "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", - "UMask": "0xA", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks i= nto the multi-socket cacheline Directory state, and found the cacheline mar= ked in Any State (A, I, S or unused)", + "UMask": "0x1", + "Unit": "M2M" }, - { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.WB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", + { + "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", - "UMask": "0xB", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks i= nto the multi-socket cacheline Directory state, and found the cacheline mar= ked in the A (SnoopAll) state, indicating the cacheline is stored in anothe= r socket in any state, and we must snoop the other sockets to make sure we = get the latest data. The data may be stored in any state in the local sock= et.", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", + "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", - "UMask": "0xC", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks i= nto the multi-socket cacheline Directory state , and found the cacheline ma= rked in the I (Invalid) state indicating the cacheline is not stored in ano= ther socket, and so there is no need to snoop the other sockets for the lat= est data. The data may be stored in any state in the local socket.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", + "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", - "UMask": "0xD", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks i= nto the multi-socket cacheline Directory state , and found the cacheline ma= rked in the S (Shared) state indicating the cacheline is either stored in a= nother socket in the S(hared) state , and so there is no need to snoop the = other sockets for the latest data. The data may be stored in any state in = the local socket.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "BriefDescription": "Directory Miss; On NonDirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" + "UMask": "0x80", + "Unit": "M2M" }, { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "BriefDescription": "Directory Miss; On NonDirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "BriefDescription": "Directory Miss; On NonDirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" + "UMask": "0x40", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "BriefDescription": "Directory Miss; On NonDirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "BriefDescription": "Directory Miss; On Dirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "BriefDescription": "Directory Miss; On Dirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "BriefDescription": "Directory Miss; On Dirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "BriefDescription": "Directory Miss; On Dirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", - "Counter": "0,1,2,3", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "BriefDescription": "Multi-socket cacheline Directory update from = A to I", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates= the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid= )", "UMask": "0x20", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "BriefDescription": "Multi-socket cacheline Directory update from = A to S", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates= the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)= ", + "UMask": "0x40", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates= the multi-socket cacheline Directory to a new state", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "BriefDescription": "Multi-socket cacheline Directory update from = I to A", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates= the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll= )", "UMask": "0x4", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "BriefDescription": "Multi-socket cacheline Directory update from = I to S", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates= the multi-socket cacheline Directory state from I (Invalid) to S (Shared)"= , + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "BriefDescription": "Multi-socket cacheline Directory update from = S to A", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates= the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)= ", "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "BriefDescription": "Multi-socket cacheline Directory update from = S to I", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates= the multi-socket cacheline Directory state from S (Shared) to I (Invalid)"= , + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" + "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", - "Counter": "0,1,2,3", - "EventCode": "0x29", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Cycles in L0. Transmit side", - "Counter": "0,1,2,3", - "EventCode": "0x26", - "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.VERT", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Sent; Slot 0", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Sent; Slot 1", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x2", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Sent; Slot 2", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x4", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Sent; LLCTRL", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.PROTHDR", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x8", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x9", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.WB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0xC", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0xE", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0xF", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Tx Flit Buffer Allocations", - "Counter": "0,1,2,3", - "EventCode": "0x40", - "EventName": "UNC_UPI_TxL_INSERTS", + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Tx Flit Buffer Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x42", - "EventName": "UNC_UPI_TxL_OCCUPANCY", + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", - "Counter": "0,1,2,3", - "EventCode": "0x45", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "BriefDescription": "Reads to iMC issued", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", "PerPkg": "1", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues = reads to the iMC (Memory Controller).", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "VNA Credits Pending Return - Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x44", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "BriefDescription": "M2M Reads Issued to iMC; All, regardless of p= riority.", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", "PerPkg": "1", - "Unit": "UPI LL" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; Protocol Header", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "BriefDescription": "Reads to iMC issued at Normal Priority (Non-I= sochronous)", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues = reads to the iMC (Memory Controller). It only counts normal priority non-= isochronous reads.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Sent; Protocol Header", - "Counter": "0,1,2,3", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "BriefDescription": "Writes to iMC issued", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues = writes to the iMC (Memory Controller).", + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority.", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" + "UMask": "0x40", + "Unit": "M2M" }, { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH= ", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", "PerPkg": "1", - "UMaskExt": "0x02", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority.", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI", "PerPkg": "1", - "UMaskExt": "0x04", - "Unit": "UPI LL" + "UMask": "0x80", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", + "BriefDescription": "Partial Non-Isochronous writes to the iMC", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", "PerPkg": "1", - "UMaskExt": "0x08", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues = partial writes to the iMC (Memory Controller). It only counts normal prior= ity non-isochronous writes.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", "PerPkg": "1", - "UMaskExt": "0x10", - "Unit": "UPI LL" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", + "BriefDescription": "Number Packet Header Matches; MC Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", "PerPkg": "1", - "UMaskExt": "0x20", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", + "BriefDescription": "Number Packet Header Matches; Mesh Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", "PerPkg": "1", - "UMaskExt": "0x40", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", + "BriefDescription": "Prefetch CAM Cycles Full", + "EventCode": "0x53", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", "PerPkg": "1", - "UMask": "0xA", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", + "BriefDescription": "Prefetch CAM Cycles Not Empty", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", "PerPkg": "1", - "UMask": "0xC", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Valid Flits Received; Idle", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "BriefDescription": "Prefetch requests that got turn into a demand= request", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", "PerPkg": "1", - "UMask": "0x47", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) promote= s a outstanding request in the prefetch queue due to a subsequent demand re= ad request that entered the M2M with the same address. Explanatory Side No= te: The Prefetch queue is made of CAM (Content Addressable Memory)", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "BriefDescription": "Inserts into the Memory Controller Prefetch Q= ueue", + "EventCode": "0x57", + "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", - "UMask": "0x08", - "Unit": "UPI LL" + "PublicDescription": "Counts when the M2M (Mesh to Memory) receive= s a prefetch request and inserts it into its outstanding prefetch queue. E= xplanatory Side Note: the prefect queue is made from CAM: Content Addressab= le Memory", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t Opcode", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "BriefDescription": "Prefetch CAM Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", "PerPkg": "1", - "UMask": "0x0108", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Snoop"= , - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", "PerPkg": "1", - "UMask": "0x09", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Snoop = Opcode", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", "PerPkg": "1", - "UMask": "0x0109", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", "PerPkg": "1", - "UMask": "0x0A", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", "PerPkg": "1", - "UMask": "0x010A", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", "PerPkg": "1", - "UMask": "0x0C", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", "PerPkg": "1", - "UMask": "0x010C", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", "PerPkg": "1", - "UMask": "0x0D", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", "PerPkg": "1", - "UMask": "0x010D", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", "PerPkg": "1", - "UMask": "0x0E", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", "PerPkg": "1", - "UMask": "0x010E", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", "PerPkg": "1", - "UMask": "0x0F", - "Unit": "UPI LL" + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", "PerPkg": "1", - "UMask": "0x010F", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", "PerPkg": "1", - "UMask": "0x08", - "Unit": "UPI LL" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st Opcode", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", "PerPkg": "1", - "UMask": "0x108", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= ", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", "PerPkg": "1", - "UMask": "0x09", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= Opcode", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", "PerPkg": "1", - "UMask": "0x109", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", "PerPkg": "1", - "UMask": "0x0A", - "Unit": "UPI LL" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_M2M_RING_SRC_THRTL", "PerPkg": "1", - "UMask": "0x10A", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", - "UMask": "0x0C", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", - "UMask": "0x10C", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", - "UMask": "0x0D", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 0", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", "PerPkg": "1", - "UMask": "0x10D", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 1", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", "PerPkg": "1", - "UMask": "0x0E", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 2", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", "PerPkg": "1", - "UMask": "0x10E", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 0", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", "PerPkg": "1", - "UMask": "0x0F", - "Unit": "UPI LL" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", "PerPkg": "1", - "UMask": "0x10F", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Conflict", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 2", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", "PerPkg": "1", - "UMask": "0x01AA", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Invalid", - "Counter": "0,1,2,3", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "BriefDescription": "AD Ingress (from CMS) Full", + "EventCode": "0x4", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x012A", - "UMaskExt": "0x01", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", - "Counter": "0,1,2,3", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "EventCode": "0x3", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", "PerPkg": "1", - "UMask": "0x01", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", - "Counter": "0,1,2,3", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "BriefDescription": "AD Ingress (from CMS) Queue Inserts", + "EventCode": "0x1", + "EventName": "UNC_M2M_RxC_AD_INSERTS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "UPI LL" + "PublicDescription": "Counts when the a new entry is Received(RxC)= and then added to the AD (Address Ring) Ingress Queue from the CMS (Common= Mesh Stop). This is generally used for reads, and", + "Unit": "M2M" }, { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", - "Counter": "0,1,2,3", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x2", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", "PerPkg": "1", - "UMask": "0x04", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Conflict", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "BriefDescription": "BL Ingress (from CMS) Full", + "EventCode": "0x8", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x1AA", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Invalid", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "EventCode": "0x7", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", "PerPkg": "1", - "UMask": "0x12A", - "UMaskExt": "0x1", - "Unit": "UPI LL" + "Unit": "M2M" }, { - "BriefDescription": "M2M to iMC Bypass; Taken", - "Counter": "0,1,2,3", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", + "BriefDescription": "BL Ingress (from CMS) Allocations", + "EventCode": "0x5", + "EventName": "UNC_M2M_RxC_BL_INSERTS", "PerPkg": "1", - "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles - at UCLK", - "Counter": "0,1,2,3", - "EventName": "UNC_M2M_CLOCKTICKS", + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "EventCode": "0x6", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", "PerPkg": "1", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On Dirty Line in I State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On Dirty Line in S State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On Dirty Line in L State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On Dirty Line in A State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On NonDirty Line in I State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On NonDirty Line in S State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On NonDirty Line in L State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Directory Hit; On NonDirty Line in A State", - "Counter": "0,1,2,3", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On Dirty Line in I State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On Dirty Line in S State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On Dirty Line in L State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On Dirty Line in A State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On NonDirty Line in I State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "BriefDescription": "Transgress Injection Starvation; AK - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On NonDirty Line in S State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On NonDirty Line in L State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Directory Miss; On NonDirty Line in A State", - "Counter": "0,1,2,3", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ISOCH", + "BriefDescription": "Transgress Injection Starvation; IV - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "M2M Reads Issued to iMC; All, regardless of p= riority", - "Counter": "0,1,2,3", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH= ", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL", + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority", - "Counter": "0,1,2,3", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Number Packet Header Matches; Mesh Match", - "Counter": "0,1,2,3", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MESH", + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Number Packet Header Matches; MC Match", - "Counter": "0,1,2,3", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MC", + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Full", - "Counter": "0,1,2,3", - "EventCode": "0x53", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Not Empty", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x55", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Number AD Ingress Credits", - "Counter": "0,1,2,3", - "EventCode": "0x41", - "EventName": "UNC_M2M_TGR_AD_CREDITS", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Number BL Ingress Credits", - "Counter": "0,1,2,3", - "EventCode": "0x42", - "EventName": "UNC_M2M_TGR_BL_CREDITS", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Tracker Cycles Full; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Tracker Cycles Full; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Tracker Cycles Full; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Tracker Cycles Not Empty; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Tracker Cycles Not Empty; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Tracker Cycles Not Empty; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Tracker Inserts; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Tracker Inserts; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Tracker Inserts; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Tracker Occupancy; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Tracker Occupancy; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Data Pending Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Full; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", "PerPkg": "1", - "UMask": "0x2", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Full; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", "PerPkg": "1", - "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", "PerPkg": "1", - "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Inserts; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", + "BriefDescription": "Tracker Cycles Full; Channel 0", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Inserts; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", + "BriefDescription": "Tracker Cycles Full; Channel 1", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Inserts; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", + "BriefDescription": "Tracker Cycles Full; Channel 2", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy; Channel 0", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", + "BriefDescription": "Tracker Cycles Not Empty; Channel 0", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy; Channel 1", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", + "BriefDescription": "Tracker Cycles Not Empty; Channel 1", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy; Channel 2", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", + "BriefDescription": "Tracker Cycles Not Empty; Channel 2", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", + "BriefDescription": "Tracker Inserts; Channel 0", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", + "BriefDescription": "Tracker Inserts; Channel 1", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", + "BriefDescription": "Tracker Inserts; Channel 2", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", + "BriefDescription": "Tracker Occupancy; Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Tracker Occupancy; Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Tracker Occupancy; Channel 2", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Data Pending Occupancy", + "EventCode": "0x48", + "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "EventCode": "0xD", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", "PerPkg": "1", - "UMask": "0x08", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "EventCode": "0xE", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", "PerPkg": "1", - "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", + "BriefDescription": "AD Egress (to CMS) Full", + "EventCode": "0xC", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", + "BriefDescription": "AD Egress (to CMS) Not Empty", + "EventCode": "0xB", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", + "BriefDescription": "AD Egress (to CMS) Allocations", + "EventCode": "0x9", + "EventName": "UNC_M2M_TxC_AD_INSERTS", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "EventCode": "0xF", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", "PerPkg": "1", - "UMask": "0x08", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", + "BriefDescription": "AD Egress (to CMS) Occupancy", + "EventCode": "0xA", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", "PerPkg": "1", - "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", + "BriefDescription": "Outbound Ring Transactions on AK; CRD Transac= tions to Cbo", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Outbound Ring Transactions on AK; NDR Transac= tions", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", + "BriefDescription": "AK Egress (to CMS) Full; All", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - N= ear Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - F= ar Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request"= , + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request"= , + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x88", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0xa0", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x90", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", + "BriefDescription": "AK Egress (to CMS) Not Empty; All", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Req= uest", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare R= equest", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Re= quest", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", + "BriefDescription": "AK Egress (to CMS) Allocations; All", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Near Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Far Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2,3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", + "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read= Cam Hit", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", + "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit R= equest", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", + "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare= Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", + "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit = Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2,3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", - "Counter": "0,1,2,3", - "EventCode": "0xAE", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", - "Counter": "0,1,2,3", - "EventCode": "0xAE", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "BriefDescription": "AK Egress (to CMS) Occupancy; All", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Req= uest", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare R= equest", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Re= quest", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "BriefDescription": "AK Egress (to CMS) Sideband", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "BriefDescription": "AK Egress (to CMS) Sideband", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_UPI", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "Counter": "0,1,2,3", - "EventCode": "0xAD", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "Counter": "0,1,2,3", - "EventCode": "0xAD", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "BriefDescription": "BL Egress (to CMS) Full; All", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - N= ear Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - F= ar Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", - "Counter": "0,1,2,3", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "BriefDescription": "BL Egress (to CMS) Not Empty; All", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "BriefDescription": "BL Egress (to CMS) Allocations; All", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache", - "Counter": "0,1,2,3", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Near Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Far Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "Counter": "0,1,2,3", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "BriefDescription": "BL Egress (to CMS) Occupancy; All", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache", - "Counter": "0,1,2,3", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Source Throttle", - "Counter": "0,1,2,3", - "EventCode": "0xA4", - "EventName": "UNC_M2M_RING_SRC_THRTL", + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "AD Ingress (from CMS) Full", - "Counter": "0,1,2,3", - "EventCode": "0x4", - "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "AD Ingress (from CMS) Not Empty", - "Counter": "0,1,2,3", - "EventCode": "0x3", - "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "BL Ingress (from CMS) Full", - "Counter": "0,1,2,3", - "EventCode": "0x8", - "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "BL Ingress (from CMS) Not Empty", - "Counter": "0,1,2,3", - "EventCode": "0x7", - "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit"= , + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit"= , + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2,3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Credits Occupancy", - "Counter": "0,1,2,3", - "EventCode": "0xE", - "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Credit Acquired", - "Counter": "0,1,2,3", - "EventCode": "0xD", - "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Full", - "Counter": "0,1,2,3", - "EventCode": "0xC", - "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Not Empty", - "Counter": "0,1,2,3", - "EventCode": "0xB", - "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV"= , + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", - "Counter": "0,1,2,3", - "EventCode": "0xF", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", - "Counter": "0,1,2,3", - "EventCode": "0x10", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Outbound Ring Transactions on AK; CRD Transac= tions to Cbo", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Outbound Ring Transactions on AK; NDR Transac= tions", - "Counter": "0,1,2,3", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.NDR", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x1E", - "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x1E", - "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", - "Counter": "0,1,2,3", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", - "Counter": "0,1,2,3", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x1A", - "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x1A", - "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Full; All", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - N= ear Side", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - F= ar Side", - "Counter": "0,1,2,3", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.IV", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Not Empty; All", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV"= , + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 0", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 2", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 0", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 1", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 2", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", + "BriefDescription": "Write Tracker Cycles Full; Channel 0", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "BriefDescription": "Write Tracker Cycles Full; Channel 1", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", + "BriefDescription": "Write Tracker Cycles Full; Channel 2", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", + "BriefDescription": "Write Tracker Inserts; Channel 0", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "BriefDescription": "Write Tracker Inserts; Channel 1", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", + "BriefDescription": "Write Tracker Inserts; Channel 2", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", + "BriefDescription": "Write Tracker Occupancy; Channel 0", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "BriefDescription": "Write Tracker Occupancy; Channel 1", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", + "BriefDescription": "Write Tracker Occupancy; Channel 2", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce"= , - "Counter": "0,1,2,3", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", - "Counter": "0,1,2,3", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical ADS Used; IV", - "Counter": "0,1,2,3", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV"= , - "Counter": "0,1,2,3", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", - "Counter": "0,1,2,3", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "Counter": "0,1,2,3", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", + "BriefDescription": "CBox AD Credits Empty; Requests", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", + "BriefDescription": "CBox AD Credits Empty; Snoops", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", + "BriefDescription": "CBox AD Credits Empty; VNA Messages", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "Counter": "0,1,2,3", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", + "BriefDescription": "CBox AD Credits Empty; Writebacks", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_M3UPI_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Counts the number of uclks in the M3 uclk do= main. This could be slightly different than the count in the Ubox because = of enable/freeze delays. However, because the M3 is close to the Ubox, the= y generally should not diverge by more than a handful of cycles.", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", + "BriefDescription": "D2C Sent", + "EventCode": "0x2B", + "EventName": "UNC_M3UPI_D2C_SENT", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Count cases BL sends direct to core", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", + "BriefDescription": "D2U Sent", + "EventCode": "0x2A", + "EventName": "UNC_M3UPI_D2U_SENT", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" + "PublicDescription": "Cases where SMI3 sends D2U command", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", + "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", + "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "Counter": "0,1,2,3", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical IV Ring in Use; Down", - "Counter": "0,1,2,3", - "EventCode": "0xAC", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "Vertical IV Ring in Use; Up", - "Counter": "0,1,2,3", - "EventCode": "0xAC", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_TxC_BL.DRS_UPI", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x40", - "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 0", - "Counter": "0,1,2,3", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 1", - "Counter": "0,1,2,3", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the = same ring destination. (1 VN0 credit only)", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "No vn0 and vna credits available to send to = M2", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 2", - "Counter": "0,1,2,3", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "BriefDescription": "M2 BL Credits Empty; IIO2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "No vn0 and vna credits available to send to = M2", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", - "Counter": "0,1,2,3", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "BriefDescription": "M2 BL Credits Empty; IIO3", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "No vn0 and vna credits available to send to = M2", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "Counter": "0,1,2,3", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.IV", + "BriefDescription": "M2 BL Credits Empty; IIO4", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "No vn0 and vna credits available to send to = M2", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV"= , - "Counter": "0,1,2,3", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", + "BriefDescription": "M2 BL Credits Empty; IIO5", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "No vn0 and vna credits available to send to = M2", + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 0", - "Counter": "0,1,2,3", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS = are in single mask. ORs them together", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "No vn0 and vna credits available to send to = M2", + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 1", - "Counter": "0,1,2,3", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS cred= its", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "No vn0 and vna credits available to send to = M2", + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 2", - "Counter": "0,1,2,3", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC Bypass; Taken", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC Bypass; Not Taken", - "Counter": "0,1,2,3", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "CMS Clockticks", - "Counter": "0,1,2,3", - "EventCode": "0xC0", - "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 0", - "Counter": "0,1,2,3", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", + "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 1", - "Counter": "0,1,2,3", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", + "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 2", - "Counter": "0,1,2,3", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "FaST wire asserted; Vertical", - "Counter": "0,1,2,3", - "EventCode": "0xA5", - "EventName": "UNC_M2M_FAST_ASSERTED.VERT", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "FaST wire asserted; Horizontal", - "Counter": "0,1,2,3", - "EventCode": "0xA5", - "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 0", - "Counter": "0,1,2,3", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 1", - "Counter": "0,1,2,3", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 2", - "Counter": "0,1,2,3", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - N= ear Side", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - F= ar Side", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request"= , - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", "PerPkg": "1", "UMask": "0x20", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request"= , - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", "PerPkg": "1", - "UMask": "0x88", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", "PerPkg": "1", - "UMask": "0x90", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", "PerPkg": "1", - "UMask": "0xA0", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Full; All", - "Counter": "0,1,2,3", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", "PerPkg": "1", - "UMask": "0x03", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Req= uest", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_RING_SRC_THRTL", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Re= quest", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "BriefDescription": "Lost Arb for VN0; REQ on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" + "PublicDescription": "VN0 message requested but lost arbitration; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare R= equest", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "BriefDescription": "Lost Arb for VN0; RSP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" + "PublicDescription": "VN0 message requested but lost arbitration; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty; All", - "Counter": "0,1,2,3", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "BriefDescription": "Lost Arb for VN0; SNP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", "PerPkg": "1", - "UMask": "0x03", - "Unit": "M2M" + "PublicDescription": "VN0 message requested but lost arbitration; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "BriefDescription": "Lost Arb for VN0; NCB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "VN0 message requested but lost arbitration; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns."= , + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "BriefDescription": "Lost Arb for VN0; NCS on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "VN0 message requested but lost arbitration; = Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit R= equest", - "Counter": "0,1,2,3", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "BriefDescription": "Lost Arb for VN0; RSP on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "VN0 message requested but lost arbitration; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit = Request", - "Counter": "0,1,2,3", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "BriefDescription": "Lost Arb for VN0; WB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare= Request", - "Counter": "0,1,2,3", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "BriefDescription": "Lost Arb for VN1; REQ on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" + "PublicDescription": "VN1 message requested but lost arbitration; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read= Cam Hit", - "Counter": "0,1,2,3", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "BriefDescription": "Lost Arb for VN1; RSP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" + "PublicDescription": "VN1 message requested but lost arbitration; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Allocations; All", - "Counter": "0,1,2,3", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "BriefDescription": "Lost Arb for VN1; SNP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", "PerPkg": "1", - "UMask": "0x03", - "Unit": "M2M" + "PublicDescription": "VN1 message requested but lost arbitration; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "BriefDescription": "Lost Arb for VN1; NCB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "VN1 message requested but lost arbitration; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns."= , + "UMask": "0x20", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "BriefDescription": "Lost Arb for VN1; NCS on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "VN1 message requested but lost arbitration; = Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Req= uest", - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "BriefDescription": "Lost Arb for VN1; RSP on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "VN1 message requested but lost arbitration; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Re= quest", - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "BriefDescription": "Lost Arb for VN1; WB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", - "Unit": "M2M" + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare R= equest", - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" + "PublicDescription": "AD and BL messages won arbitration concurren= tly / in parallel", + "UMask": "0x40", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy; All", - "Counter": "0,1,2,3", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", "PerPkg": "1", - "UMask": "0x03", - "Unit": "M2M" + "PublicDescription": "Arbitration stage made no progress on pendin= g ad vn0 messages because slotting stage cannot accept new message", + "UMask": "0x4", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Sideband", - "Counter": "0,1,2,3", - "EventCode": "0x6B", - "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Arbitration stage made no progress on pendin= g ad vn1 messages because slotting stage cannot accept new message", + "UMask": "0x8", + "Unit": "M3UPI" }, { - "BriefDescription": "AK Egress (to CMS) Sideband", - "Counter": "0,1,2,3", - "EventCode": "0x6B", - "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Arbitration stage made no progress on pendin= g bl vn0 messages because slotting stage cannot accept new message", + "UMask": "0x10", + "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 AD Credits Empty; VNA", - "Counter": "0,1,2", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pendin= g bl vn1 messages because slotting stage cannot accept new message", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", "PerPkg": "1", + "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win= to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", "PerPkg": "1", + "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win= to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "BriefDescription": "Can't Arb for VN0; REQ on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x4", + "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Home (REQ) messages on AD. R= EQ is generally used to send requests, request responses, and snoop respons= es.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "BriefDescription": "Can't Arb for VN0; RSP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on AD= . RSP packets are used to transmit a variety of protocol flits including g= rants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "BriefDescription": "Can't Arb for VN0; SNP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Snoops (SNP) messages on AD. = SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "BriefDescription": "Can't Arb for VN0; NCB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Broadcast (NCB) = messages on BL. NCB is generally used to transmit data without coherency. = For example, non-coherent read data returns.", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "BriefDescription": "Can't Arb for VN0; NCS on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Standard (NCS) m= essages on BL.", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "BriefDescription": "Can't Arb for VN0; RSP on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on BL= . RSP packets are used to transmit a variety of protocol flits including gr= ants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "BriefDescription": "Can't Arb for VN0; WB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Data Response (WB) messages o= n BL. WB is generally used to transmit data with coherency. For example, = remote reads and writes, or cache to cache transfers will transmit their da= ta using WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "BriefDescription": "Can't Arb for VN1; REQ on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Home (REQ) messages on AD. R= EQ is generally used to send requests, request responses, and snoop respons= es.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", + "BriefDescription": "Can't Arb for VN1; RSP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x1", + "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on AD= . RSP packets are used to transmit a variety of protocol flits including g= rants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", + "BriefDescription": "Can't Arb for VN1; SNP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Snoops (SNP) messages on AD. = SNP is used for outgoing snoops.", "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", + "BriefDescription": "Can't Arb for VN1; NCB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", "PerPkg": "1", - "UMask": "0x8", + "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Broadcast (NCB) = messages on BL. NCB is generally used to transmit data without coherency. = For example, non-coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", + "BriefDescription": "Can't Arb for VN1; NCS on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Standard (NCS) m= essages on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "CBox AD Credits Empty; VNA Messages", - "Counter": "0,1,2", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "BriefDescription": "Can't Arb for VN1; RSP on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on BL= . RSP packets are used to transmit a variety of protocol flits including gr= ants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CBox AD Credits Empty; Writebacks", - "Counter": "0,1,2", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "BriefDescription": "Can't Arb for VN1; WB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Data Response (WB) messages o= n BL. WB is generally used to transmit data with coherency. For example, = remote reads and writes, or cache to cache transfers will transmit their da= ta using WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CBox AD Credits Empty; Requests", - "Counter": "0,1,2", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "BriefDescription": "No Credits to Arb for VN0; REQ on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses."= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CBox AD Credits Empty; Snoops", - "Counter": "0,1,2", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "BriefDescription": "No Credits to Arb for VN0; RSP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Number of uclks in domain", - "Counter": "0,1,2", - "EventCode": "0x1", - "EventName": "UNC_M3UPI_CLOCKTICKS", + "BriefDescription": "No Credits to Arb for VN0; SNP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "D2U Sent", - "Counter": "0,1,2", - "EventCode": "0x2A", - "EventName": "UNC_M3UPI_D2U_SENT", + "BriefDescription": "No Credits to Arb for VN0; NCB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the = same ring destination. (1 VN0 credit only)", - "Counter": "0,1,2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", + "BriefDescription": "No Credits to Arb for VN0; NCS on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messa= ges on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "M2 BL Credits Empty; IIO2", - "Counter": "0,1,2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "BriefDescription": "No Credits to Arb for VN0; RSP on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "M2 BL Credits Empty; IIO3", - "Counter": "0,1,2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "BriefDescription": "No Credits to Arb for VN0; WB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "M2 BL Credits Empty; IIO4", - "Counter": "0,1,2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "BriefDescription": "No Credits to Arb for VN1; REQ on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses."= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "M2 BL Credits Empty; IIO5", - "Counter": "0,1,2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "BriefDescription": "No Credits to Arb for VN1; RSP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS = are in single mask. ORs them together", - "Counter": "0,1,2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "BriefDescription": "No Credits to Arb for VN1; SNP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS cred= its", - "Counter": "0,1,2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "BriefDescription": "No Credits to Arb for VN1; NCB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", - "Counter": "0,1,2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "BriefDescription": "No Credits to Arb for VN1; NCS on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messa= ges on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", - "Counter": "0,1,2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "BriefDescription": "No Credits to Arb for VN1; RSP on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", - "Counter": "0,1,2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "BriefDescription": "No Credits to Arb for VN1; WB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", - "Counter": "0,1,2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Ar= b", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to slot 0 of independent flit while b= l message is in arbitration", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", - "Counter": "0,1,2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle"= , + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to slot 0 of independent flit while p= ipeline is idle", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", - "Counter": "0,1,2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl = message in same flit", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl = message in same flit", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "BriefDescription": "VN0 message lost contest for flit; REQ on AD"= , + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally u= sed to send requests, request responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "BriefDescription": "VN0 message lost contest for flit; RSP on AD"= , + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "BriefDescription": "VN0 message lost contest for flit; SNP on AD"= , + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for = outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "BriefDescription": "VN0 message lost contest for flit; NCB on BL"= , + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, non= -coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "BriefDescription": "VN0 message lost contest for flit; NCS on BL"= , + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "BriefDescription": "VN0 message lost contest for flit; RSP on BL"= , + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are= used to transmit a variety of protocol flits including grants and completi= ons (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for AD; VN1 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "BriefDescription": "VN0 message lost contest for flit; WB on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "AD FlowQ Bypass", - "Counter": "0,1,2", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "BriefDescription": "VN1 message lost contest for flit; REQ on AD"= , + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally u= sed to send requests, request responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "AD FlowQ Bypass", - "Counter": "0,1,2", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "BriefDescription": "VN1 message lost contest for flit; RSP on AD"= , + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "AD FlowQ Bypass", - "Counter": "0,1,2", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "BriefDescription": "VN1 message lost contest for flit; SNP on AD"= , + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for = outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "AD FlowQ Bypass", - "Counter": "0,1,2", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "BriefDescription": "VN1 message lost contest for flit; NCB on BL"= , + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, non= -coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "BriefDescription": "VN1 message lost contest for flit; NCS on BL"= , + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "BriefDescription": "VN1 message lost contest for flit; RSP on BL"= , + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are= used to transmit a variety of protocol flits including grants and completi= ons (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "BriefDescription": "VN1 message lost contest for flit; WB on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO"= , + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Indication that at least one packet (flit) i= s in the bgf (fifo only)", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path"= , + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Indication that at least one packet (flit) i= s in the bgf path (i.e. pipe to fifo)", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "VN0 or VN1 BL RSP message was blocked from a= rbitration request due to lack of D2K CMP credits", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "BriefDescription": "Credit Occupancy; D2K Credits", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "D2K completion fifo credit occupancy (credit= s in use), accumulated across all cycles", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Occupancy of m3upi ingress -> upi link la= yer bgf; packets (flits) in fifo", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "BriefDescription": "Credit Occupancy; Packets in BGF Path", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy of m3upi ingress -> upi link la= yer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "BriefDescription": "Credit Occupancy", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "count of bl messages in pump-1-pending state= , in completion fifo only", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "BriefDescription": "Credit Occupancy", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "count of bl messages in pump-1-pending state= , in marker table and in fifo", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "BriefDescription": "Credit Occupancy; Transmit Credits", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Link layer transmit queue credit occupancy (= credits in use), accumulated across all cycles", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "BriefDescription": "Credit Occupancy; VNA In Use", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Remote UPI VNA credit occupancy (number of c= redits in use), accumulated across all cycles", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", + "BriefDescription": "Data Flit Not Sent; All", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 RE= Q Messages", - "Counter": "0,1,2", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", + "BriefDescription": "Data Flit Not Sent; No BGF Credits", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 SN= P Messages", - "Counter": "0,1,2", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", + "BriefDescription": "Data Flit Not Sent; No TxQ Credits", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB= Messages", - "Counter": "0,1,2", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 0", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "generating bl data flit sequence; waiting fo= r data pump 0", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 RE= Q Messages", - "Counter": "0,1,2", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", "PerPkg": "1", + "PublicDescription": "pump-1-pending logic is at capacity (pending= table plus completion fifo at limit)", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 SN= P Messages", - "Counter": "0,1,2", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "pump-1-pending logic is tracking at least on= e message", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB= Messages", - "Counter": "0,1,2", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "pump-1-pending completion fifo is full", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ = Messages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "pump-1-pending logic is at or near capacity,= such that pump-0-only bl messages are getting stalled in slotting stage", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP = Messages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "a bl message finished but is in limbo and mo= ved to pump-1-pending logic", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP = Messages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 1", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "generating bl data flit sequence; waiting fo= r data pump 1", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB M= essages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC", "PerPkg": "1", - "UMask": "0x08", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ = Messages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", + "BriefDescription": "Sent Header Flit; One Message", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "One message in flit; VNA or non-VNA flit", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP = Messages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", + "BriefDescription": "Sent Header Flit; One Message in non-VNA", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "One message in flit; non-VNA flit", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP = Messages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "BriefDescription": "Sent Header Flit; Two Messages", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Two messages in flit; VNA flit", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB M= essages", - "Counter": "0,1,2", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "BriefDescription": "Sent Header Flit; Three Messages", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Three messages in flit; VNA flit", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "AK Flow Q Inserts", - "Counter": "0,1,2", - "EventCode": "0x2F", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", "PerPkg": "1", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "AK Flow Q Occupancy", - "EventCode": "0x1E", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", "PerPkg": "1", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for BL; VN0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "BriefDescription": "Slotting BL Message Into Header Flit; All", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "BriefDescription": "Slotting BL Message Into Header Flit; Needs D= ata Flit", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "BL message requires data flit sequence", + "UMask": "0x2", "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 0", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Waiting for header pump 0", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for BL; VN1 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Bubble", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit but f= lit transmission delayed", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Not Avail", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit and n= ot available", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", - "Counter": "0,1,2", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 1", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Waiting for header pump 1", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "BriefDescription": "Flit Gen - Header 1; Acumullate", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting control state machine is in any accumulate state= ; multi-message flit may be assembled over multiple cycles", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; header flit slotting control state machine is in accum_ready state; f= lit is ready to send but transmission is blocked; more messages may be slot= ted into flit", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; Flit is being assembled over multiple cycles, but no additional messa= ge is being slotted into flit in current cycle; accumulate cycle is wasted"= , + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting entered run-ahead state; new header flit is star= ted while transmission of prior, fully assembled flit is blocked", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting is in run-ahead to start new flit, and message i= s actually slotted into new flit", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "BriefDescription": "Flit Gen - Header 1; Parallel Ok", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; New header flit construction may proceed in parallel with data flit s= equence", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit finished assembly in parallel with data flit sequence", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "BriefDescription": "Flit Gen - Header 1; Parallel Message", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Events related to Header Flit Generation - S= et 1; Message is slotted into header flit in parallel with data flit sequen= ce", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Events related to Header Flit Generation - S= et 2; Rate-matching stall injected", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No= Message", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Events related to Header Flit Generation - S= et 2; Rate matching stall injected, but no additional message slotted durin= g stall cycle", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "BriefDescription": "Header Not Sent; All", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "BriefDescription": "Header Not Sent; No BGF Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No BGF credits available", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Me= ssage Slotted", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No BGF credits available; no additional message slotted in= to flit", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "BriefDescription": "Header Not Sent; No TxQ Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No TxQ credits available", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Me= ssage Slotted", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No TxQ credits available; no additional message slotted in= to flit", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "BriefDescription": "Header Not Sent; Sent - One Slot Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with only one slot taken (two slots fr= ee)", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with three slots taken (no slots free)= ", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with only two slots taken (one slots f= ree)", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "BriefDescription": "Message Held; Can't Slot AD", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "some AD message could not be slotted (logica= l OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "BriefDescription": "Message Held; Can't Slot BL", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "some BL message could not be slotted (logica= l OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "BriefDescription": "Message Held; Parallel AD Lost", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", "PerPkg": "1", + "PublicDescription": "some AD message lost contest for slot 0 (log= ical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "BriefDescription": "Message Held; Parallel Attempt", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "PublicDescription": "ad and bl messages attempted to slot into th= e same flit in parallel", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel BL Lost", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", "PerPkg": "1", + "PublicDescription": "some BL message lost contest for slot 0 (log= ical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "BriefDescription": "Message Held; Parallel Success", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "ad and bl messages were actually slotted int= o the same flit in paralle", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "BriefDescription": "Message Held; VN0", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "vn0 message(s) that couldn't be slotted into= last vn0 flit are held in slotting stage while processing vn1 flit", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", - "Counter": "0,1,2", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", + "BriefDescription": "Message Held; VN1", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "vn1 message(s) that couldn't be slotted into= last vn1 flit are held in slotting stage while processing vn0 flit", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", - "Counter": "0,1,2", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ o= n AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Home (REQ) = messages on AD. REQ is generally used to send requests, request responses,= and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 NC= S Messages", - "Counter": "0,1,2", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Response (R= SP) messages on AD. RSP packets are used to transmit a variety of protocol= flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 RS= P Messages", - "Counter": "0,1,2", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP o= n AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Snoops (SNP= ) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB= Messages", - "Counter": "0,1,2", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB o= n BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Non-Coheren= t Broadcast (NCB) messages on BL. NCB is generally used to transmit data w= ithout coherency. For example, non-coherent read data returns.", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 NC= B Messages", - "Counter": "0,1,2", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS o= n BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Non-Coheren= t Standard (NCS) messages on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Response (R= SP) messages on BL. RSP packets are used to transmit a variety of protocol = flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on= BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Data Respon= se (WB) messages on BL. WB is generally used to transmit data with coheren= cy. For example, remote reads and writes, or cache to cache transfers will= transmit their data using WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCB Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ o= n AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCS Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP o= n AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 WB Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB o= n BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCS Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS o= n BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCB Messages", - "Counter": "0,1,2", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Credit Used; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on= BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Credit Used; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ= on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Home (REQ) messages on AD. REQ is g= enerally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Credit Used; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on AD. RSP = packets are used to transmit a variety of protocol flits including grants a= nd completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Credit Used; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP= on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is= used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Credit Used; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB= on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Broadcast (NCB) message= s on BL. NCB is generally used to transmit data without coherency. For ex= ample, non-coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Credit Used; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS= on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Standard (NCS) messages= on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 No Credits; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on BL. RSP p= ackets are used to transmit a variety of protocol flits including grants an= d completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 No Credits; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB = on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote = reads and writes, or cache to cache transfers will transmit their data usin= g WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 No Credits; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ= on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Home (REQ) messages on AD. REQ is g= enerally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 No Credits; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on AD. RSP = packets are used to transmit a variety of protocol flits including grants a= nd completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 No Credits; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP= on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is= used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 No Credits; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB= on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Broadcast (NCB) message= s on BL. NCB is generally used to transmit data without coherency. For ex= ample, non-coherent read data returns.", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Credit Used; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS= on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Standard (NCS) messages= on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Credit Used; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on BL. RSP p= ackets are used to transmit a variety of protocol flits including grants an= d completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Credit Used; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB = on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote = reads and writes, or cache to cache transfers will transmit their data usin= g WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Credit Used; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "BriefDescription": "VN0 message can't slot into flit; REQ on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses."= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Credit Used; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "BriefDescription": "VN0 message can't slot into flit; RSP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Credit Used; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "BriefDescription": "VN0 message can't slot into flit; SNP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 No Credits; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "BriefDescription": "VN0 message can't slot into flit; NCB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 No Credits; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "BriefDescription": "VN0 message can't slot into flit; NCS on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Standard (NCS) messa= ges on BL.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 No Credits; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "BriefDescription": "VN0 message can't slot into flit; RSP on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 No Credits; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "BriefDescription": "VN0 message can't slot into flit; WB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 No Credits; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "BriefDescription": "VN1 message can't slot into flit; REQ on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses."= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 No Credits; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "BriefDescription": "VN1 message can't slot into flit; RSP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; CHA on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", + "BriefDescription": "VN1 message can't slot into flit; SNP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; CHA on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", + "BriefDescription": "VN1 message can't slot into flit; NCB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", + "BriefDescription": "VN1 message can't slot into flit; NCS on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", + "BriefDescription": "VN1 message can't slot into flit; RSP on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; WB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Snoop Arbitration; FlowQ Won", - "Counter": "0,1,2", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", + "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Snoop Arbitration; FlowQ Won", - "Counter": "0,1,2", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", + "BriefDescription": "SMI3 Prefetch Messages; Arrived", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", - "Counter": "0,1,2", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", - "Counter": "0,1,2", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Dropped because it was overwritten by new me= ssage while prefetch queue was full", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", + "BriefDescription": "SMI3 Prefetch Messages; Slotted", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", + "BriefDescription": "Remote VNA Credits; Any In Use", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "At least one remote vna credit is in use", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "BriefDescription": "Remote VNA Credits; Corrected", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of remote vna credits corrected (loca= l return) per cycle", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", + "BriefDescription": "Remote VNA Credits; Level < 1", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Remote vna credit level is less than 1 (i.e.= no vna credits available)", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", + "BriefDescription": "Remote VNA Credits; Level < 4", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Remote vna credit level is less than 4; bl (= or ad requiring 4 vna) cannot arb on vna", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", + "BriefDescription": "Remote VNA Credits; Level < 5", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Remote vna credit level is less than 5; para= llel ad/bl arb on vna not possible", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Remote VNA Credits; Used", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of remote vna credits consumed per cy= cle", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", + "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", + "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the CMS Ingress"= , + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", + "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Transgress Injection Starvation; AK - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", + "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", + "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Transgress Injection Starvation; IV - Bounce"= , + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", - "Counter": "0,1,2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", - "Counter": "0,1,2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", - "Counter": "0,1,2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", - "Counter": "0,1,2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", - "Counter": "0,1,2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", - "Counter": "0,1,2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", - "Counter": "0,1,2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", - "Counter": "0,1,2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", - "Counter": "0,1,2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", - "Counter": "0,1,2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", - "Counter": "0,1,2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", - "Counter": "0,1,2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "CMS Clockticks", - "Counter": "0,1,2", - "EventCode": "0xC0", - "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", - "Counter": "0,1,2", - "EventCode": "0xAE", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", - "Counter": "0,1,2", - "EventCode": "0xAE", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "Counter": "0,1,2", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "Counter": "0,1,2", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "Counter": "0,1,2", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "Counter": "0,1,2", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "Counter": "0,1,2", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "Counter": "0,1,2", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "Counter": "0,1,2", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "Counter": "0,1,2", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "Counter": "0,1,2", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress."= , + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "Counter": "0,1,2", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "Counter": "0,1,2", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "Counter": "0,1,2", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "Counter": "0,1,2", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "BriefDescription": "Failed ARB for AD; VN0 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "Counter": "0,1,2", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", - "Counter": "0,1,2", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", - "Counter": "0,1,2", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "AD arb but no win; arb request asserted but = not won", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", - "Counter": "0,1,2", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", - "Counter": "0,1,2", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", - "Counter": "0,1,2", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", - "Counter": "0,1,2", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", - "Counter": "0,1,2", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache", - "Counter": "0,1,2", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "Counter": "0,1,2", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "Counter": "0,1,2", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "Counter": "0,1,2", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "Counter": "0,1,2", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", - "Counter": "0,1,2", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "Counter": "0,1,2", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", - "Counter": "0,1,2", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", - "Counter": "0,1,2", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache", - "Counter": "0,1,2", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Source Throttle", - "Counter": "0,1,2", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN0; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN0; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN0; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN0; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN0; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN0; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN0; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN1; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN1; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN1; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN1; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "BriefDescription": "Number of Snoop Targets; CHA on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to CHA", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN1; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of non-idle = cycles in issuing Vn0 Snpf", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN1; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to peer UPI0", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Lost Arb for VN1; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to peer UPI1", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", - "Counter": "0,1,2", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", + "BriefDescription": "Number of Snoop Targets; CHA on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to CHA", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", - "Counter": "0,1,2", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of non-idle = cycles in issuing Vn1 Snpf", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN0", - "Counter": "0,1,2", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to peer UPI0", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN1", - "Counter": "0,1,2", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to peer UPI1", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN0", - "Counter": "0,1,2", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ t= xn issued when SnpF pending on Vn0", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN1", - "Counter": "0,1,2", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ V= n0 SnpF issued when SnpF pending on Vn1", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", - "Counter": "0,1,2", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ t= xn issued when SnpF pending on Vn1", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN0; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ V= n1 SnpF issued when SnpF pending on Vn0", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN0; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", + "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 REQ Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN0; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", + "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 SNP Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN0; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", + "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 WB Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN0; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", + "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 REQ Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN0; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", + "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 SNP Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN0; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", + "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 WB Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN1; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", + "BriefDescription": "Speculative ARB for AD - New Message; VN0 RE= Q Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN1; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", + "BriefDescription": "Speculative ARB for AD - New Message; VN0 SN= P Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN1; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", + "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB= Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN1; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", + "BriefDescription": "Speculative ARB for AD - New Message; VN1 RE= Q Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN1; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", + "BriefDescription": "Speculative ARB for AD - New Message; VN1 SN= P Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN1; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", + "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB= Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Can't Arb for VN1; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ = Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN0; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP = Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN0; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP = Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN0; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB M= essages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN0; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ = Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN0; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP = Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN0; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP = Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN0; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB M= essages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN1; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", + "BriefDescription": "AK Flow Q Inserts", + "EventCode": "0x2F", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", "PerPkg": "1", - "UMask": "0x01", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN1; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", + "BriefDescription": "AK Flow Q Occupancy", + "EventCode": "0x1E", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", "PerPkg": "1", - "UMask": "0x02", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN1; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", + "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN1; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", + "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN1; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", + "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN1; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", + "BriefDescription": "Failed ARB for BL; VN0 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "No Credits to Arb for VN1; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", + "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle"= , - "Counter": "0,1,2", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Ar= b", - "Counter": "0,1,2", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", - "Counter": "0,1,2", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "BriefDescription": "Failed ARB for BL; VN1 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "BL arb but no win; arb request asserted but = not won", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", - "Counter": "0,1,2", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message lost contest for flit; REQ on AD"= , - "Counter": "0,1,2", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", + "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message lost contest for flit; SNP on AD"= , - "Counter": "0,1,2", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", + "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message lost contest for flit; RSP on AD"= , - "Counter": "0,1,2", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", + "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message lost contest for flit; RSP on BL"= , - "Counter": "0,1,2", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", + "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message lost contest for flit; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", + "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message lost contest for flit; NCB on BL"= , - "Counter": "0,1,2", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", + "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message lost contest for flit; NCS on BL"= , - "Counter": "0,1,2", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", + "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message lost contest for flit; REQ on AD"= , - "Counter": "0,1,2", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", + "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message lost contest for flit; SNP on AD"= , - "Counter": "0,1,2", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", + "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message lost contest for flit; RSP on AD"= , - "Counter": "0,1,2", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", + "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message lost contest for flit; RSP on BL"= , - "Counter": "0,1,2", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", + "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message lost contest for flit; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", + "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message lost contest for flit; NCB on BL"= , - "Counter": "0,1,2", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", + "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message lost contest for flit; NCS on BL"= , - "Counter": "0,1,2", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", + "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO"= , - "Counter": "0,1,2", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path"= , - "Counter": "0,1,2", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", - "Counter": "0,1,2", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", + "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Credit Occupancy; VNA In Use", - "Counter": "0,1,2", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", - "Counter": "0,1,2", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Credit Occupancy; Packets in BGF Path", - "Counter": "0,1,2", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Credit Occupancy; Transmit Credits", - "Counter": "0,1,2", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "Credit Occupancy; D2K Credits", - "Counter": "0,1,2", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Credit Occupancy", - "Counter": "0,1,2", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Credit Occupancy", - "Counter": "0,1,2", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "BriefDescription": "Speculative ARB for BL - New Message; VN0 NC= S Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB= Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "BriefDescription": "Speculative ARB for BL - New Message; VN1 NC= B Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "BriefDescription": "Speculative ARB for BL - New Message; VN1 RS= P Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCS Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 RSP Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 WB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCS Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", + "UMask": "0x80", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 RSP Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 WB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Data Flit Not Sent; All", - "Counter": "0,1,2", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Data Flit Not Sent; No BGF Credits", - "Counter": "0,1,2", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Data Flit Not Sent; No TxQ Credits", - "Counter": "0,1,2", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 0", - "Counter": "0,1,2", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 1", - "Counter": "0,1,2", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Generating BL Data Flit Sequence", - "Counter": "0,1,2", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Generating BL Data Flit Sequence", - "Counter": "0,1,2", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Generating BL Data Flit Sequence", - "Counter": "0,1,2", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Generating BL Data Flit Sequence", - "Counter": "0,1,2", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Generating BL Data Flit Sequence", - "Counter": "0,1,2", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", - "Counter": "0,1,2", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_FLITS_MISC", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Sent Header Flit; One Message", - "Counter": "0,1,2", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Sent Header Flit; Two Messages", - "Counter": "0,1,2", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Sent Header Flit; Three Messages", - "Counter": "0,1,2", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Sent Header Flit; One Message in non-VNA", - "Counter": "0,1,2", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Slotting BL Message Into Header Flit; All", - "Counter": "0,1,2", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Slotting BL Message Into Header Flit; Needs D= ata Flit", - "Counter": "0,1,2", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 0", - "Counter": "0,1,2", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 1", - "Counter": "0,1,2", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1", - "Counter": "0,1,2", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Bubble", - "Counter": "0,1,2", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Not Avail", - "Counter": "0,1,2", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Acumullate", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Parallel Ok", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Parallel Message", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", - "Counter": "0,1,2", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", - "Counter": "0,1,2", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No= Message", - "Counter": "0,1,2", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Header Not Sent; All", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Header Not Sent; No BGF Credits", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Header Not Sent; No TxQ Credits", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit"= , + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M3UPI" }, - { - "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Me= ssage Slotted", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Me= ssage Slotted", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Header Not Sent; Sent - One Slot Taken", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit"= , + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce"= , + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", - "Counter": "0,1,2", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; VN0", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; VN1", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; Parallel Attempt", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; Parallel Success", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; Parallel AD Lost", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; Parallel BL Lost", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; Can't Slot AD", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Message Held; Can't Slot BL", - "Counter": "0,1,2", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ o= n AD", - "Counter": "0,1,2", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP o= n AD", - "Counter": "0,1,2", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n AD", - "Counter": "0,1,2", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n BL", - "Counter": "0,1,2", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on= BL", - "Counter": "0,1,2", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB o= n BL", - "Counter": "0,1,2", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS o= n BL", - "Counter": "0,1,2", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ o= n AD", - "Counter": "0,1,2", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP o= n AD", - "Counter": "0,1,2", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n AD", - "Counter": "0,1,2", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n BL", - "Counter": "0,1,2", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on= BL", - "Counter": "0,1,2", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB o= n BL", - "Counter": "0,1,2", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS o= n BL", - "Counter": "0,1,2", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ= on AD", - "Counter": "0,1,2", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV"= , + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP= on AD", - "Counter": "0,1,2", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on AD", - "Counter": "0,1,2", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on BL", - "Counter": "0,1,2", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB = on BL", - "Counter": "0,1,2", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB= on BL", - "Counter": "0,1,2", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS= on BL", - "Counter": "0,1,2", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ= on AD", - "Counter": "0,1,2", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP= on AD", - "Counter": "0,1,2", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on AD", - "Counter": "0,1,2", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on BL", - "Counter": "0,1,2", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB = on BL", - "Counter": "0,1,2", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB= on BL", - "Counter": "0,1,2", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS= on BL", - "Counter": "0,1,2", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message can't slot into flit; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message can't slot into flit; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message can't slot into flit; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message can't slot into flit; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message can't slot into flit; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message can't slot into flit; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN0 message can't slot into flit; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message can't slot into flit; REQ on AD", - "Counter": "0,1,2", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message can't slot into flit; SNP on AD", - "Counter": "0,1,2", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message can't slot into flit; RSP on AD", - "Counter": "0,1,2", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message can't slot into flit; RSP on BL", - "Counter": "0,1,2", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message can't slot into flit; WB on BL", - "Counter": "0,1,2", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message can't slot into flit; NCB on BL", - "Counter": "0,1,2", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "VN1 message can't slot into flit; NCS on BL", - "Counter": "0,1,2", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "SMI3 Prefetch Messages; Arrived", - "Counter": "0,1,2", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", - "Counter": "0,1,2", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "SMI3 Prefetch Messages; Slotted", - "Counter": "0,1,2", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", - "Counter": "0,1,2", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", - "Counter": "0,1,2", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Used", - "Counter": "0,1,2", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Corrected", - "Counter": "0,1,2", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Level < 1", - "Counter": "0,1,2", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV"= , + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Level < 4", - "Counter": "0,1,2", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "No credits available to send to UPIs on the = AD Ring", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Level < 5", - "Counter": "0,1,2", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "No credits available to send to UPIs on the = AD Ring", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Any In Use", - "Counter": "0,1,2", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "No credits available to send to UPIs on the = AD Ring", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", + "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "No credits available to send to UPIs on the = AD Ring", + "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", + "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "No credits available to send to UPIs on the = AD Ring", + "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , - "Counter": "0,1,2", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "No credits available to send to UPIs on the = AD Ring", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , - "Counter": "0,1,2", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "BriefDescription": "UPI0 AD Credits Empty; VNA", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "No credits available to send to UPIs on the = AD Ring", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", + "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", + "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", + "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", + "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x40", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", + "BriefDescription": "UPI0 BL Credits Empty; VNA", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", + "BriefDescription": "Prefetches generated by the flow control queu= e of the M3UPI unit.", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Count cases where flow control queue that si= ts between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a pr= efetch to the iMC (Memory Controller)", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; AD - Credit"= , - "Counter": "0,1,2", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; BL - Credit"= , - "Counter": "0,1,2", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", - "Counter": "0,1,2", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "Counter": "0,1,2", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "BriefDescription": "VN0 Credit Used; WB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Data Response (WB) messages on BL. WB is generally used to tran= smit data with coherency. For example, remote reads and writes, or cache t= o cache transfers will transmit their data using WB.", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "BriefDescription": "VN0 Credit Used; NCB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally u= sed to transmit data without coherency. For example, non-coherent read dat= a returns.", + "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "BriefDescription": "VN0 Credit Used; REQ on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Home (REQ) messages on AD. REQ is generally used to send reques= ts, request responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "BriefDescription": "VN0 Credit Used; RSP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Response (RSP) messages on AD. RSP packets are used to transmit= a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "BriefDescription": "VN0 Credit Used; SNP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "BriefDescription": "VN0 Credit Used; RSP on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Response (RSP) messages on BL. RSP packets are used to transmit = a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "BriefDescription": "VN0 No Credits; WB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "BriefDescription": "VN0 No Credits; NCB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns."= , "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "BriefDescription": "VN0 No Credits; REQ on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of Cycles there were no VN0 Credits; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "BriefDescription": "VN0 No Credits; RSP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of Cycles there were no VN0 Credits; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "BriefDescription": "VN0 No Credits; SNP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of Cycles there were no VN0 Credits; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "BriefDescription": "VN0 No Credits; RSP on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of Cycles there were no VN0 Credits; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "BriefDescription": "VN1 Credit Used; WB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Data Response (WB) messages on BL. WB is generally used to trans= mit data with coherency. For example, remote reads and writes, or cache to= cache transfers will transmit their data using WB.", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "BriefDescription": "VN1 Credit Used; NCB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally us= ed to transmit data without coherency. For example, non-coherent read data= returns.", "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "BriefDescription": "VN1 Credit Used; REQ on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Home (REQ) messages on AD. REQ is generally used to send request= s, request responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "BriefDescription": "VN1 Credit Used; RSP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Response (RSP) messages on AD. RSP packets are used to transmit = a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "BriefDescription": "VN1 Credit Used; SNP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "BriefDescription": "VN1 Credit Used; RSP on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a= variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "BriefDescription": "VN1 No Credits; WB on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "BriefDescription": "VN1 No Credits; NCB on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns."= , "UMask": "0x20", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", - "Counter": "0,1,2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "BriefDescription": "VN1 No Credits; REQ on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Number of Cycles there were no VN1 Credits; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", + "UMask": "0x1", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", - "Counter": "0,1,2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "BriefDescription": "VN1 No Credits; RSP on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Number of Cycles there were no VN1 Credits; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", + "UMask": "0x4", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", - "Counter": "0,1,2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "BriefDescription": "VN1 No Credits; SNP on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Number of Cycles there were no VN1 Credits; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", - "Counter": "0,1,2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "BriefDescription": "VN1 No Credits; RSP on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Number of Cycles there were no VN1 Credits; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", + "UMask": "0x8", "Unit": "M3UPI" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", - "Counter": "0,1,2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_TxC_BL.DRS_UPI", + "Deprecated": "1", + "EventCode": "0x40", + "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", - "Counter": "0,1,2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (= UPI)", + "EventCode": "0x1", + "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Counts clockticks of the fixed frequency clo= ck controlling the Intel Ultra Path Interconnect (UPI). This clock runs at= 1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will= have a fixed Frequency of 1.2 Ghz.", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", + "BriefDescription": "Data Response packets that go direct to core"= , + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Counts Data Response (DRS) packets that atte= mpted to go direct to core bypassing the CHA.", + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Deprecated": "1", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", + "BriefDescription": "Data Response packets that go direct to Intel= UPI", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Counts Data Response (DRS) packets that atte= mpted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA= .", + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x10", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0x20", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "UMask": "0x40", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "UMask": "0x80", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", - "Counter": "0,1,2", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", + "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdow= n)", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Counts cycles when the Intel Ultra Path Inte= rconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down t= he UPI link. Link power states are per link and per direction, so for exam= ple the Tx direction could be in one state while Rx was in another, this ev= ent only coutns when both links are shutdown.", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", - "Counter": "0,1,2", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", - "Counter": "0,1,2", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", - "Counter": "0,1,2", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", - "Counter": "0,1,2", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", - "Counter": "0,1,2", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x10", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x20", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THR= ESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", - "Counter": "0,1,2", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", "PerPkg": "1", "UMask": "0x10", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THR= ESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x40", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "Counter": "0,1,2", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", + "BriefDescription": "L1 Req Nack", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Counts the number of times a link sends/rece= ives a LinkReqNAck. When the UPI links would like to change power state, t= he Tx side initiates a request to the Rx side requesting to change states. = This requests can either be accepted or denied. If the Rx side replies wi= th an Ack, the power mode will change. If it replies with NAck, no change = will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNA= ck refers to receiving an NAck (meaning this agent's Tx originally requeste= d the power change). A Tx LinkReqNAck refers to sending this command (mean= ing the peer agent's Tx originally requested the power change and this agen= t accepted it).", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "BriefDescription": "L1 Req (same as L1 Ack).", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "PublicDescription": "Counts the number of times a link sends/rece= ives a LinkReqAck. When the UPI links would like to change power state, th= e Tx side initiates a request to the Rx side requesting to change states. = This requests can either be accepted or denied. If the Rx side replies wit= h an Ack, the power mode will change. If it replies with NAck, no change w= ill take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck= refers to receiving an Ack (meaning this agent's Tx originally requested t= he power change). A Tx LinkReqAck refers to sending this command (meaning = the peer agent's Tx originally requested the power change and this agent ac= cepted it).", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "Counter": "0,1,2", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "Counter": "0,1,2", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "Counter": "0,1,2", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "Counter": "0,1,2", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", + "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p powe= r mode", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Counts cycles when the receive side (Rx) of = the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode = where we disable 60% of the UPI lanes, decreasing our bandwidth in order to= save power.", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "Counter": "0,1,2", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "BriefDescription": "Cycles in L0. Receive side.", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Number of UPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "Counter": "0,1,2", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCB", + "UMask": "0xe", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCB", + "UMask": "0x10e", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCS", + "UMask": "0xf", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCS", + "UMask": "0x10f", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce"= , - "Counter": "0,1,2", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "REQ Message Class", + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit"= , - "Counter": "0,1,2", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t Opcode", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]"= , + "UMask": "0x108", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit"= , - "Counter": "0,1,2", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Conflict", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x1aa", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Invalid", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x12a", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0xc", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10c", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", - "Counter": "0,1,2", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", + "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - RSP", + "UMask": "0xa", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - RSP", + "UMask": "0x10a", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop"= , + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "SNP Message Class", + "UMask": "0x9", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop = Opcode", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]"= , + "UMask": "0x109", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0xd", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", + "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10d", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to t= he Egress. This is a latency optimization, and should generally be the com= mon case. If this value is less than the number of FLITs transferred, it i= mplies that there was queueing getting onto the ring, and thus the transact= ions saw higher latency.", + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot1 RxQ buffer (Receive Queue) and passed directly acr= oss the BGF and into the Egress. This is a latency optimization, and shoul= d generally be the common case. If this value is less than the number of F= LITs transferred, it implies that there was queueing getting onto the ring,= and thus the transactions saw higher latency.", + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to = the Egress. This is a latency optimization, and should generally be the co= mmon case. If this value is less than the number of FLITs transferred, it = implies that there was queueing getting onto the ring, and thus the transac= tions saw higher latency.", + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "BriefDescription": "CRC Errors Detected", + "EventCode": "0xB", + "EventName": "UNC_UPI_RxL_CRC_ERRORS", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Number of CRC errors detected in the UPI Age= nt. Each UPI flit incorporates 8 bits of CRC for error detection. This co= unts the number of flits where the CRC was able to detect an error. After = an error has been detected, the UPI agent will send a request to the transm= itting socket to resend the flit (as well as any flits that came after it).= ", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; IV", - "Counter": "0,1,2", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", + "BriefDescription": "LLR Requests Sent", + "EventCode": "0x8", + "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Number of LLR Requests were transmitted. Th= is should generally be <=3D the number of CRC errors detected. If multi= ple errors are detected before the Rx side receives a LLC_REQ_ACK from the = Tx side, there is no need to send more LLR_REQ_NACKs.", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "BriefDescription": "VN0 Credit Consumed", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "BriefDescription": "VN1 Credit Consumed", + "EventCode": "0x3A", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "BriefDescription": "VNA Credit Consumed", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "PublicDescription": "Counts the number of times that an RxQ VNA c= redit was consumed (i.e. message uses a VNA credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", + "BriefDescription": "Valid data FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Counts valid data FLITs (80 bit FLow contro= l unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interc= onnect (UPI) Receive Queue slots on this UPI unit.", + "UMask": "0xf", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", + "BriefDescription": "Null FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs= ) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Qu= eue slots on this UPI unit.", + "UMask": "0x27", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", + "BriefDescription": "Valid Flits Received; Data", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.DATA", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Data Flits (which consume all slots), but how much to count= is based on Slot0-2 mask, so count can be 0-3 depending on which slots are= enabled for counting..", + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV"= , - "Counter": "0,1,2", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", + "BriefDescription": "Valid Flits Received; Idle", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).", + "UMask": "0x47", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", + "BriefDescription": "Valid Flits Received; LLCRD Not Empty", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables counting of LLCRD (with non-zero payload). This only appl= ies to slot 2 since LLCRD is only allowed in slot 2", "UMask": "0x10", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", + "BriefDescription": "Valid Flits Received; LLCTRL", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL = messages.", + "UMask": "0x40", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", + "BriefDescription": "Protocol header and credit FLITs received fro= m any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "PublicDescription": "Counts protocol header and credit FLITs (80= bit FLow control unITs) received from any of the 3 UPI slots on this UPI u= nit.", + "UMask": "0x97", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NULL", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x20", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", + "BriefDescription": "Valid Flits Received; Protocol Header", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slo= t uMask bits)", + "UMask": "0x80", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.PROTHDR", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0x80", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", - "Counter": "0,1,2", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", + "BriefDescription": "Valid Flits Received; Slot 0", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 0 - Other mask bits determine types of headers to coun= t.", + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", + "BriefDescription": "Valid Flits Received; Slot 1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 1 - Other mask bits determine types of headers to coun= t.", + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", + "BriefDescription": "Valid Flits Received; Slot 2", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 2 - Other mask bits determine types of headers to coun= t.", + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0xc", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0xd", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0xa", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "Counter": "0,1,2", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI LL" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "UMask": "0xb", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", + "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", + "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", + "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x10", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0x20", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "Counter": "0,1,2", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "UMask": "0x40", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", "PerPkg": "1", "UMask": "0x20", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", - "Counter": "0,1,2", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "UMask": "0x80", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", "PerPkg": "1", "UMask": "0x10", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", + "BriefDescription": "Cycles in which the Tx of the Intel Ultra Pat= h Interconnect (UPI) is in L0p power mode", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Counts cycles when the transmit side (Tx) of= the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode= where we disable 60% of the UPI lanes, decreasing our bandwidth in order t= o save power.", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", - "Counter": "0,1,2", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "Counter": "0,1,2", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "Counter": "0,1,2", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "BriefDescription": "Cycles in L0. Transmit side.", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Number of UPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "Counter": "0,1,2", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCB", + "UMask": "0xe", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "Counter": "0,1,2", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCB", + "UMask": "0x10e", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "Counter": "0,1,2", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCS", + "UMask": "0xf", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "Counter": "0,1,2", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - NCS", + "UMask": "0x10f", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "Counter": "0,1,2", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "REQ Message Class", + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "Counter": "0,1,2", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st Opcode", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]"= , + "UMask": "0x108", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "Counter": "0,1,2", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Conflict", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "UMask": "0x1aa", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "Counter": "0,1,2", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Invalid", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "UMask": "0x12a", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "Counter": "0,1,2", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0xc", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "Counter": "0,1,2", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10c", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical IV Ring in Use; Up", - "Counter": "0,1,2", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - RSP", + "UMask": "0xa", + "Unit": "UPI LL" }, { - "BriefDescription": "Vertical IV Ring in Use; Down", - "Counter": "0,1,2", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class - RSP", + "UMask": "0x10a", + "Unit": "UPI LL" }, { - "BriefDescription": "D2C Sent", - "Counter": "0,1,2", - "EventCode": "0x2B", - "EventName": "UNC_M3UPI_D2C_SENT", + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= ", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", "PerPkg": "1", - "Unit": "M3UPI" + "PublicDescription": "SNP Message Class", + "UMask": "0x9", + "Unit": "UPI LL" }, { - "BriefDescription": "FaST wire asserted; Vertical", - "Counter": "0,1,2", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= Opcode", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]"= , + "UMask": "0x109", + "Unit": "UPI LL" }, { - "BriefDescription": "FaST wire asserted; Horizontal", - "Counter": "0,1,2", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", + "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0xd", + "Unit": "UPI LL" }, { - "BriefDescription": "Sent Header Flit", - "Counter": "0,1,2", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", + "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10d", + "Unit": "UPI LL" }, { - "BriefDescription": "Sent Header Flit", - "Counter": "0,1,2", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", + "BriefDescription": "FLITs that bypassed the TxL Buffer", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" + "PublicDescription": "Counts incoming FLITs (FLow control unITs) w= hich bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI L= ink. Generally, when data is transmitted across the Intel Ultra Path Interc= onnect (UPI), it will bypass the TxQ and pass directly to the link. Howeve= r, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR = mode, increasing latency to transfer out to the link.", + "Unit": "UPI LL" }, { - "BriefDescription": "Sent Header Flit", - "Counter": "0,1,2", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", + "BriefDescription": "Valid data FLITs transmitted via any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" + "PublicDescription": "Counts valid data FLITs (80 bit FLow control= unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path= Interconnect (UPI) slots on this UPI unit.", + "UMask": "0xf", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "Counter": "0,1,2", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", + "BriefDescription": "Null FLITs transmitted from any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs= ) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on = this UPI unit.", + "UMask": "0x27", + "Unit": "UPI LL" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV"= , - "Counter": "0,1,2", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", + "BriefDescription": "Valid Flits Sent; Data", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.DATA", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Data Flits (which consume all slots), but how much to count= is based on Slot0-2 mask, so count can be 0-3 depending on which slots are= enabled for counting..", + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "UPI0 BL Credits Empty; VNA", - "Counter": "0,1,2", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "BriefDescription": "Idle FLITs transmitted", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M3UPI" + "PublicDescription": "Counts when the Intel Ultra Path Interconnec= t(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle = must be sending either data FLITs, protocol/credit FLITs or idle FLITs.", + "UMask": "0x47", + "Unit": "UPI LL" }, { - "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", - "Counter": "0,1,2", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables counting of LLCRD (with non-zero payload). This only appl= ies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI LL" }, { - "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", - "Counter": "0,1,2", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "BriefDescription": "Valid Flits Sent; LLCTRL", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M3UPI" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL = messages.", + "UMask": "0x40", + "Unit": "UPI LL" }, { - "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", - "Counter": "0,1,2", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "BriefDescription": "Protocol header and credit FLITs transmitted = across any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M3UPI" + "PublicDescription": "Counts protocol header and credit FLITs (80 = bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Int= erconnect) slots on this UPI unit.", + "UMask": "0x97", + "Unit": "UPI LL" }, { - "BriefDescription": "Message Received; VLW", - "Counter": "0,1", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NULL", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" + "UMask": "0x20", + "Unit": "UPI LL" }, { - "BriefDescription": "Message Received; MSI", - "Counter": "0,1", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "BriefDescription": "Valid Flits Sent; Protocol Header", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slo= t uMask bits)", + "UMask": "0x80", + "Unit": "UPI LL" }, { - "BriefDescription": "Message Received; IPI", - "Counter": "0,1", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.PROTHDR", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" + "UMask": "0x80", + "Unit": "UPI LL" }, { - "BriefDescription": "Message Received", - "Counter": "0,1", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "BriefDescription": "Valid Flits Sent; Slot 0", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", "PerPkg": "1", - "UMask": "0x8", - "Unit": "UBOX" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 0 - Other mask bits determine types of headers to coun= t.", + "UMask": "0x1", + "Unit": "UPI LL" }, { - "BriefDescription": "Message Received", - "Counter": "0,1", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "BriefDescription": "Valid Flits Sent; Slot 1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", "PerPkg": "1", - "UMask": "0x10", - "Unit": "UBOX" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 1 - Other mask bits determine types of headers to coun= t.", + "UMask": "0x2", + "Unit": "UPI LL" }, { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "Counter": "0,1", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", + "BriefDescription": "Valid Flits Sent; Slot 2", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", "PerPkg": "1", - "Unit": "UBOX" + "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 2 - Other mask bits determine types of headers to coun= t.", + "UMask": "0x4", + "Unit": "UPI LL" }, { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "Counter": "0,1", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" + "Unit": "UPI LL" }, { - "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", - "Counter": "0,1", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDRAND", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" + "Unit": "UPI LL" }, { - "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", - "Counter": "0,1", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDSEED", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" + "Unit": "UPI LL" }, { - "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "Counter": "0,1", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" + "UMask": "0xe", + "Unit": "UPI LL" }, { - "BriefDescription": "RACU Request", - "Counter": "0,1", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", "PerPkg": "1", - "Unit": "UBOX" + "UMask": "0xf", + "Unit": "UPI LL" }, { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", - "Counter": "FIXED", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", "PerPkg": "1", - "Unit": "UBOX" + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_GTONE", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_GTONE", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CORE_SNP.CORE_GTONE", - "UMask": "0x42", - "Unit": "CHA" + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_GTONE", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_CORE_SNP.EVICT_GTONE", - "UMask": "0x82", - "Unit": "CHA" + "UMask": "0x8", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.NO_SNP", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_LOOKUP.NO_SNP", - "UMask": "0x2", - "Unit": "CHA" + "UMask": "0xc", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.SNP", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.SNP", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_LOOKUP.SNP", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0xa", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.HA", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated.", "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.HA", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_UPDATE.HA", - "UMask": "0x1", - "Unit": "CHA" + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.TOR", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.TOR", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_DIR_UPDATE.TOR", - "UMask": "0x2", - "Unit": "CHA" + "UMask": "0x9", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.EX_RDS", - "Counter": "0,1,2,3", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.WB", "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.EX_RDS", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_HITME_HIT.EX_RDS", - "UMask": "0x1", - "Unit": "CHA" + "UMask": "0xc", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RFO_HIT_S", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RFO_HIT_S", + "BriefDescription": "Tx Flit Buffer Allocations", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_MISC.RFO_HIT_S", - "UMask": "0x8", - "Unit": "CHA" + "PublicDescription": "Number of allocations into the UPI Tx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = TxQ and pass directly to the link. However, the TxQ will be used with L0p = and when LLR occurs, increasing latency to transfer out to the link. This = event can be used in conjunction with the Flit Buffer Occupancy event in or= der to calculate the average flit buffer lifetime.", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "Tx Flit Buffer Occupancy", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.INVITOE_LOCAL", - "UMask": "0x10", - "Unit": "CHA" + "PublicDescription": "Accumulates the number of flits in the TxQ. = Generally, when data is transmitted across UPI, it will bypass the TxQ and= pass directly to the link. However, the TxQ will be used with L0p and whe= n LLR occurs, increasing latency to transfer out to the link. This can be u= sed with the cycles not empty event to track average occupancy, or the allo= cations event to track average lifetime in the TxQ.", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_REMOTE", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.INVITOE_REMOTE", - "UMask": "0x20", - "Unit": "CHA" + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.READS", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS", + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.READS", - "UMask": "0x3", - "Unit": "CHA" + "PublicDescription": "Number of VNA credits in the Rx side that ar= e waitng to be returned back across the link.", + "Unit": "UPI LL" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.READS_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.READS_LOCAL", - "UMask": "0x1", - "Unit": "CHA" + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.WRITES", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES", + "BriefDescription": "Message Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.WRITES", - "UMask": "0xC", - "Unit": "CHA" + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.WRITES_LOCAL", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "BriefDescription": "Message Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; IPI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_REQUESTS.WRITES_LOCAL", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.; Inter Processor Interrupts", "UMask": "0x4", - "Unit": "CHA" + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IRQ", + "BriefDescription": "Message Received; MSI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.; Message Signaled Interrupts - interrupts sent by devi= ces (including PCIe via IOxAPIC) (Socket Mode only)", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; VLW", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_INSERTS.IRQ", + "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", "UMask": "0x1", - "Unit": "CHA" + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "UMask": "0x80", - "Unit": "CHA" + "PublicDescription": "Number of times an IDI Lock/SplitLock sequen= ce was started", + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IRQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_RxC_OCCUPANCY.IRQ", + "PublicDescription": "PHOLD cycles.", "UMask": "0x1", - "Unit": "CHA" + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPIFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPIFWD", "UMask": "0x4", - "Unit": "CHA" + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPSFWD", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSPSFWD", - "UMask": "0x8", - "Unit": "CHA" + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", "PerPkg": "1", - "PublicDescription": "This event is deprecated. Refer to new event= UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "UMask": "0x20", - "Unit": "CHA" + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "Number outstanding register requests within = message channel tracker", + "Unit": "UBOX" + }, + { + "BriefDescription": "UPI interconnect send bandwidth for payload. = Derived from unc_upi_txl_flits.all_data", + "EventCode": "0x2", + "EventName": "UPI_DATA_BANDWIDTH_TX", + "PerPkg": "1", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control= unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path= Interconnect (UPI) slots on this UPI unit.", + "ScaleUnit": "7.11E-06Bytes", + "UMask": "0xf", + "Unit": "UPI LL" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json b/to= ols/perf/pmu-events/arch/x86/skylakex/uncore-power.json index 64301a600ede..8e21dc3eff16 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json @@ -1,14 +1,13 @@ [ { "BriefDescription": "pclk Cycles", - "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This = event counts the number of pclk cycles measured while the counter was enabl= ed. The pclk, like the Memory Controller's dclk, counts at a constant rate= making it a good measure of actual wall time.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", - "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", "PerPkg": "1", @@ -16,7 +15,6 @@ }, { "BriefDescription": "UNC_P_DEMOTIONS", - "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", "PerPkg": "1", @@ -24,71 +22,70 @@ }, { "BriefDescription": "Phase Shed 0 Cycles", - "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", "PerPkg": "1", + "PublicDescription": "Cycles spent in phase-shedding power state 0= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", - "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", "PerPkg": "1", + "PublicDescription": "Cycles spent in phase-shedding power state 1= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", - "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", "PerPkg": "1", + "PublicDescription": "Cycles spent in phase-shedding power state 2= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", - "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", "PerPkg": "1", + "PublicDescription": "Cycles spent in phase-shedding power state 3= ", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", - "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when thermal con= ditions are the upper limit on frequency. This is related to the THERMAL_T= HROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are abo= ve the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled = at the output of the algorithm that determines the actual frequency, while = THERMAL_THROTTLE looks at the input.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", - "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when power is th= e upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", - "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when IO P Limit = is preventing us from dropping the frequency lower. This algorithm monitor= s the needs to the IO subsystem on both local and remote sockets and will m= aintain a frequency high enough to maintain good IO BW. This is necessary = for when all the IA cores on a socket are idle but a user still would like = to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the system = is changing frequency. This can not be filtered by thread ID. One can als= o use it with the occupancy counter that monitors number of threads in C0 t= o estimate the performance impact that frequency transitions had on the sys= tem.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES", - "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_MCP_PROCHOT_CYCLES", "PerPkg": "1", @@ -96,47 +93,46 @@ }, { "BriefDescription": "Memory Phase Shedding Cycles", - "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the PCU has= triggered memory phase shedding. This is a mode that can be run in the iM= C physicals that saves power at the expense of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", - "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C0. This event can be used in conjunction with edge detect to coun= t C0 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", - "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C2E. This event can be used in conjunction with edge detect to cou= nt C2E entrances (or exits using invert). Residency events do not include = transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C3", - "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C3. This event can be used in conjunction with edge detect to coun= t C3 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", - "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the package= was in C6. This event can be used in conjunction with edge detect to coun= t C6 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", - "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", "PerPkg": "1", @@ -144,55 +140,54 @@ }, { "BriefDescription": "Number of cores in C-State; C0 and C1", - "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C-State; C3", - "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C-State; C6 and C7", - "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", "Unit": "PCU" }, { "BriefDescription": "External Prochot", - "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in e= xternal PROCHOT mode. This mode is triggered when a sensor off the die det= ermines that something off-die (like DRAM) is too hot and must throttle to = avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", - "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that we are in I= nternal PROCHOT mode. This mode is triggered when a sensor on the die dete= rmines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", - "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Number of cycles spent performing core C sta= te transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", - "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json index dd334b416c57..f59405877ae8 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data loads that caused a page = walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB leve= ls, but the walk need not have completed.", @@ -11,8 +9,6 @@ }, { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a load. EPT page walk duration are excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -32,8 +26,6 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -42,8 +34,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 1G page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -52,8 +42,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 2M/4M page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -62,8 +50,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 4K page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -72,8 +58,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a load. EPT page walk duration are excluded in Skylake= .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a load. EPT page walk duration are excluded in Skylak= e microarchitecture.", @@ -82,8 +66,6 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data stores that caused a page= walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB lev= els, but the walk need not have completed.", @@ -92,8 +74,6 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit= the STLB (2nd Level TLB).", @@ -102,8 +82,6 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store. EPT page walk duration are excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -113,8 +91,6 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -123,8 +99,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 1G page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -133,8 +107,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M/4M page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -143,8 +115,6 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -153,8 +123,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a store. EPT page walk duration are excluded in Skylak= e.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a store. EPT page walk duration are excluded in Skyla= ke microarchitecture.", @@ -163,8 +131,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a EPT (Extended Page Table) walk for any request type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts cycles for each PMH (Page Miss Handle= r) that is busy with an EPT (Extended Page Table) walk for any request type= .", @@ -173,8 +139,6 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of flushes of the big or s= mall ITLB pages. Counting include both TLB Flush (covering all sets) and TL= B Set Clear (set-specific).", @@ -183,8 +147,6 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts page walks of any page size (4K/2M/4M= /1G) caused by a code fetch. This implies it missed in the ITLB and further= levels of TLB, but the walk need not have completed.", @@ -193,8 +155,6 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -202,8 +162,6 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request. EPT page walk duration are e= xcluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -213,8 +171,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -223,8 +179,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (1G)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -233,8 +187,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -243,8 +195,6 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -253,8 +203,6 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for an instruction fetch request. EPT page walk duration a= re excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss H= andler) that is busy with a page walk for an instruction fetch request. EPT= page walk duration are excluded in Skylake michroarchitecture.", @@ -263,8 +211,6 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -273,8 +219,6 @@ }, { "BriefDescription": "STLB flush attempts", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", --=20 2.39.0.314.g84b9a713c41-goog