From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AF1FC4332F for ; Thu, 15 Dec 2022 07:02:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229854AbiLOHCo (ORCPT ); Thu, 15 Dec 2022 02:02:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229864AbiLOHBr (ORCPT ); Thu, 15 Dec 2022 02:01:47 -0500 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 262E9654FB for ; Wed, 14 Dec 2022 22:58:12 -0800 (PST) Received: by mail-pj1-x1049.google.com with SMTP id z4-20020a17090ab10400b002195a146546so1242831pjq.9 for ; Wed, 14 Dec 2022 22:58:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=sgCDP3pJROkhad6DYzCvvAqrKeqJ49c0tHS0MI2Lno4=; b=RxkiuYSNhRrgfgAuAj719Y6c1q+ZpQATHevJcgd0RnPx51ybY58K/pUTgwua7PsLfO GOmSCqqnnFdPV5qJx7pGR8kdSE+A8IShbz+mqbrsNLjReKNskNYJ7bATa28vpmbw6ci8 RCZKEG85Tj28EVsCp4C9mPbBZK3g71DoZLg96H1NY48J7PozCc+Gmv7xh8XHkbGpBxwF 0oRjM2Ueg7D38AB7Qu2i/XDVpeTGIuyJ7smfi6uUxAWnyz+rsppCohQnjCFNRHooLUYP XGhJ5pFDH1dAdBsp2+hzTpUooidfSKDoeZ3vdB7yAxOpW+lUup/uuVYAOS8ZEC/kxjOw qqrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sgCDP3pJROkhad6DYzCvvAqrKeqJ49c0tHS0MI2Lno4=; b=1Zkyf2oKOz9CJQGiA8gGTO+dlyWGjw4HMU9FKBbya/lTgW24CTqcQeShCzTxOwxa3n /lh2bK4Sc5CANMwC6gVGLbqn6luOJipWciXpwi9tnugcQvXICdbkOUvrIT0htvYy6End gTHeDJJzy/x7dnLnmDpZjppIg3nAn0Cdxlb16YNHkd9eMVMpn9HRcx6ijeaHcVEvsSot cAjI9y03ap67LcnaojHIfDV8LrT/rmjwcIqrrWEPymraD7K2fUWU3afelTNKf77mUDZY EN71iZ5+ZZNyGkUpaaynQzLSKcvrv3LMB023bnvEd9Ip6NVidD9+Ot0zhjjVUYnE0KSC 51Mw== X-Gm-Message-State: ANoB5plowzLKSMcBeIaz2cDXMpj8p6mK24R7UwCzFDmiR56bPjzGcCqB YWeWgMUdanxyms/9d3zeCDqTgB6YGiT1 X-Google-Smtp-Source: AA0mqf6vb0umCO4Jxmwc5PTB7GMO6Fzs6Q/53DjQNIj/LBEksX305Kq4AWkCr0a6/zZQFVlN1zZd5vKXM2uX X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:c7dc:d96f:4f9:f59d]) (user=irogers job=sendgmr) by 2002:a63:3153:0:b0:478:9503:f498 with SMTP id x80-20020a633153000000b004789503f498mr24951913pgx.96.1671087491071; Wed, 14 Dec 2022 22:58:11 -0800 (PST) Date: Wed, 14 Dec 2022 22:55:06 -0800 In-Reply-To: <20221215065510.1621979-1-irogers@google.com> Message-Id: <20221215065510.1621979-20-irogers@google.com> Mime-Version: 1.0 References: <20221215065510.1621979-1-irogers@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Subject: [PATCH v1 28/32] perf vendor events intel: Refresh snowridgex events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Kan Liang , Xing Zhengjun , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Garry , Stephane Eranian , Perry Taylor , Caleb Biggers , Ian Rogers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the snowridgex events using the new tooling from: https://github.com/intel/perfmon The events are unchanged but unused json values are removed and descriptions improved. This increases consistency across the json files. Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/snowridgex/cache.json | 252 - .../arch/x86/snowridgex/floating-point.json | 11 - .../arch/x86/snowridgex/frontend.json | 36 - .../arch/x86/snowridgex/memory.json | 84 - .../pmu-events/arch/x86/snowridgex/other.json | 143 - .../arch/x86/snowridgex/pipeline.json | 213 - .../arch/x86/snowridgex/uncore-memory.json | 624 +- .../arch/x86/snowridgex/uncore-other.json | 26334 +++++++--------- .../arch/x86/snowridgex/uncore-power.json | 114 +- .../arch/x86/snowridgex/virtual-memory.json | 117 - 10 files changed, 11934 insertions(+), 15994 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json b/tools/p= erf/pmu-events/arch/x86/snowridgex/cache.json index d674ee88c3a5..0ab90e3bf76b 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/cache.json @@ -1,1137 +1,885 @@ [ { "BriefDescription": "Counts the number of core requests (demand an= d L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also coun= ts requests that would have gone directly to the External Queue (XQ), but a= re rejected due to a full or nearly full condition, indicating back pressur= e from the IDI link. The L2Q may also reject transactions from a core to = ensure fairness between cores, or to delay a cores dirty eviction when the = address conflicts incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core = basis.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of L1D cacheline (dirty) ev= ictions caused by load misses, stores, and prefetches.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "DL1.DIRTY_EVICTION", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of L1D cacheline (dirty) e= victions caused by load misses, stores, and prefetches. Does not count evi= ctions or dirty writebacks caused by snoops. Does not count a replacement = unless a (dirty) line was written back.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of demand and prefetch tran= sactions that the External Queue (XQ) rejects due to a full or near full co= ndition.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ANY", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the total number of L2 Cache accesses.= Counts on a per core basis.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of L2 Cache Accesses= , includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/= L2 Prefetches only. Counts on a per core basis.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a hit. Counts on a per core basis.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a hit from a front door request only (does not include rejects = or recycles), Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a miss. Counts on a per core basis.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a miss from a front door request only (does not include rejects= or recycles). Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of L2 Cache accesses that m= iss the L2 and get rejected. Counts on a per core basis.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.REJECTS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of L2 Cache accesses that = miss the L2 and get BBL reject short and long rejects (includes those coun= ted in L2_reject_XQ.any). Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x38" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in DRAM or MMIO (non-DRAM).", "SampleAfterValue": "200003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", "SampleAfterValue": "200003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the LLC or other co= re with HITE/F/M.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x7" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the LLC or other core with HITE/F/M.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles the core is stal= led due to a demand load which hit in the Last Level Cache (LLC) or other c= ore with HITE/F/M.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a store buffer being full.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x40" }, { "BriefDescription": "Counts the number of load uops retired that h= it in DRAM.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache, in which a snoop was required and modified data was for= warded from another core or module.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L1 data cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L1 data cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of memory uops retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of memory uops retired. A= single uop that performs both a load AND a store will be counted as 1, not= 2 (e.g. ADD [mem], CONST)", "SampleAfterValue": "200003", "UMask": "0x83" }, { "BriefDescription": "Counts the number of load uops retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of load uops retired= .", "SampleAfterValue": "200003", "UMask": "0x81" }, { "BriefDescription": "Counts the number of store uops retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of store uops retire= d.", "SampleAfterValue": "200003", "UMask": "0x82" }, { "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x21" }, { "BriefDescription": "Counts the number of memory uops retired that= were splits.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x43" }, { "BriefDescription": "Counts the number of retired split load uops.= ", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "Counts the number of retired split store uops= .", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x42" }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and modified data was fo= rwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, but no data was forwarde= d.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and non-modified data wa= s forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3001F803C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and modi= fied data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, but no d= ata was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and non-= modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where no snoop was needed to satisfy the reques= t.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED"= , "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x801F803C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that were supplied by the = L3 cache where a snoop was sent, the snoop hit, and modified data was forwa= rded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1001F803C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2001F803C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x401F803C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and modif= ied data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10003C0477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, but no da= ta was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x4003C0477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and non-m= odified data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x8003C0477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2003C0477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where no snoop was needed to satisfy the request= .", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1003C0477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores that were supplied by= the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1F803C0800", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x101F803C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and modified data= was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1010003C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, but no data was f= orwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1004003C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and non-modified = data was forwarded.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1008003C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1002003C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1001003C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory writes that were suppl= ied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x201F803C0000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x20" } diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json = b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json index 2e1b80c714fd..88522244b760 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json @@ -1,36 +1,25 @@ [ { "BriefDescription": "Counts the number of cycles the floating poin= t divider is busy.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.FPDIV", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles the floating poi= nt divider is busy. Does not imply a stall waiting for the divider.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", "SampleAfterValue": "20003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x8" } diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json b/tool= s/perf/pmu-events/arch/x86/snowridgex/frontend.json index 5d938a5dafcf..5ba998e06592 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json @@ -1,103 +1,67 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of BACLEARS due to a condit= ional jump.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.COND", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of BACLEARS due to an indir= ect branch.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.INDIRECT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of BACLEARS due to a return= branch.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.RETURN", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of BACLEARS due to a direct= , unconditional jump.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.UNCOND", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of times a decode restricti= on reduces the decode throughput due to wrong instruction length prediction= .", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xe9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of requests to the instruct= ion cache for one or more bytes of a cache line.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", "SampleAfterValue": "200003", "UMask": "0x3" }, { "BriefDescription": "Counts the number of instruction cache hits."= , - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of requests that hit in th= e instruction cache. The event only counts new cache line accesses, so tha= t multiple back to back fetches to the exact same cache line and byte chunk= count as one. Specifically, the event counts when accesses from sequentia= l code crosses the cache line boundary, or when a branch target is moved to= a new line or to a non-sequential byte chunk of the same line.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of instruction cache misses= .", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", "SampleAfterValue": "200003", "UMask": "0x2" diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json b/tools/= perf/pmu-events/arch/x86/snowridgex/memory.json index 15eba23796e4..18621909d1a9 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json @@ -1,441 +1,357 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of misaligned load uops tha= t are 4K page splits.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of misaligned store uops th= at are 4K page splits.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3002184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3002184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x802184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x802184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1002184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1002184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2002184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2002184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184008000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x402184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x402184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all hardware and software prefetches t= hat were not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000470", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000800", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000800", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x102184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x102184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x202184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x202184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/other.json b/tools/p= erf/pmu-events/arch/x86/snowridgex/other.json index 4a1b7cc5aa23..00ae180ded25 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/other.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/other.json @@ -1,674 +1,531 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.SELF_LOCKS", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EdgeDetect": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.ALL", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock issued by other cores.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.BLOCK_CYCLES", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock issued by other cores. Counts on a per c= ore basis.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.BLOCK_CYCLES", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.LOCK_CYCLES", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock it issued.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.LOCK_CYCLES", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock it issued. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of bus locks a core issued = its self (e.g. lock to UC or Split Lock) and does not include cache locks."= , - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EdgeDetect": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.SELF_LOCKS", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of bus locks a core issued= its self (e.g. lock to UC or Split Lock) and does not include cache locks.= Counts on a per core basis.", "SampleAfterValue": "200003" }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_DRAM_HIT", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_DRAM_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_L2_HIT", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_L2_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_LLC_HIT", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_LLC_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of core cycles during which= interrupts are masked (disabled).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.MASKED", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of core cycles during which= there are pending interrupts while interrupts are masked (disabled).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of core cycles during whic= h there are pending interrupts while interrupts are masked (disabled). Incr= ements by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending= (which means the APIC is telling the ROB to cause an INTR). This event doe= s not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt = Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR= ) because in these cases the interrupts would be held up in the APIC and w= ould not be pended to the ROB. This event does count when an interrupt is o= nly inhibited by MOV/POP SS state machines or the STI state machine. These = extra inhibits only last for a single instructions and would not be importa= nt.", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of hardware interrupts rece= ived by the processor.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.RECEIVED", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "203", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that have any type of r= esponse.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all code reads that have an outstandin= g request. Returns the number of cycles until the response is received (i.e= . XQ to XQ latency).", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000044", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3000000010000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8003000000000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000004", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000001", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000002", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x800000010000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that have any type of resp= onse.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10400", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency)."= , - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000040", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000010", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000020", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000000010000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2000000010000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x18000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x400000010000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all hardware and software prefetches t= hat have any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10470", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000477", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts streaming stores that have any type of= response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10800", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that have any ty= pe of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100000010000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x100184000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory reads that have an out= standing request. Returns the number of cycles until the response is receiv= ed (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x8000100000000000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Counts uncached memory writes that have any t= ype of response.", - "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x200000010000", - "Offcore": "1", "SampleAfterValue": "100003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json b/tool= s/perf/pmu-events/arch/x86/snowridgex/pipeline.json index 09919fdb9a38..9dd8c909facc 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json @@ -1,662 +1,449 @@ [ { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of instructions in w= hich the instruction pointer (IP) of the processor is resteered due to a br= anch instruction and the branch instruction successfully retires. All bran= ch type instructions are accounted for.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xf9" }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xbf" }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x7e" }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xeb" }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xfd" }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xf7" }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xfe" }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of mispredicted bran= ch instructions retired. All branch type instructions are accounted for. = Prediction of the branch target address enables the processor to begin exec= uting instructions before the non-speculative execution path is known. The = branch prediction unit (BPU) predicts the target address based on the instr= uction pointer (IP) of the branch and on the execution path through which e= xecution reached this IP. A branch misprediction occurs when the predict= ion is wrong, and results in discarding all instructions executed in the sp= eculative path and re-fetching from the correct path.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x7e" }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xeb" }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xf7" }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0xfe" }, { "BriefDescription": "Counts the total number of BTCLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xe8", "EventName": "BTCLEAR.ANY", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of BTCLEARS which oc= curs when the Branch Target Buffer (BTB) predicts a taken branch.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", - "CollectPEBSRecord": "2", - "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", - "PDIR_COUNTER": "NA", - "PEBScounters": "33", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses fixed counter 1.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses a programmable general purpose performance counter.", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", - "CollectPEBSRecord": "2", - "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PDIR_COUNTER": "NA", - "PEBScounters": "34", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", "UMask": "0x3" }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.ANY", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of cycles the integer divid= er is busy.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.IDIV", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of cycles the integer divi= der is busy. Does not imply a stall waiting for the divider.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", - "CollectPEBSRecord": "2", - "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", - "PEBScounters": "32", "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses fixed counter 0.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Counts the total number of instructions retir= ed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses a programmable general purpose performance counter.", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of retired loads that are b= locked for any of the following reasons: DTLB miss, address alias, store f= orward or data unknown (includes memory disambiguation blocks and ESP consu= ming load blocks).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the total number of machine clears for= any reason including, but not limited to, memory ordering, memory disambig= uation, SMC, and FP assist.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.ANY", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003" }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", "UMask": "0x1" }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", "SampleAfterValue": "1000003", "UMask": "0x6" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to branch mispredicts.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" }, { "BriefDescription": "This event is deprecated. Refer to new event = TOPDOWN_BAD_SPECULATION.FASTNUKE", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to backend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to certain allocation restriction= s.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stalls in w= hich a scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC or FPC RAT stalls, which c= an be due to FIQ or IEC reservation stalls in which the integer, floating p= oint or SIMD scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the physical register file una= ble to accept an entry (marble stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the reorder buffer being full = (ROB stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x40" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to scoreboards from the instructi= on queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x10" }, { "BriefDescription": "This event is deprecated.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to frontend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BACLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTCLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", "SampleAfterValue": "1000003", "UMask": "0x40" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to the microcode sequencer (MS)= .", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ITLB misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", "SampleAfterValue": "1000003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to other common frontend stalls= not categorized.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to wrong predecodes.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x4" }, { "BriefDescription": "Counts the total number of consumed retiremen= t slots.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "TOPDOWN_RETIRING.ALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the total number of uops retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of uops that are from comp= lex flows issued by the Microcode Sequencer (MS). This includes uops from f= lows due to complex instructions, faults, assists, and inserted flows.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in MS flows.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x2" } diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json index f2c17f19299f..7dc0910694ed 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json @@ -1,619 +1,545 @@ [ - { - "BriefDescription": "Pre-charge for reads", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_M_PRE_COUNT.RD", - "PerPkg": "1", - "UMask": "0x04", - "Unit": "iMC" - }, - { - "BriefDescription": "Pre-charge for writes", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_M_PRE_COUNT.WR", - "PerPkg": "1", - "UMask": "0x08", - "Unit": "iMC" - }, { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x04", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", + "PublicDescription": "Counts the total number of DRAM Read CAS com= mands, w/ and w/o auto-pre, issued on this channel. This includes underfil= ls.", "ScaleUnit": "64Bytes", - "UMask": "0x0f", + "UMask": "0xf", "Unit": "iMC" }, { - "BriefDescription": "read requests to memory controller", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.RD", + "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", + "PublicDescription": "Counts the total number of DRAM Write CAS co= mmands issued, w/ and w/o auto-pre, on this channel.", "ScaleUnit": "64Bytes", - "UMask": "0x0f", + "UMask": "0x30", "Unit": "iMC" }, { - "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "LLC_MISSES.MEM_WRITE", + "BriefDescription": "DRAM Activate Count : All Activates", + "EventCode": "0x01", + "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x30", + "PublicDescription": "DRAM Activate Count : All Activates : Counts= the number of DRAM Activate commands sent on this channel. Activate comma= nds are issued to open up a page on the DRAM devices so that it can be read= or written to with a CAS. One can calculate the number of Page Misses by = subtracting the number of Page Miss precharges from the number of Activates= .", + "UMask": "0xb", "Unit": "iMC" }, { - "BriefDescription": "write requests to memory controller", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.WR", + "BriefDescription": "DRAM Activate Count : Activate due to Bypass"= , + "EventCode": "0x01", + "EventName": "UNC_M_ACT_COUNT.BYP", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0x30", + "PublicDescription": "DRAM Activate Count : Activate due to Bypass= : Counts the number of DRAM Activate commands sent on this channel. Activ= ate commands are issued to open up a page on the DRAM devices so that it ca= n be read or written to with a CAS. One can calculate the number of Page M= isses by subtracting the number of Page Miss precharges from the number of = Activates.", + "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "All DRAM CAS commands issued", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", + "PublicDescription": "Counts the total number of DRAM CAS commands= issued on this channel.", "UMask": "0x3f", "Unit": "iMC" }, { - "BriefDescription": "Number of DRAM Refreshes Issued", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", + "BriefDescription": "All DRAM read CAS commands issued (including = underfills)", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the total number of DRAM Read CAS com= mands, w/ and w/o auto-pre, issued on this channel. This includes underfil= ls.", + "UMask": "0xf", "Unit": "iMC" }, { - "BriefDescription": "Number of DRAM Refreshes Issued", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CA= S commands w/auto-pre", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total= number or DRAM Read CAS commands issued on this channel. This includes bo= th regular RD CAS commands as well as those with explicit Precharge. AutoP= re is only used in systems that are using closed page policy. We do not fi= lter based on major mode, as RD_CAS is not issued during WMM (with the exce= ption of underfills).", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Number of DRAM Refreshes Issued", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "BriefDescription": "All DRAM read CAS commands issued (does not i= nclude underfills)", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the total number of DRAM Read CAS com= mands issued on this channel. This includes both regular RD CAS commands a= s well as those with implicit Precharge. We do not filter based on major = mode, as RD_CAS is not issued during WMM (with the exception of underfills)= .", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "BriefDescription": "DRAM underfill read CAS commands issued", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts the total of DRAM Read CAS commands i= ssued due to an underfill", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "BriefDescription": "All DRAM write CAS commands issued", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts the total number of DRAM Write CAS co= mmands issued, w/ and w/o auto-pre, on this channel.", + "UMask": "0x30", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/o auto-pre", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands. : Precharge due to p= age table", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/ auto-pre", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.WR_PRE", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Memory controller clock ticks", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", + "PublicDescription": "Clockticks of the integrated memory controll= er (IMC)", "Unit": "iMC" }, { - "BriefDescription": "Half clockticks for IMC", - "Counter": "FIXED", - "CounterType": "FIXED", - "EventCode": "0xff", - "EventName": "UNC_M_HCLOCKTICKS", - "PerPkg": "1", - "Unit": "iMC" - }, - { - "BriefDescription": "Read Pending Queue Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", - "PerPkg": "1", - "Unit": "iMC" - }, - { - "BriefDescription": "Read Pending Queue Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", - "PerPkg": "1", - "Unit": "iMC" - }, - { - "BriefDescription": "Write Pending Queue Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", + "BriefDescription": "Free running counter that increments for the = Memory Controller", + "EventName": "UNC_M_CLOCKTICKS_FREERUN", "PerPkg": "1", + "PublicDescription": "UNC_M_CLOCKTICKS_FREERUN", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", + "BriefDescription": "DRAM Precharge All Commands", + "EventCode": "0x44", + "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", + "PublicDescription": "DRAM Precharge All Commands : Counts the num= ber of times that the precharge all command was sent.", "Unit": "iMC" }, { - "BriefDescription": "DRAM Activate Count : All Activates", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_M_ACT_COUNT.ALL", + "BriefDescription": "Number of DRAM Refreshes Issued", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", - "UMask": "0x0B", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the= number of refreshes issued.", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "Number of DRAM Refreshes Issued", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", "PerPkg": "1", - "UMask": "0x1C", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the= number of refreshes issued.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Read Data Buffer Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_M_RDB_INSERTS", + "BriefDescription": "Number of DRAM Refreshes Issued", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the= number of refreshes issued.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "All DRAM read CAS commands issued (does not i= nclude underfills)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.RD_REG", + "BriefDescription": "Half clockticks for IMC", + "EventCode": "0xff", + "EventName": "UNC_M_HCLOCKTICKS", "PerPkg": "1", - "UMask": "0x01", "Unit": "iMC" }, { - "BriefDescription": "DRAM underfill read CAS commands issued", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "BriefDescription": "UNC_M_PARITY_ERRORS", + "EventCode": "0x2c", + "EventName": "UNC_M_PARITY_ERRORS", "PerPkg": "1", - "UMask": "0x04", "Unit": "iMC" }, { - "BriefDescription": "DRAM Activate Count : Activate due to Bypass"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_M_ACT_COUNT.BYP", + "BriefDescription": "UNC_M_PCLS.RD", + "EventCode": "0xA0", + "EventName": "UNC_M_PCLS.RD", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CA= S commands w/auto-pre", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "BriefDescription": "UNC_M_PCLS.TOTAL", + "EventCode": "0xA0", + "EventName": "UNC_M_PCLS.TOTAL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "BriefDescription": "UNC_M_PCLS.WR", + "EventCode": "0xA0", + "EventName": "UNC_M_PCLS.WR", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/ auto-pre", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "EventCode": "0x85", + "EventName": "UNC_M_POWER_CHANNEL_PPD", + "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100"= , + "MetricName": "power_channel_ppd", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Channel PPD Cycles : Number of cycles when a= ll the ranks in the channel are in PPD mode. If IBT=3Doff is enabled, then= this can be used to count those cycles. If it is not enabled, then this c= an count the number of cycles when that could have been taken advantage of.= ", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", + "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", + "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", + "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", + "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", + "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Cycles Memory is in self refresh power mode", + "EventCode": "0x43", + "EventName": "UNC_M_POWER_SELF_REFRESH", + "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= ", + "MetricName": "power_self_refresh", + "PerPkg": "1", + "PublicDescription": "Clock-Enabled Self-Refresh : Counts the numb= er of cycles when the iMC is in self-refresh and the iMC still has a clock.= This happens in some package C-states. For example, the PCU may ask the = iMC to enter self-refresh even though some of the cores are still processin= g. One use of this is for Monroe technology. Self-refresh is required dur= ing package C3 and C6, but there is no clock in the iMC at this time, so it= is not possible to count these cases.", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", + "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0", + "BriefDescription": "DRAM Precharge commands.", + "EventCode": "0x02", + "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", + "UMask": "0x1c", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1", + "BriefDescription": "Pre-charges due to page misses", + "EventCode": "0x02", + "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "DRAM Precharge commands. : Precharge due to = page miss : Counts the number of DRAM Precharge commands sent on this chann= el. : Pages Misses are due to precharges from bank scheduler (rd/wr request= s)", + "UMask": "0xc", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0", + "BriefDescription": "DRAM Precharge commands. : Precharge due to p= age table", + "EventCode": "0x02", + "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "DRAM Precharge commands. : Precharge due to = page table : Counts the number of DRAM Precharge commands sent on this chan= nel. : Prechages from Page Table", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1", + "BriefDescription": "Pre-charge for reads", + "EventCode": "0x02", + "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "DRAM Precharge commands. : Precharge due to = read : Counts the number of DRAM Precharge commands sent on this channel. := Precharge from read bank scheduler", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue CAM Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M_WPQ_READ_HIT.PCH0", + "BriefDescription": "Pre-charge for writes", + "EventCode": "0x02", + "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "DRAM Precharge commands. : Precharge due to = write : Counts the number of DRAM Precharge commands sent on this channel. = : Precharge from write bank scheduler", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue CAM Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M_WPQ_READ_HIT.PCH1", + "BriefDescription": "Read Data Buffer Full", + "EventCode": "0x19", + "EventName": "UNC_M_RDB_FULL", "PerPkg": "1", - "UMask": "0x02", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue CAM Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0", + "BriefDescription": "Read Data Buffer Inserts", + "EventCode": "0x17", + "EventName": "UNC_M_RDB_INSERTS", "PerPkg": "1", - "UMask": "0x01", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue CAM Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1", + "BriefDescription": "Read Data Buffer Not Empty", + "EventCode": "0x18", + "EventName": "UNC_M_RDB_NOT_EMPTY", "PerPkg": "1", - "UMask": "0x02", "Unit": "iMC" }, { - "BriefDescription": "UNC_M_PCLS.RD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M_PCLS.RD", + "BriefDescription": "Read Data Buffer Occupancy", + "EventCode": "0x1A", + "EventName": "UNC_M_RDB_OCCUPANCY", "PerPkg": "1", - "UMask": "0x01", "Unit": "iMC" }, { - "BriefDescription": "UNC_M_PCLS.WR", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M_PCLS.WR", + "BriefDescription": "Read Pending Queue Full Cycles", + "EventCode": "0x12", + "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { - "BriefDescription": "UNC_M_PCLS.TOTAL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M_PCLS.TOTAL", + "BriefDescription": "Read Pending Queue Full Cycles", + "EventCode": "0x15", + "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge All Commands", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M_DRAM_PRE_ALL", + "BriefDescription": "Read Pending Queue Not Empty", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0", "PerPkg": "1", + "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "UNC_M_PARITY_ERRORS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2c", - "EventName": "UNC_M_PARITY_ERRORS", + "BriefDescription": "Read Pending Queue Not Empty", + "EventCode": "0x11", + "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1", "PerPkg": "1", + "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_M_POWER_CHANNEL_PPD", - "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.= ", - "MetricName": "power_channel_ppd %", + "BriefDescription": "Read Pending Queue Allocations", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the = number of allocations into the Read Pending Queue. This queue is used to s= chedule reads out to the memory controller and to track the requests. Requ= ests allocate into the RPQ soon after they enter the memory controller, and= need credits for an entry in this buffer before being sent from the HA to = the iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Cycles Memory is in self refresh power mode", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_M_POWER_SELF_REFRESH", - "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= .", - "MetricName": "power_self_refresh %", + "BriefDescription": "Read Pending Queue Allocations", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the = number of allocations into the Read Pending Queue. This queue is used to s= chedule reads out to the memory controller and to track the requests. Requ= ests allocate into the RPQ soon after they enter the memory controller, and= need credits for an entry in this buffer before being sent from the HA to = the iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Read Data Buffer Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M_RDB_FULL", + "BriefDescription": "Read Pending Queue Occupancy", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates t= he occupancies of the Read Pending Queue each cycle. This can then be used= to calculate both the average occupancy (in conjunction with the number of= cycles not empty) and the average latency (in conjunction with the number = of allocations). The RPQ is used to schedule reads out to the memory contr= oller and to track the requests. Requests allocate into the RPQ soon after= they enter the memory controller, and need credits for an entry in this bu= ffer before being sent from the HA to the iMC. They deallocate after the CA= S command has been issued to memory.", "Unit": "iMC" }, { - "BriefDescription": "Read Data Buffer Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_M_RDB_NOT_EMPTY", + "BriefDescription": "Read Pending Queue Occupancy", + "EventCode": "0x81", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates t= he occupancies of the Read Pending Queue each cycle. This can then be used= to calculate both the average occupancy (in conjunction with the number of= cycles not empty) and the average latency (in conjunction with the number = of allocations). The RPQ is used to schedule reads out to the memory contr= oller and to track the requests. Requests allocate into the RPQ soon after= they enter the memory controller, and need credits for an entry in this bu= ffer before being sent from the HA to the iMC. They deallocate after the CA= S command has been issued to memory.", "Unit": "iMC" }, { - "BriefDescription": "Read Data Buffer Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1A", - "EventName": "UNC_M_RDB_OCCUPANCY", + "BriefDescription": "Write Pending Queue Full Cycles", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0", "PerPkg": "1", + "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Full Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0", + "BriefDescription": "Write Pending Queue Full Cycles", + "EventCode": "0x16", + "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1", "PerPkg": "1", + "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Full Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1", + "BriefDescription": "Write Pending Queue Not Empty", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0", "PerPkg": "1", + "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Full Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x22", - "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0", + "BriefDescription": "Write Pending Queue Not Empty", + "EventCode": "0x21", + "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1", "PerPkg": "1", + "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Full Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1", + "BriefDescription": "Write Pending Queue Allocations", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS.PCH0", "PerPkg": "1", + "PublicDescription": "Write Pending Queue Allocations : Counts the= number of allocations into the Write Pending Queue. This can then be used= to calculate the average queuing latency (in conjunction with the WPQ occu= pancy count). The WPQ is used to schedule write out to the memory controll= er and to track the writes. Requests allocate into the WPQ soon after they= enter the memory controller, and need credits for an entry in this buffer = before being sent from the CHA to the iMC. They deallocate after being iss= ued to DRAM. Write requests themselves are able to complete (from the pers= pective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/o auto-pre", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "BriefDescription": "Write Pending Queue Allocations", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS.PCH1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Write Pending Queue Allocations : Counts the= number of allocations into the Write Pending Queue. This can then be used= to calculate the average queuing latency (in conjunction with the WPQ occu= pancy count). The WPQ is used to schedule write out to the memory controll= er and to track the writes. Requests allocate into the WPQ soon after they= enter the memory controller, and need credits for an entry in this buffer = before being sent from the CHA to the iMC. They deallocate after being iss= ued to DRAM. Write requests themselves are able to complete (from the pers= pective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Pre-charges due to page misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", + "BriefDescription": "Write Pending Queue Occupancy", + "EventCode": "0x82", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", "PerPkg": "1", - "UMask": "0x0c", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates = the occupancies of the Write Pending Queue each cycle. This can then be us= ed to calculate both the average queue occupancy (in conjunction with the n= umber of cycles not empty) and the average latency (in conjunction with the= number of allocations). The WPQ is used to schedule write out to the memo= ry controller and to track the writes. Requests allocate into the WPQ soon= after they enter the memory controller, and need credits for an entry in t= his buffer before being sent from the HA to the iMC. They deallocate after= being issued to DRAM. Write requests themselves are able to complete (fro= m the perspective of the rest of the system) as soon they have posted to th= e iMC. This is not to be confused with actually performing the write to DR= AM. Therefore, the average latency for this queue is actually not useful f= or deconstruction intermediate write latencies. So, we provide filtering b= ased on if the request has posted or not. By using the not posted filter, = we can track how long writes spent in the iMC before completions were sent = to the HA. The posted filter, on the other hand, provides information abou= t how much queueing is actually happenning in the iMC for writes before the= y are actually issued to memory. High average occupancies will generally c= oincide with high write major mode counts.", "Unit": "iMC" }, { - "BriefDescription": "Free running counter that increments for the = Memory Controller", - "Counter": "4", - "CounterType": "FREERUN", - "EventName": "UNC_M_CLOCKTICKS_FREERUN", + "BriefDescription": "Write Pending Queue Occupancy", + "EventCode": "0x83", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates = the occupancies of the Write Pending Queue each cycle. This can then be us= ed to calculate both the average queue occupancy (in conjunction with the n= umber of cycles not empty) and the average latency (in conjunction with the= number of allocations). The WPQ is used to schedule write out to the memo= ry controller and to track the writes. Requests allocate into the WPQ soon= after they enter the memory controller, and need credits for an entry in t= his buffer before being sent from the HA to the iMC. They deallocate after= being issued to DRAM. Write requests themselves are able to complete (fro= m the perspective of the rest of the system) as soon they have posted to th= e iMC. This is not to be confused with actually performing the write to DR= AM. Therefore, the average latency for this queue is actually not useful f= or deconstruction intermediate write latencies. So, we provide filtering b= ased on if the request has posted or not. By using the not posted filter, = we can track how long writes spent in the iMC before completions were sent = to the HA. The posted filter, on the other hand, provides information abou= t how much queueing is actually happenning in the iMC for writes before the= y are actually issued to memory. High average occupancies will generally c= oincide with high write major mode counts.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT.PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT.PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1", "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", + "UMask": "0x2", "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json b/= tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json index 1701db46696d..3b35e08e24d6 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json @@ -1,25060 +1,21961 @@ [ { - "BriefDescription": "Uncore cache clock ticks", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.= ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.MMIO_READ", + "Filter": "config1=3D0x40040e33", "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", "Unit": "CHA" }, { - "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts= .ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.MMIO_WRITE", + "Filter": "config1=3D0x40041e33", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Lin= e Non-ISOCH", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=3D0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DA= TA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC= _IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", "PerPkg": "1", - "UMask": "0x01", - "Unit": "CHA" + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x16 = card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 c= ard is plugged in to slot 0", + "ScaleUnit": "4Bytes", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Lines Victimized : All Lines Victimized", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_WRITE", + "FCMask": "0x07", + "Filter": "ch_mask=3D0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_D= ATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", "PerPkg": "1", - "UMask": "0x0F", - "Unit": "CHA" + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x16 ca= rd plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 car= d is plugged in to slot 0", + "ScaleUnit": "4Bytes", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Local read requests that miss the SF/LLC and = remote read requests sent to the CHA's home agent", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.UNCACHEABLE", + "Filter": "config1=3D0x40e33", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", "Unit": "CHA" }, { - "BriefDescription": "Local write requests that miss the SF/LLC and= remote write requests sent to the CHA's home agent", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_FULL", + "Filter": "config1=3D0x41833", "PerPkg": "1", - "UMask": "0x0c", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "ScaleUnit": "64Bytes", + "UMask": "0xc001fe01", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", + "Filter": "config1=3D0x41a33", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "ScaleUnit": "64Bytes", + "UMask": "0xc001fe01", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All requests from iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0xC001FF01", - "UMaskExt": "0xC001FF", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All requests from iA Cores that= Hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0xC001FD01", - "UMaskExt": "0xC001FD", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "UMask": "0xC80FFD01", - "UMaskExt": "0xC80FFD", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0xC807FD01", - "UMaskExt": "0xC807FD", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_cha_tor_inserts.ia_miss", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "config1=3D0x40e33", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.= ia_miss", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_READ", - "Filter": "config1=3D0x40040e33", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts= .ia_miss", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_WRITE", - "Filter": "config1=3D0x40041e33", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_cha_tor_inserts.ia_miss", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "config1=3D0x41833", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_cha_tor_inserts.ia_miss", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "config1=3D0x41a33", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "ScaleUnit": "64Bytes", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0xC80FFE01", - "UMaskExt": "0xC80FFE", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0xC807FE01", - "UMaskExt": "0xC807FE", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All requests from IO Devices", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0xC001FF04", - "UMaskExt": "0xC001FF", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All requests from IO Devices th= at hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0xC001FD04", - "UMaskExt": "0xC001FD", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All requests from IO Devices th= at missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0xC001FE04", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All requests from iA Cores", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0xC001FF01", - "UMaskExt": "0xC001FF", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0xC001FD01", - "UMaskExt": "0xC001FD", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0xC001FE01", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0xC80FFE01", - "UMaskExt": "0xC80FFE", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0xC807FE01", - "UMaskExt": "0xC807FE", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All requests from IO Devices"= , - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0xC001FF04", - "UMaskExt": "0xC001FF", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All requests from IO Devices = that hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0xC001FD04", - "UMaskExt": "0xC001FD", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All requests from IO Devices = that missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0xC001FE04", - "UMaskExt": "0xC001FE", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0xCC43FE04", - "UMaskExt": "0xCC43FE", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Clockticks", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0xC88FFD01", - "UMaskExt": "0xC88FFD", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores tha= t hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0xC827FD01", - "UMaskExt": "0xC827FD", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0xC8A7FD01", - "UMaskExt": "0xC8A7FD", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0xC887FD01", - "UMaskExt": "0xC887FD", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0xC88FFE01", - "UMaskExt": "0xC88FFE", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that= missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0xC827FE01", - "UMaskExt": "0xC827FE", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0xC8A7FE01", - "UMaskExt": "0xC8A7FE", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0xC887FE01", - "UMaskExt": "0xC887FE", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores t= hat hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0xC827FD01", - "UMaskExt": "0xC827FD", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0xC8A7FD01", - "UMaskExt": "0xC8A7FD", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores th= at missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0xC827FE01", - "UMaskExt": "0xC827FE", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= Hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0xCC43FD04", - "UMaskExt": "0xCC43FD", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0xCC43FF04", - "UMaskExt": "0xCC43FF", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0xC887FF01", - "UMaskExt": "0xC887FF", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0xC807FF01", - "UMaskExt": "0xC807FF", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0xC827FF01", - "UMaskExt": "0xC827FF", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0xC8A7FF01", - "UMaskExt": "0xC8A7FF", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0xC80FFF01", - "UMaskExt": "0xC80FFF", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0xC807FF01", - "UMaskExt": "0xC807FF", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0xC827FF01", - "UMaskExt": "0xC827FF", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0xC8A7FF01", - "UMaskExt": "0xC8A7FF", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "UMask": "0xC80FFF01", - "UMaskExt": "0xC80FFF", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0xC8C7FF01", - "UMaskExt": "0xC8C7FF", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0xCD43FF04", - "UMaskExt": "0xCD43FF", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0xCD43FD04", - "UMaskExt": "0xCD43FD", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0xCD43FE04", - "UMaskExt": "0xCD43FE", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0xc867fe01", - "UMaskExt": "0xc867fe", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0xc86ffe01", - "UMaskExt": "0xc86ffe", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0xC86FFE01", - "UMaskExt": "0xC86FFE", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0xC87FDE01", - "UMaskExt": "0xC87FDE", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0xC877DE01", - "UMaskExt": "0xC877DE", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0xC8F3FE04", - "UMaskExt": "0xC8F3FE", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0xc8f3fe04", - "UMaskExt": "0xc8f3fe", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0xC8F3FD04", - "UMaskExt": "0xC8F3FD", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0xC8F3FF04", - "UMaskExt": "0xC8F3FF", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0xC8F3FF04", - "UMaskExt": "0xC8F3FF", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0xC867FE01", - "UMaskExt": "0xC867FE", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x1BC1FF", - "UMaskExt": "0x1BC1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the integrated IO (IIO) traffic= controller", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 0"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 1"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "PortMask": "0x02", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 2"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 3"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=3D0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_D= ATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", - "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 0"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 1"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 2"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 3"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", - "FCMask": "0x07", - "Filter": "ch_mask=3D0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DA= TA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC= _IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", - "PerPkg": "1", - "PortMask": "0x01", - "ScaleUnit": "4Bytes", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests PCIe makes of the main die : = All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x04", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "PortMask": "0x20", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x80", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x80", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Free running counter that increments for IIO = clocktick", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "Unit": "IIO" + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x04", + "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken= ", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Take= n : Counts the number of times when the CHA was able to bypass HA pipe on t= he way to iMC. This is a latency optimization for situations when there is= light loadings on the memory subsystem. This can be filtered by when the = bypass was taken and when it was not. : Filter for transactions that succee= ded in taking the intermediate bypass.", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x04", + "BriefDescription": "CHA to iMC Bypass : Not Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the n= umber of times when the CHA was able to bypass HA pipe on the way to iMC. = This is a latency optimization for situations when there is light loadings = on the memory subsystem. This can be filtered by when the bypass was taken= and when it was not. : Filter for transactions that could not take the byp= ass, and issues a read to memory. Note that transactions that did not take = the bypass but did not issue read to memory will not be counted.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x04", + "BriefDescription": "CHA to iMC Bypass : Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "CHA to iMC Bypass : Taken : Counts the numbe= r of times when the CHA was able to bypass HA pipe on the way to iMC. This= is a latency optimization for situations when there is light loadings on t= he memory subsystem. This can be filtered by when the bypass was taken and= when it was not. : Filter for transactions that succeeded in taking the fu= ll bypass.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x04", + "BriefDescription": "Uncore cache clock ticks", + "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x03", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", - "FCMask": "0x04", + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x03", - "Unit": "IIO" + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Mul= tiple Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Mu= ltiple Snoops : Counts the number of transactions that trigger a configurab= le number of cross snoops. Cores are snooped if the transaction looks up t= he cache and determines that it is necessary based on the operation type an= d what CoreValid bits are set. For example, if 2 CV bits are set on a data= read, the cores must have the data in S state so it is not necessary to sn= oop them. However, if only 1 CV bit is set the core my have modified the d= ata. If the transaction was an RFO, it would need to invalidate the lines.= This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf2", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop = : Counts the number of transactions that trigger a configurable number of c= ross snoops. Cores are snooped if the transaction looks up the cache and d= etermines that it is necessary based on the operation type and what CoreVal= id bits are set. For example, if 2 CV bits are set on a data read, the cor= es must have the data in S state so it is not necessary to snoop them. How= ever, if only 1 CV bit is set the core my have modified the data. If the t= ransaction was an RFO, it would need to invalidate the lines. This event c= an be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf1", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requ= ests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x03", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Multiple Core Req= uests : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x42", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Single Core Reques= ts", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Single Core Reque= sts : Counts the number of transactions that trigger a configurable number = of cross snoops. Cores are snooped if the transaction looks up the cache a= nd determines that it is necessary based on the operation type and what Cor= eValid bits are set. For example, if 2 CV bits are set on a data read, the= cores must have the data in S state so it is not necessary to snoop them. = However, if only 1 CV bit is set the core my have modified the data. If t= he transaction was an RFO, it would need to invalidate the lines. This eve= nt can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x41", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 7", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction"= , + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", "PerPkg": "1", - "UMask": "0x80", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction= : Counts the number of transactions that trigger a configurable number of = cross snoops. Cores are snooped if the transaction looks up the cache and = determines that it is necessary based on the operation type and what CoreVa= lid bits are set. For example, if 2 CV bits are set on a data read, the co= res must have the data in S state so it is not necessary to snoop them. Ho= wever, if only 1 CV bit is set the core my have modified the data. If the = transaction was an RFO, it would need to invalidate the lines. This event = can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x82", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 6", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Single Eviction := Counts the number of transactions that trigger a configurable number of cr= oss snoops. Cores are snooped if the transaction looks up the cache and de= termines that it is necessary based on the operation type and what CoreVali= d bits are set. For example, if 2 CV bits are set on a data read, the core= s must have the data in S state so it is not necessary to snoop them. Howe= ver, if only 1 CV bit is set the core my have modified the data. If the tr= ansaction was an RFO, it would need to invalidate the lines. This event ca= n be filtered based on who triggered the initial snoop(s).", + "UMask": "0x81", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 5", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Multiple External = Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Multiple External= Snoops : Counts the number of transactions that trigger a configurable num= ber of cross snoops. Cores are snooped if the transaction looks up the cac= he and determines that it is necessary based on the operation type and what= CoreValid bits are set. For example, if 2 CV bits are set on a data read,= the cores must have the data in S state so it is not necessary to snoop th= em. However, if only 1 CV bit is set the core my have modified the data. = If the transaction was an RFO, it would need to invalidate the lines. This= event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x22", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 4", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", - "FCMask": "0x04", + "BriefDescription": "Core Cross Snoops Issued : Single External Sn= oops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IIO" + "PublicDescription": "Core Cross Snoops Issued : Single External S= noops : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x21", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 3", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", + "BriefDescription": "Counter 0 Occupancy", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IIO" + "PublicDescription": "Counter 0 Occupancy : Since occupancy counts= can only be captured in the Cbo's 0 counter, this event allows a user to c= apture occupancy related information by filtering the Cb0 occupancy count c= aptured in Counter 0. The filtering available is found in the control reg= ister - threshold, invert and edge detect. E.g. setting threshold to 1 ca= n effectively monitor how many cycles the monitored queue has an entry.", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 2", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IIO" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 1", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IIO" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x04", + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", "PerPkg": "1", - "PortMask": "0xff", - "UMask": "0x03", - "Unit": "IIO" + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", "PerPkg": "1", - "UMask": "0xff", - "Unit": "IIO" + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Misc Events - Set 1 : Lost Forward", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.LOST_FWD", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", "PerPkg": "1", "UMask": "0x10", - "Unit": "IRP" + "Unit": "CHA" }, { - "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" + "UMask": "0x20", + "Unit": "CHA" }, { - "BriefDescription": "Coherent Ops : WbMtoI", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0f", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IRP" + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IRP" + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Inbound write (fast path) requests received b= y the IRP", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IRP" + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the IO coherency tracker (IRP)"= , - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", "PerPkg": "1", - "Unit": "IRP" + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "FAF RF full", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_I_FAF_FULL", + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "CHA" }, { - "BriefDescription": "Occupancy of the IRP FAF queue", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", + "UMask": "0x40", + "Unit": "CHA" }, { - "BriefDescription": "FAF allocation -- sent to ADQ", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", + "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", "PerPkg": "1", - "Unit": "IRP" + "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", + "UMask": "0x80", + "Unit": "CHA" }, { - "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", "PerPkg": "1", - "UMask": "0x78", - "Unit": "IRP" + "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", + "UMask": "0x2", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the mesh to memory (M2M)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventName": "UNC_M2M_CLOCKTICKS", + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "CMS Clockticks", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the mesh to PCI (M2P)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_M2P_CLOCKTICKS", + "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", "PerPkg": "1", - "Unit": "M2PCIe" + "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "CMS Clockticks", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc0", - "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", - "Unit": "M2PCIe" + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" }, { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", - "Counter": "FIXED", - "CounterType": "FIXED", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "Unit": "UBOX" + "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Local - All Lines", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x200F", - "UMaskExt": "0x20", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Counter 0 Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1F", - "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Number of times that an RFO hit in S state", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Local INVITOE requests (exclusive ownership o= f a cache line without receiving data) that miss the SF/LLC and remote INVI= TOE requests sent to the CHA's home agent", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE", + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x30", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0xC001FFff", - "UMaskExt": "0xC001FF", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0xC80FFD01", - "UMaskExt": "0xC80FFD", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0xC807FD01", - "UMaskExt": "0xC807FD", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0xc803fe04", - "UMaskExt": "0xc803fe", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0xc803fe04", - "UMaskExt": "0xc803fe", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0xcc43fe04", - "UMaskExt": "0xcc43fe", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Bypass : Taken", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Bypass : Not Taken", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Single External Sn= oops", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", - "UMask": "0x21", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Single Core Reques= ts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", - "UMask": "0x41", + "PublicDescription": "Counts when a normal (Non-Isochronous) read = is issued to any of the memory controller channels from the CHA.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Single Eviction", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", "PerPkg": "1", - "UMask": "0x81", + "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of th= e number of reads issued to any of the memory controller channels. This ca= n be filtered by the priority of the reads.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Lin= e Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", - "UMask": "0xF1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full = line write is issued from the CHA to any of the memory controller channels.= ", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Multiple External = Snoops", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", "PerPkg": "1", - "UMask": "0x22", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH F= ull Line : Counts the total number of full line writes issued from the HA i= nto the memory controller.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requ= ests", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", "PerPkg": "1", - "UMask": "0x42", + "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial= Non-ISOCH : Counts the total number of full line writes issued from the HA= into the memory controller.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", "PerPkg": "1", - "UMask": "0x82", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH P= artial : Counts the total number of full line writes issued from the HA int= o the memory controller.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Mul= tiple Snoops", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL", "PerPkg": "1", - "UMask": "0xF2", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", + "UMask": "0x1fffff", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "BriefDescription": "Cache Lookups : All Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cache Lookups : All Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Any local or remote transaction to the LLC, includi= ng prefetch.", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.CODE_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1bd0ff", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "BriefDescription": "Cache Lookups : Code Reads", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cache Lookups : Code Reads : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", + "UMask": "0x1bd0ff", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "BriefDescription": "Cache Lookups : CRd Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cache Lookups : CRd Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote CRd transactions to the LLC. This = includes CRd prefetch.", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "BriefDescription": "Cache Lookups : Code Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cache Lookups : Code Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", + "UMask": "0x1bd001", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "BriefDescription": "Cache Lookups : Local request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cache Lookups : Local request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Any local transaction to the LLC, including prefe= tches from the Core", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1bc1ff", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1bc1ff", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x1fc1ff", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "BriefDescription": "Cache Lookups : Data Read Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cache Lookups : Data Read Request Filter : C= ounts the number of times the LLC was accessed - this includes code, data, = prefetches and hints coming from L2. This has numerous filters available. = Note the non-standard filtering equation. This event will count requests = that lookup the cache multiple times with multiple increments. One must AL= WAYS select a state or states (in the umask field) to match. Otherwise, th= e event will count nothing. : Read transactions.", "Unit": "CHA" }, { - "BriefDescription": "Direct GO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "BriefDescription": "Cache Lookups : Data Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cache Lookups : Data Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", + "UMask": "0x1bc101", "Unit": "CHA" }, { - "BriefDescription": "HA to iMC Reads Issued : ISOCH", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x841ff", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "BriefDescription": "Cache Lookups : E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.E", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cache Lookups : E State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Exclusive State", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "BriefDescription": "Cache Lookups : F State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.F", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cache Lookups : F State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Forward State", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests"= , + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", + "UMask": "0x1a44ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cache Lookups : Flush or Invalidate Filter := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Lines in M state", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "BriefDescription": "Cache Lookups : I State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.I", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cache Lookups : I State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Miss", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Lines in E state", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "BriefDescription": "Cache Lookups : Transactions homed locally Fi= lter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cache Lookups : Transactions homed locally F= ilter : Counts the number of times the LLC was accessed - this includes cod= e, data, prefetches and hints coming from L2. This has numerous filters av= ailable. Note the non-standard filtering equation. This event will count = requests that lookup the cache multiple times with multiple increments. On= e must ALWAYS select a state or states (in the umask field) to match. Othe= rwise, the event will count nothing. : Transaction whose address resides in= the local MC.", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Lines in S State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "BriefDescription": "Cache Lookups : M State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.M", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cache Lookups : M State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Modified State", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Local Only", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "BriefDescription": "Cache Lookups : All Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", "PerPkg": "1", - "UMaskExt": "0x20", + "PublicDescription": "Cache Lookups : All Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", + "UMask": "0x1fe001", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Local - Lines in M State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "BriefDescription": "Cache Lookups : Write Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", "PerPkg": "1", - "UMask": "0x2001", - "UMaskExt": "0x20", + "PublicDescription": "Cache Lookups : Write Request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Writeback transactions to the LLC This includes = all write transactions -- both Cacheable and UC.", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Local - Lines in E State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "BriefDescription": "Cache Lookups : Reads", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ", "PerPkg": "1", - "UMask": "0x2002", - "UMaskExt": "0x20", + "PublicDescription": "Cache Lookups : Reads : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS select a state= or states (in the umask field) to match. Otherwise, the event will count = nothing.", + "UMask": "0x1bd9ff", "Unit": "CHA" }, { - "BriefDescription": "Lines Victimized : Local - Lines in S State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Locally HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", "PerPkg": "1", - "UMask": "0x2004", - "UMaskExt": "0x20", + "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Locally HOMed : Counts the number of times the LLC was accessed - this= includes code, data, prefetches and hints coming from L2. This has numero= us filters available. Note the non-standard filtering equation. This even= t will count requests that lookup the cache multiple times with multiple in= crements. One must ALWAYS select a state or states (in the umask field) to= match. Otherwise, the event will count nothing.", + "UMask": "0x9d9ff", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc : Silent Snoop Eviction", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Remotely HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Remotely HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", + "UMask": "0x11d9ff", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc : Write Combining Aliasing", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.WC_ALIASING", + "BriefDescription": "Cache Lookups : Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cache Lookups : Read Misses : Counts the num= ber of times the LLC was accessed - this includes code, data, prefetches an= d hints coming from L2. This has numerous filters available. Note the non= -standard filtering equation. This event will count requests that lookup t= he cache multiple times with multiple increments. One must ALWAYS select a= state or states (in the umask field) to match. Otherwise, the event will = count nothing.", + "UMask": "0x1bd901", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : = Counts the number of times the LLC was accessed - this includes code, data,= prefetches and hints coming from L2. This has numerous filters available.= Note the non-standard filtering equation. This event will count requests= that lookup the cache multiple times with multiple increments. One must A= LWAYS select a state or states (in the umask field) to match. Otherwise, t= he event will count nothing.", + "UMask": "0xbd901", "Unit": "CHA" }, { - "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", + "UMask": "0x13d901", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", + "BriefDescription": "Cache Lookups : Remotely requested Read or Sn= oop Misses that are Remotely HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM= ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cache Lookups : Remotely requested Read or S= noop Misses that are Remotely HOMed : Counts the number of times the LLC wa= s accessed - this includes code, data, prefetches and hints coming from L2.= This has numerous filters available. Note the non-standard filtering equ= ation. This event will count requests that lookup the cache multiple times= with multiple increments. One must ALWAYS select a state or states (in th= e umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x161901", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", + "BriefDescription": "Cache Lookups : Remotely Requested Reads that= are Locally HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cache Lookups : Remotely Requested Reads tha= t are Locally HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", + "UMask": "0xa19ff", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", + "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filt= er", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Fil= ter : Counts the number of times the LLC was accessed - this includes code,= data, prefetches and hints coming from L2. This has numerous filters avai= lable. Note the non-standard filtering equation. This event will count re= quests that lookup the cache multiple times with multiple increments. One = must ALWAYS select a state or states (in the umask field) to match. Otherw= ise, the event will count nothing.", + "UMask": "0x1bd90e", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", + "BriefDescription": "Cache Lookups : RFO Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", + "UMask": "0x1bc8ff", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", + "BriefDescription": "Cache Lookups : RFO Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cache Lookups : RFO Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote RFO transactions to the LLC. This = includes RFO prefetch.", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", + "BriefDescription": "Cache Lookups : RFO Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cache Lookups : RFO Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", + "UMask": "0x1bc801", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", "PerPkg": "1", - "UMaskExt": "0x01", + "UMask": "0x888ff", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", + "BriefDescription": "Cache Lookups : S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.S", "PerPkg": "1", - "UMaskExt": "0x02", + "PublicDescription": "Cache Lookups : S State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Shared State", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", + "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", "PerPkg": "1", - "UMaskExt": "0x04", + "PublicDescription": "Cache Lookups : SnoopFilter - E State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Exclusive State", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", + "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", "PerPkg": "1", - "UMaskExt": "0x10", + "PublicDescription": "Cache Lookups : SnoopFilter - H State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit HitMe State", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", + "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", "PerPkg": "1", - "UMaskExt": "0x20", + "PublicDescription": "Cache Lookups : SnoopFilter - S State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Shared State", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", + "BriefDescription": "Cache Lookups : Filters Requests for those th= at write info into the cache", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", "PerPkg": "1", - "UMaskExt": "0x40", + "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", + "UMask": "0x1a42ff", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", "PerPkg": "1", - "UMaskExt": "0x80", + "UMask": "0x842ff", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", + "BriefDescription": "Lines Victimized : All Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", "PerPkg": "1", - "UMaskExt": "0x100", + "PublicDescription": "Lines Victimized : All Lines Victimized : Co= unts the number of lines that were victimized on a fill. This can be filte= red by the state that the line was in.", + "UMask": "0xf", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", + "BriefDescription": "Lines Victimized : Lines in E state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", "PerPkg": "1", - "UMaskExt": "0x200", + "PublicDescription": "Lines Victimized : Lines in E state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", + "BriefDescription": "Lines Victimized : Local - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", "PerPkg": "1", - "UMaskExt": "0x800", + "PublicDescription": "Lines Victimized : Local - All Lines : Count= s the number of lines that were victimized on a fill. This can be filtered= by the state that the line was in.", + "UMask": "0x200f", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", + "BriefDescription": "Lines Victimized : Local - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", "PerPkg": "1", - "UMaskExt": "0x1000", + "PublicDescription": "Lines Victimized : Local - Lines in E State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", + "UMask": "0x2002", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", + "BriefDescription": "Lines Victimized : Local - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", "PerPkg": "1", - "UMaskExt": "0x2000", + "PublicDescription": "Lines Victimized : Local - Lines in M State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", + "UMask": "0x2001", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", + "BriefDescription": "Lines Victimized : Local Only", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", "PerPkg": "1", - "UMaskExt": "0x4000", + "PublicDescription": "Lines Victimized : Local Only : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", + "BriefDescription": "Lines Victimized : Local - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", "PerPkg": "1", - "UMaskExt": "0x8000", + "PublicDescription": "Lines Victimized : Local - Lines in S State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", + "UMask": "0x2004", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", + "BriefDescription": "Lines Victimized : Lines in M state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", "PerPkg": "1", - "UMaskExt": "0x10000", + "PublicDescription": "Lines Victimized : Lines in M state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", + "BriefDescription": "Lines Victimized : Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", "PerPkg": "1", - "UMaskExt": "0x20000", + "PublicDescription": "Lines Victimized : Lines in S State : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", + "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", "PerPkg": "1", - "UMaskExt": "0x40000", + "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous= events in the Cbo.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", + "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", "PerPkg": "1", - "UMaskExt": "0x80000", + "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneo= us events in the Cbo.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", + "BriefDescription": "Number of times that an RFO hit in S state.", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", "PerPkg": "1", - "UMaskExt": "0x100000", + "PublicDescription": "Counts when a RFO (the Read for Ownership is= sued before a write) request hit a cacheline in the S (Shared) state.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", + "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", "PerPkg": "1", - "UMaskExt": "0x200000", + "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellan= eous events in the Cbo. : Counts the number of times when a Snoop hit in FS= E states and triggered a silent eviction. This is useful because this info= rmation is lost in the PRE encodings.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", + "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", "PerPkg": "1", - "UMaskExt": "0x400000", + "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscel= laneous events in the Cbo. : Counts the number of times that a USWC write (= WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followe= d by the USWC write. This occurs when there is WC aliasing.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", "PerPkg": "1", - "UMaskExt": "0x800000", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", "PerPkg": "1", - "UMaskExt": "0x1000000", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", + "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", "PerPkg": "1", - "UMaskExt": "0x2000000", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", + "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", "PerPkg": "1", - "UMaskExt": "0x4000000", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", + "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", "PerPkg": "1", - "UMaskExt": "0x8000000", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", + "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", "PerPkg": "1", - "UMaskExt": "0x10000000", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", "PerPkg": "1", - "UMaskExt": "0x01", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", "PerPkg": "1", - "UMaskExt": "0x02", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", "PerPkg": "1", - "UMaskExt": "0x04", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", "PerPkg": "1", - "UMaskExt": "0x08", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", "PerPkg": "1", - "UMaskExt": "0x10", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", "PerPkg": "1", - "UMaskExt": "0x20", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations : IRQ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations : PRQ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Allocations : PRQ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 0 only.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 1 only.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C or SF Way", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 10 only.", "Unit": "CHA" }, { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 11 only.", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 12 only.", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 13 only.", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 2 only.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 3 only.", + "UMask": "0x8", "Unit": "CHA" }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 4 only.", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 5 only.", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 6 only.", "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 7 only.", "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 8 only.", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 9 only.", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "BriefDescription": "Local INVITOE requests (exclusive ownership o= f a cache line without receiving data) that miss the SF/LLC and remote INVI= TOE requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Counts the total number of requests coming f= rom a unit on this socket for exclusive ownership of a cache line without r= eceiving data (INVITOE) to the CHA.", + "UMask": "0x30", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "BriefDescription": "Local read requests that miss the SF/LLC and = remote read requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Counts read requests made into this CHA. Rea= ds include all read opcodes (including RFO: the Read for Ownership issued b= efore a write) .", + "UMask": "0x3", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "BriefDescription": "Local write requests that miss the SF/LLC and= remote write requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Counts write requests made into the CHA, inc= luding streaming, evictions, HitM (Reads from another core to a Modified ca= cheline), etc.", + "UMask": "0xc", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Rejects - Set 1 : HA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 1 : ANY0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "ISMQ Retries - Set 1 : HA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : ANY0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : HA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : LLC Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : SF Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_CHA_RING_SRC_THRTL", "PerPkg": "1", - "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Count= s number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : Allow Snoop", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected= ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejecte= d : Counts number of allocations per cycle into the specified Ingress queue= .", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IRQ0 Reject counter was true", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C or SF Way", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : L= LC or SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Re= quest", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Re= quest", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : ANY0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : HA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : Victim", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent : Snoops sent for Local Requests"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requ= ests", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoops Sent : Directed snoops for Local Reque= sts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "BriefDescription": "ISMQ Retries - Set 1 : HA", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : RspI", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts = number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : RspS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a request", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : RspIFwd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a response", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : RspSFwd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject AK ring me= ssage", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : Rsp*WB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCB", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCS", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : RspCnflct", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for generat= ing a response", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Snoop Responses Received Local : RspFwd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry= Queue Inserts of Transactions that were already in another Retry Q (sub-ev= ents encode the reason for the next reject) : No BL VN0 credit for generati= ng a writeback", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject IV ring me= ssage", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Misc Snoop Responses Received : MtoI RspIData= M", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry = Queue Inserts of Transactions that were already in another Retry Q (sub-eve= nts encode the reason for the next reject)", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t SF", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "BriefDescription": "Other Retries - Set 1 : ANY0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue I= nserts of Transactions that were already in another Retry Q (sub-events enc= ode the reason for the next reject) : Any condition listed in the Other0 Re= ject counter was true", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "BriefDescription": "Other Retries - Set 1 : HA", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Ins= erts of Transactions that were already in another Retry Q (sub-events encod= e the reason for the next reject)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit SF", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Way conflict with another re= quest that caused the reject", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Q= ueue Inserts of Transactions that were already in another Retry Q (sub-even= ts encode the reason for the next reject)", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "WbPushMtoI : Pushed to LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Address match with an outsta= nding request that was rejected.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "WbPushMtoI : Pushed to Memory", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "BriefDescription": "Other Retries - Set 1 : SF Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Qu= eue Inserts of Transactions that were already in another Retry Q (sub-event= s encode the reason for the next reject) : Requests did not generate Snoop = filter victim", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "BriefDescription": "Other Retries - Set 1 : Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue= Inserts of Transactions that were already in another Retry Q (sub-events e= ncode the reason for the next reject)", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", "PerPkg": "1", - "UMaskExt": "0x01", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", "PerPkg": "1", - "UMaskExt": "0x02", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the PRQ0 Reject counter was true", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", "PerPkg": "1", - "UMaskExt": "0x04", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", "PerPkg": "1", - "UMaskExt": "0x08", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", "PerPkg": "1", - "UMaskExt": "0x10", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", "PerPkg": "1", - "UMaskExt": "0x20", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "XPT Prefetches : Sent (on 0?)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.SENT0", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0= ", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a request", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "XPT Prefetches : Sent (on 1?)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.SENT1", + "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0= ", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a response", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Re= quest", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject AK ring message", "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0= ", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCB", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : I State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.I", + "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0= ", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCS", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : SnoopFilter - S State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0= ", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for generating a response", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : SnoopFilter - E State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0"= , + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0= : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)= : No BL VN0 credit for generating a writeback", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : SnoopFilter - H State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Re= quest", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject IV ring message", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : S State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.S", + "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop = : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)"= , + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : E State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.E", + "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUE= STQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any c= ondition listed in the WBQ0 Reject counter was true", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : M State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.M", + "BriefDescription": "Request Queue Retries - Set 1 : HA", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUEST= Q includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : F State", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.F", + "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way= ", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Wa= y : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Way conflict with another request that caused the reject", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : RFO Requests", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", "PerPkg": "1", - "UMask": "0x1BC8FF", - "UMaskExt": "0x1BC8", + "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim := REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : IRQ - iA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match= ", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Matc= h : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : = REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : = Requests did not generate Snoop filter victim", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : SF/LLC Evictions", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQ= UESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PRQ - IOSF", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : IRQ - Non iA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : PRQ - Non IOSF", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All from Local IO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0xC000FF04", - "UMaskExt": "0xC000FF", + "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All from Local iA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0xC000FF01", - "UMaskExt": "0xC000FF", + "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : All from Local iA and IO", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0xC000FF05", - "UMaskExt": "0xC000FF", + "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Just Hits", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", "PerPkg": "1", - "UMaskExt": "0x01", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Just Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", "PerPkg": "1", - "UMaskExt": "0x02", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.DDR", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.DDR4", + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", "PerPkg": "1", - "UMaskExt": "0x04", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : MMCFG Access", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AK", "PerPkg": "1", - "UMaskExt": "0x20", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Just Local Targets", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", "PerPkg": "1", - "UMaskExt": "0x80", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of= the extended umask field", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", "PerPkg": "1", - "UMaskExt": "0x200", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in = b[29:19] of the extended umask field", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "UMaskExt": "0x400", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Just NearMem", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", "PerPkg": "1", - "UMaskExt": "0x400000", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Just NotNearMem", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.IV", "PerPkg": "1", - "UMaskExt": "0x800000", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Just NonCoherent", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", "PerPkg": "1", - "UMaskExt": "0x1000000", + "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : Just ISOC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "UMaskExt": "0x2000000", + "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : IRQ - iA", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : SF/LLC Evictions", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : PRQ - IOSF", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : IRQ - Non iA", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All from Local IO", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", "PerPkg": "1", - "UMask": "0xC000FF04", - "UMaskExt": "0xC000FF", + "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All from Local iA", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", "PerPkg": "1", - "UMask": "0xC000FF01", - "UMaskExt": "0xC000FF", + "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : All from Local iA and IO", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_CHA_RxR_CRD_STARVED_1", "PerPkg": "1", - "UMask": "0xC000FF05", - "UMaskExt": "0xC000FF", + "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Just Hits", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", "PerPkg": "1", - "UMaskExt": "0x01", + "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Just Misses", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", "PerPkg": "1", - "UMaskExt": "0x02", + "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : MMCFG Access", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", "PerPkg": "1", - "UMaskExt": "0x20", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Just Local Targets", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AK", "PerPkg": "1", - "UMaskExt": "0x80", + "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] = of the extended umask field", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", "PerPkg": "1", - "UMaskExt": "0x200", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode i= n b[29:19] of the extended umask field", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", "PerPkg": "1", - "UMaskExt": "0x400", + "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Just NearMem", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "UMaskExt": "0x400000", + "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Just NotNearMem", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", "PerPkg": "1", - "UMaskExt": "0x800000", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Just NonCoherent", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.IV", "PerPkg": "1", - "UMaskExt": "0x1000000", + "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : Just ISOC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", "PerPkg": "1", - "UMaskExt": "0x2000000", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", + "UMask": "0x10", "Unit": "CHA" }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited"= , + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking exclusive lines in the cores? cache.? Snoop filter capacity= evictions occur when the snoop filter is full and evicts an existing entry= to track a new entry.? Does not count clean evictions such as when a core?= s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking modified lines in the cores? cache.? Snoop filter capacity = evictions occur when the snoop filter is full and evicts an existing entry = to track a new entry.? Does not count clean evictions such as when a core?s= cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Counts snoop filter capacity evictions for e= ntries tracking shared lines in the cores? cache.? Snoop filter capacity ev= ictions occur when the snoop filter is full and evicts an existing entry to= track a new entry.? Does not count clean evictions such as when a core?s c= ache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Snoops Sent : All", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Snoops Sent : All : Counts the number of sno= ops issued by the HA.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requ= ests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Snoops Sent : Broadcast snoops for Local Req= uests : Counts the number of snoops issued by the HA. : Counts the number o= f broadcast snoops issued by the HA responding to local requests", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Snoops Sent : Directed snoops for Local Reque= sts", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Snoops Sent : Directed snoops for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= directed snoops issued by the HA responding to local requests", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Snoops Sent : Snoops sent for Local Requests"= , + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Snoops Sent : Snoops sent for Local Requests= : Counts the number of snoops issued by the HA. : Counts the number of bro= adcast or directed snoops issued by the HA responding to local requests", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Snoop Responses Received Local : RspCnflct := Number of snoop responses received for a Local request : Filters for snoo= ps responses of RspConflict to local CA requests. This is returned when a = snoop finds an existing outstanding transaction in a remote caching agent w= hen it CAMs that caching agent. This triggers conflict resolution hardware= . This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Snoop Responses Received Local : RspFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Snoop Responses Received Local : RspFwd : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspFwd to local CA requests. This snoop response is only poss= ible for RdCur when a snoop HITM/E in a remote caching agent and it directl= y forwards data to a requestor without changing the requestor's cache line = state.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB = : Number of snoop responses received for a Local request : Filters for a s= noop response of Rsp*Fwd*WB to local CA requests. This snoop response is o= nly used in 4s systems. It is used when a snoop HITM's in a remote caching= agent and it directly forwards data to a requestor, and simultaneously ret= urns data to the home to be written back to memory.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Snoop Responses Received Local : RspI", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Snoop Responses Received Local : RspI : Numb= er of snoop responses received for a Local request : Filters for snoops re= sponses of RspI to local CA requests. RspI is returned when the remote cac= he does not have the data, or when the remote cache silently evicts data (s= uch as when an RFO hits non-modified data).", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Snoop Responses Received Local : RspIFwd : N= umber of snoop responses received for a Local request : Filters for snoop = responses of RspIFwd to local CA requests. This is returned when a remote = caching agent forwards data and the requesting agent is able to acquire the= data in E or M states. This is commonly returned with RFO transactions. = It can be either a HitM or a HitFE.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Snoop Responses Received Local : RspS", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Snoop Responses Received Local : RspS : Numb= er of snoop responses received for a Local request : Filters for snoop res= ponses of RspS to local CA requests. RspS is returned when a remote cache = has data but is not forwarding it. It is a way to let the requesting socke= t know that it cannot allocate the data in E state. No data is sent with S= RspS.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Snoop Responses Received Local : RspSFwd : N= umber of snoop responses received for a Local request : Filters for a snoo= p response of RspSFwd to local CA requests. This is returned when a remote= caching agent forwards data but holds on to its currently copy. This is c= ommon for data and code reads that hit in a remote socket in E or F state."= , + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspIWB or RspSWB to local CA requests. This is returned when = a non-RFO request hits in M state. Data and Code Reads can return either R= spIWB or RspSWB depending on how the system has been configured. InvItoE t= ransactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIData= M", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM= ", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit LLC", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit SF", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t LLC", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t SF", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", + "BriefDescription": "TOR Inserts : All", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Inserts : All : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent. Does not include addressless requests such as locks and= interrupts.", + "UMask": "0xc001ffff", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", + "BriefDescription": "TOR Inserts : DDR4 Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Inserts : DDR4 Access : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR4", "PerPkg": "1", - "UMask": "0x01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", + "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts. : TOR allocation occurred as a result of SF/LLC e= victions (came from the ISMQ)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", + "BriefDescription": "TOR Inserts : Just Hits", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : Just Hits : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "TOR Inserts : All requests from iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : All requests from iA Cores : C= ounts the number of entries successfully inserted into the TOR that match q= ualifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", + "UMask": "0xc001ff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores := Counts the number of entries successfully inserted into the TOR that match= qualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", + "UMask": "0xc8c7ff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores"= , + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", + "UMask": "0xc8d7ff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Coun= ts the number of entries successfully inserted into the TOR that match qual= ifications specified by the subevent. Does not include addressless reques= ts such as locks and interrupts.", + "UMask": "0xc80fff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", + "UMask": "0xc88fff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : = Counts the number of entries successfully inserted into the TOR that match = qualifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", + "UMask": "0xc827ff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es : Counts the number of entries successfully inserted into the TOR that m= atch qualifications specified by the subevent. Does not include addressle= ss requests such as locks and interrupts.", + "UMask": "0xc8a7ff01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "TOR Inserts : All requests from iA Cores that= Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Hit the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0xc001fd01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0xc80ffd01", "Unit": "CHA" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat hit the LLC : Counts the number of entries successfully inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", + "UMask": "0xc88ffd01", "Unit": "CHA" }, { - "BriefDescription": "Distress signal asserted : Vertical", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to page walks that hit the LLC : Counts the number of entries successfull= y inserted into the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fd01", "Unit": "CHA" }, { - "BriefDescription": "Distress signal asserted : Horizontal", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores tha= t hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores th= at hit the LLC : Counts the number of entries successfully inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xc827fd01", "Unit": "CHA" }, { - "BriefDescription": "Distress signal asserted : DPT Local", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es that hit the LLC : Counts the number of entries successfully inserted in= to the TOR that match qualifications specified by the subevent. Does not = include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fd01", "Unit": "CHA" }, { - "BriefDescription": "Distress signal asserted : DPT Remote", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that H= it the LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", + "UMask": "0xc807fd01", "Unit": "CHA" }, { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Hit the LLC : Counts the number of entries successfully inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", + "UMask": "0xc887fd01", "Unit": "CHA" }, { - "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", "Unit": "CHA" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBA", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0xc80ffe01", "Unit": "CHA" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBA", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat Missed the LLC : Counts the number of entries successfully inserted int= o the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xc88ffe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk that missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xc837fe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that= missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores tha= t missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc827fe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es that missed the LLC : Counts the number of entries successfully inserted= into the TOR that match qualifications specified by the subevent. Does n= ot include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", + "UMask": "0xc867fe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", + "UMask": "0xc86ffe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0xc807fe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Missed the LLC : Counts the number of entries successfully inserted int= o the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xc887fe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that= Missed LLC : Counts the number of entries successfully inserted into the T= OR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that = Missed the LLC : Counts the number of entries successfully inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that = Missed the LLC : Counts the number of entries successfully inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that M= issed LLC : Counts the number of entries successfully inserted into the TOR= that match qualifications specified by the subevent. Does not include ad= dressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Coun= ts the number of entries successfully inserted into the TOR that match qual= ifications specified by the subevent. Does not include addressless reques= ts such as locks and interrupts.", + "UMask": "0xc807ff01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores := Counts the number of entries successfully inserted into the TOR that match= qualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", + "UMask": "0xc887ff01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", + "UMask": "0xcc3fff01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. = Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", + "UMask": "0xcc37ff01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. = Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", + "UMask": "0xcc2fff01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB9", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. = Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Writ= e Backs) :Counts the number of entries successfully inserted into the TOR = that match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", "Unit": "CHA" }, { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB9", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. = Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", + "UMask": "0xcc67ff01", "Unit": "CHA" }, { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE6", - "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", + "UMask": "0xc86fff01", "Unit": "CHA" }, { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE6", - "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", + "UMask": "0xc867ff01", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "BriefDescription": "TOR Inserts : All requests from IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : All requests from IO Devices := Counts the number of entries successfully inserted into the TOR that match= qualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", + "UMask": "0xc001ff04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices"= , + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "BriefDescription": "TOR Inserts : All requests from IO Devices th= at hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat hit the LLC : Counts the number of entries successfully inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t Hit the LLC : Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that hit the LLC : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", + "UMask": "0xcd43fd04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that hit the LLC : Counts the number of entries successfully inserted into= the TOR that match qualifications specified by the subevent. Does not in= clude addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fd04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= hit the LLC : Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : C= ounts the number of entries successfully inserted into the TOR that match q= ualifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", + "UMask": "0xcc43ff04", "Unit": "CHA" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices : Counts the number of entries succes= sfully inserted into the TOR that match qualifications specified by the sub= event. Does not include addressless requests such as locks and interrupts= .", + "UMask": "0xcd43ff04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "BriefDescription": "TOR Inserts : All requests from IO Devices th= at missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat missed the LLC : Counts the number of entries successfully inserted int= o the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xc001fe04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that missed the LLC : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", + "UMask": "0xcd43fe04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that missed the LLC : Counts the number of entries successfully inserted i= nto the TOR that match qualifications specified by the subevent. Does not= include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= missed the LLC : Counts the number of entries successfully inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices"= , + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", + "UMask": "0xc8f3ff04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Co= unts the number of entries successfully inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", + "UMask": "0xc803ff04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices := Counts the number of entries successfully inserted into the TOR that match= qualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", + "UMask": "0xcc23ff04", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "BriefDescription": "TOR Inserts : IRQ - iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lock= s and interrupts. : From an iA Core", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Sink Starvation on Vertical Ring", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", + "BriefDescription": "TOR Inserts : IRQ - Non iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", "PerPkg": "1", + "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", + "BriefDescription": "TOR Inserts : Just ISOC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ISOC", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : Just ISOC : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", + "BriefDescription": "TOR Inserts : Just Local Targets", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : Just Local Targets : Counts th= e number of entries successfully inserted into the TOR that match qualifica= tions specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "BriefDescription": "TOR Inserts : All from Local iA and IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Inserts : All from Local iA and IO : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts. : All locally initiated requests", + "UMask": "0xc000ff05", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "BriefDescription": "TOR Inserts : All from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Inserts : All from Local iA : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally initiated requests from iA Cores", + "UMask": "0xc000ff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", + "BriefDescription": "TOR Inserts : All from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "TOR Inserts : All from Local IO : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally generated IO traffic", + "UMask": "0xc000ff04", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", + "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of= the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] o= f the extended umask field : Counts the number of entries successfully inse= rted into the TOR that match qualifications specified by the subevent. Do= es not include addressless requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", + "BriefDescription": "TOR Inserts : Just Misses", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Inserts : Just Misses : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AK", + "BriefDescription": "TOR Inserts : MMCFG Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Inserts : MMCFG Access : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", + "BriefDescription": "TOR Inserts : Just NearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Inserts : Just NearMem : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.IV", + "BriefDescription": "TOR Inserts : Just NonCoherent", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "BriefDescription": "TOR Inserts : Just NotNearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests such = as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in = b[29:19] of the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in= b[29:19] of the extended umask field : Counts the number of entries succes= sfully inserted into the TOR that match qualifications specified by the sub= event. Does not include addressless requests such as locks and interrupts= .", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", + "BriefDescription": "TOR Inserts : PRQ - IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent. Does not include addressless requests such as lo= cks and interrupts. : From a PCIe Device", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", + "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the nu= mber of entries successfully inserted into the TOR that match qualification= s specified by the subevent. Does not include addressless requests such a= s locks and interrupts.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", + "BriefDescription": "TOR Occupancy : DDR4 Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", + "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts. : TOR allocation occurred as a = result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", + "BriefDescription": "TOR Occupancy : Just Hits", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", + "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : All requests from iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xc001ff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", + "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores"= , + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc8c7ff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Core= s", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xc8d7ff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : Fo= r each cycle, this event accumulates the number of valid entries in the TOR= that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", + "UMask": "0xc80fff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", + "UMask": "0xc88fff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = : For each cycle, this event accumulates the number of valid entries in the= TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", + "UMask": "0xc827ff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores : For each cycle, this event accumulates the number of valid entries i= n the TOR that match qualifications specified by the subevent. Does not= include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7ff01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AK", + "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Hit the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.IV", + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that hit the LLC : For each cycle, this event accumulates = the number of valid entries in the TOR that match qualifications specified = by the subevent. Does not include addressless requests such as locks an= d interrupts.", + "UMask": "0xc837fd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores t= hat hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = that hit the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that hit the LLC : For each cycle, this event accumulates the number o= f valid entries in the TOR that match qualifications specified by the subev= ent. Does not include addressless requests such as locks and interrupts= .", + "UMask": "0xc8a7fd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fd01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", + "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Missed the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xc88ffe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that missed the LLC : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", + "UMask": "0xc837fe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores th= at missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores t= hat missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that missed the LLC : For each cycle, this event accumulates the numbe= r of valid entries in the TOR that match qualifications specified by the su= bevent. Does not include addressless requests such as locks and interru= pts.", + "UMask": "0xc8a7fe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", + "UMask": "0xc867fe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", + "UMask": "0xc86ffe01", "Unit": "CHA" }, { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Missed the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fe01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xc887fe01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores tha= t Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores th= at Missed LLC : For each cycle, this event accumulates the number of valid = entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that= Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that= Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that = Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that= Missed LLC : For each cycle, this event accumulates the number of valid en= tries in the TOR that match qualifications specified by the subevent. D= oes not include addressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : Fo= r each cycle, this event accumulates the number of valid entries in the TOR= that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", + "UMask": "0xc807ff01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores"= , + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc887ff01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", + "UMask": "0xc86fff01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", + "UMask": "0xc867ff01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "BriefDescription": "TOR Occupancy : All requests from IO Devices"= , + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xc001ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Device= s", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "BriefDescription": "TOR Occupancy : All requests from IO Devices = that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= that hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat Hit the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that hit the LLC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", + "UMask": "0xcd43fd04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that hit the LLC : For each cycle, this event accumulates the number of = valid entries in the TOR that match qualifications specified by the subeven= t. Does not include addressless requests such as locks and interrupts."= , + "UMask": "0xc8f3fd04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at hit the LLC : For each cycle, this event accumulates the number of valid= entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", + "UMask": "0xcc43ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", + "UMask": "0xcd43ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "BriefDescription": "TOR Occupancy : All requests from IO Devices = that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= that missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", + "UMask": "0xc001fe04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", + "UMask": "0xcd43fe04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that missed the LLC : For each cycle, this event accumulates the number = of valid entries in the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupt= s.", + "UMask": "0xc8f3fe04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at missed the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", + "UMask": "0xc8f3ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : = For each cycle, this event accumulates the number of valid entries in the T= OR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", + "UMask": "0xc803ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices"= , + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", + "UMask": "0xcc23ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "BriefDescription": "TOR Occupancy : IRQ - iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts. : From an iA Core", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "BriefDescription": "TOR Occupancy : Just ISOC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "BriefDescription": "TOR Occupancy : Just Local Targets", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "TOR Occupancy : Just Local Targets : For eac= h cycle, this event accumulates the number of valid entries in the TOR that= match qualifications specified by the subevent. Does not include addre= ssless requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "TOR Occupancy : All from Local iA and IO : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts. : All locally initiated= requests", + "UMask": "0xc000ff05", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "BriefDescription": "TOR Occupancy : All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : All from Local iA : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally initiated reques= ts from iA Cores", + "UMask": "0xc000ff01", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "BriefDescription": "TOR Occupancy : All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : All from Local IO : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally generated IO tra= ffic", + "UMask": "0xc000ff04", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] = of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19]= of the extended umask field : For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "BriefDescription": "TOR Occupancy : Just Misses", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : Just Misses : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "BriefDescription": "TOR Occupancy : MMCFG Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "BriefDescription": "TOR Occupancy : Just NearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : Just NearMem : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "BriefDescription": "TOR Occupancy : Just NonCoherent", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : Just NonCoherent : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "BriefDescription": "TOR Occupancy : Just NotNearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : Just NotNearMem : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. Does not include addressl= ess requests such as locks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode i= n b[29:19] of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode = in b[29:19] of the extended umask field : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts. : From a PCIe Device", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cy= cle, this event accumulates the number of valid entries in the TOR that mat= ch qualifications specified by the subevent. Does not include addressle= ss requests such as locks and interrupts.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal ADS Used : BL - All", "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", + "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : IV", "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : IV", "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : IV", "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", + "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : IV", "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", + "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", + "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", "PerPkg": "1", - "UMask": "0x04", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "Vertical IV Ring in Use : Up", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB3", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Vertical IV Ring in Use : Down", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB3", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", + "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", - "Unit": "CHA" - }, - { - "BriefDescription": "Source Throttle", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xae", - "EventName": "UNC_CHA_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe4", - "EventName": "UNC_CHA_RxR_CRD_STARVED_1", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ALL", - "PerPkg": "1", - "UMask": "0x1FFFFF", - "UMaskExt": "0x1FFF", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x1bc1ff", - "UMaskExt": "0x1bc1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : Flush or Invalidate Requests"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x1A44FF", - "UMaskExt": "0x1A44", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.CODE_READ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "BriefDescription": "WbPushMtoI : Pushed to LLC", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", "PerPkg": "1", - "UMask": "0x1bd0ff", - "UMaskExt": "0x1bd0", + "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the numb= er of times when the CHA was received WbPushMtoI : Counts the number of tim= es when the CHA was able to push WbPushMToI to LLC", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "BriefDescription": "WbPushMtoI : Pushed to Memory", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", "PerPkg": "1", - "UMask": "0xC88FFD01", - "UMaskExt": "0xC88FFD", + "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the n= umber of times when the CHA was received WbPushMtoI : Counts the number of = times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to= MEM)", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", "PerPkg": "1", - "UMask": "0xC887FD01", - "UMaskExt": "0xC887FD", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 0 only.", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", "PerPkg": "1", - "UMask": "0xC88FFE01", - "UMaskExt": "0xC88FFE", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 1 only.", + "UMask": "0x2", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", "PerPkg": "1", - "UMask": "0xC8A7FE01", - "UMaskExt": "0xC8A7FE", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 10 only.", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", "PerPkg": "1", - "UMask": "0xC887FE01", - "UMaskExt": "0xC887FE", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 11 only.", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", "PerPkg": "1", - "UMask": "0xC803FD04", - "UMaskExt": "0xC803FD", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 12 only.", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at Hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", "PerPkg": "1", - "UMask": "0xCC43FD04", - "UMaskExt": "0xCC43FD", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 13 only.", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", "PerPkg": "1", - "UMask": "0xC803FD04", - "UMaskExt": "0xC803FD", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 2 only.", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", "PerPkg": "1", - "UMask": "0xC803FF04", - "UMaskExt": "0xC803FF", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 3 only.", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; CRd Pref from local IA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", "PerPkg": "1", - "UMask": "0xC88FFF01", - "UMaskExt": "0xC88FFF", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 4 only.", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", "PerPkg": "1", - "UMask": "0xC803FF04", - "UMaskExt": "0xC803FF", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 5 only.", + "UMask": "0x20", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", "PerPkg": "1", - "UMask": "0xCC43FF04", - "UMaskExt": "0xCC43FF", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 6 only.", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores"= , - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", "PerPkg": "1", - "UMask": "0xC887FF01", - "UMaskExt": "0xC887FF", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 7 only.", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; CRd Pref from local IA", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", "PerPkg": "1", - "UMask": "0xC88FFF01", - "UMaskExt": "0xC88FFF", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 8 only.", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", "PerPkg": "1", - "UMask": "0xC8D7FF01", - "UMaskExt": "0xC8D7FF", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 9 only.", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", "PerPkg": "1", - "UMask": "0xCC23FF04", - "UMaskExt": "0xCC23FF", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x8", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits= ", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", "PerPkg": "1", - "UMask": "0xC8C3FF04", - "UMaskExt": "0xC8C3FF", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x4", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. = Modified Write Backs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", "PerPkg": "1", - "UMask": "0xcc27ff01", - "UMaskExt": "0xcc27ff", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x80", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits= ", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", "PerPkg": "1", - "UMask": "0xc867fe01", - "UMaskExt": "0xc867fe", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x40", "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", + "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT0", "PerPkg": "1", - "UMask": "0xc86ffe01", - "UMaskExt": "0xc86ffe", + "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XP= T prefetches sent", + "UMask": "0x1", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : RFO Request Filter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT1", "PerPkg": "1", - "UMaskExt": "0x08", + "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XP= T prefetches sent", + "UMask": "0x10", "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups : Transactions homed locally Fi= lter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", "PerPkg": "1", - "UMaskExt": "0x800", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : All Request Filter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", "PerPkg": "1", - "UMaskExt": "0x20", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Data Read Request Filter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", "PerPkg": "1", - "UMaskExt": "0x01", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Write Request Filter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", "PerPkg": "1", - "UMaskExt": "0x02", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", "PerPkg": "1", - "UMaskExt": "0x04", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : CRd Request Filter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", "PerPkg": "1", - "UMaskExt": "0x10", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Local request Filter", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", "PerPkg": "1", - "UMaskExt": "0x40", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : All Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", "PerPkg": "1", - "UMask": "0x1fe001", - "UMaskExt": "0x1fe0", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", "PerPkg": "1", - "UMask": "0x1fc1ff", - "UMaskExt": "0x1fc1", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Data Read Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", "PerPkg": "1", - "UMask": "0x1bc101", - "UMaskExt": "0x1bc1", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", "PerPkg": "1", - "UMask": "0x841ff", - "UMaskExt": "0x841", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", "PerPkg": "1", - "UMask": "0x842ff", - "UMaskExt": "0x842", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.RFO_LOCAL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", "PerPkg": "1", - "UMask": "0x888ff", - "UMaskExt": "0x888", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", "PerPkg": "1", - "UMask": "0xC867FF01", - "UMaskExt": "0xC867FF", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", "PerPkg": "1", - "UMask": "0xC86FFF01", - "UMaskExt": "0xC86FFF", - "Unit": "CHA" + "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DDR4 Access", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic= controller", + "EventCode": "0x01", + "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", - "UMaskExt": "0x04", - "Unit": "CHA" + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : DDR4 Access", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "BriefDescription": "Free running counter that increments for IIO = clocktick", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", - "UMaskExt": "0x04", - "Unit": "CHA" + "PublicDescription": "Free running counter that increments for int= egrated IO (IIO) traffic controller clockticks", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC8F3FD04", - "UMaskExt": "0xC8F3FD", - "Unit": "CHA" + "PortMask": "0xFF", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that= Missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC867FE01", - "UMaskExt": "0xC867FE", - "Unit": "CHA" + "PortMask": "0xff", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 0-7", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that= Missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC86FFE01", - "UMaskExt": "0xC86FFE", - "Unit": "CHA" + "PortMask": "0x01", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores"= , - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC8C7FF01", - "UMaskExt": "0xC8C7FF", - "Unit": "CHA" + "PortMask": "0x02", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Core= s", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC8D7FF01", - "UMaskExt": "0xC8D7FF", - "Unit": "CHA" + "PortMask": "0x04", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xCC27FF01", - "UMaskExt": "0xCC27FF", - "Unit": "CHA" + "PortMask": "0x08", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores tha= t Missed LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC877DE01", - "UMaskExt": "0xC877DE", - "Unit": "CHA" + "PortMask": "0x10", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that = Missed LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC87FDE01", - "UMaskExt": "0xC87FDE", - "Unit": "CHA" + "PortMask": "0x20", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC867FF01", - "UMaskExt": "0xC867FF", - "Unit": "CHA" + "PortMask": "0x40", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC86FFF01", - "UMaskExt": "0xC86FFF", - "Unit": "CHA" + "PortMask": "0x80", + "PublicDescription": "PCIe Completion Buffer Inserts of completion= s with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plug= ged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x3", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices"= , - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xCC23FF04", - "UMaskExt": "0xCC23FF", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7"= , + "UMask": "0xff", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Device= s", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC8C3FF04", - "UMaskExt": "0xC8C3FF", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7"= , + "UMask": "0xff", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xCD43FF04", - "UMaskExt": "0xCD43FF", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 1", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xCD43FD04", - "UMaskExt": "0xCD43FD", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 2", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xCD43FE04", - "UMaskExt": "0xCD43FE", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 3", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xcc3fff01", - "UMaskExt": "0xcc3fff", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Missed the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 4", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC837FE01", - "UMaskExt": "0xC837FE", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Hit the LLC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 5", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC837FD01", - "UMaskExt": "0xC837FD", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 6", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xC837FF01", - "UMaskExt": "0xC837FF", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. = Non Modified Write Backs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 7", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "FCMask": "0x04", "PerPkg": "1", - "UMask": "0xcc67ff01", - "UMaskExt": "0xcc67ff", - "Unit": "CHA" + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : = x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or = x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. = Non Modified Write Backs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xcc37ff01", - "UMaskExt": "0xcc37ff", - "Unit": "CHA" + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. = Non Modified Write Backs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xcc2fff01", - "UMaskExt": "0xcc2fff", - "Unit": "CHA" + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC837FF01", - "UMaskExt": "0xC837FF", - "Unit": "CHA" + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1= , Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that hit the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC837FD01", - "UMaskExt": "0xC837FD", - "Unit": "CHA" + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that missed the LLC", - "CounterType": "PGMABLE", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xC837FE01", - "UMaskExt": "0xC837FE", - "Unit": "CHA" + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Code Read Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x1BD001", - "UMaskExt": "0x1BD0", - "Unit": "CHA" + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : RFO Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x1BC801", - "UMaskExt": "0x1BC8", - "Unit": "CHA" + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5= , Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Reads", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x1BD9FF", - "UMaskExt": "0x1BD9", - "Unit": "CHA" + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Read Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x1BD901", - "UMaskExt": "0x1BD9", - "Unit": "CHA" + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x0BD901", - "UMaskExt": "0x0BD9", - "Unit": "CHA" + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. = Includes all requests initiated by the main die, including reads and write= s. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x13D901", - "UMaskExt": "0x13D9", - "Unit": "CHA" + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Locally HOMed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x09D9FF", - "UMaskExt": "0x09D9", - "Unit": "CHA" + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Remotely Requested Reads that= are Locally HOMed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x0A19FF", - "UMaskExt": "0x0A19", - "Unit": "CHA" + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, = Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Remotely HOMed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x11D9FF", - "UMaskExt": "0x11D9", - "Unit": "CHA" + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filt= er", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x1BD90E", - "UMaskExt": "0x1BD9", - "Unit": "CHA" + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Remotely requested Read or Sn= oop Misses that are Remotely HOMed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM= ", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x161901", - "UMaskExt": "0x1619", - "Unit": "CHA" + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Filters Requests for those th= at write info into the cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x1A42FF", - "UMaskExt": "0x1A42", - "Unit": "CHA" + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, = Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Cache Lookups : Code Reads", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x1BD0FF", - "UMaskExt": "0x1BD0", - "Unit": "CHA" + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x02", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x02", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. I= ncludes all requests initiated by the main die, including reads and writes.= : x4 card is plugged in to slot 7", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x02", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := IOMMU - Type 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x02", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := IOMMU - Type 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or= x4 card is plugged in to slot 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or= x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x08", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 5", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x02", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x02", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reading fro= m Card's IO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 7", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x02", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : I= OMMU - Type 0", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x02", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : I= OMMU - Type 1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x= 4 card is plugged in to slot 0", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 4 card is plugged in to slot 1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 4 card is plugged in to slot 3", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x= 4 card is plugged in to slot 4", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 4 card is plugged in to slot 5", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "UMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "UMask": "0x02", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x08", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's IO space : Number of DWs (4 bytes) requested by the main die. Inclu= des all requests initiated by the main die, including reads and writes. : x= 4 card is plugged in to slot 7", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x08", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : IOMMU - Type 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x08", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : IOMMU - Type 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugge= d in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged = in to slot 2", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugge= d in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged = in to slot 6", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "UMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting c= ompletion of Card read from Core DRAM : Number of DWs (4 bytes) requested b= y the main die. Includes all requests initiated by the main die, including= reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x20", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := IOMMU - Type 0", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x20", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := IOMMU - Type 1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x20", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or= x4 card is plugged in to slot 0", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x20", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 3", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x20", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or= x4 card is plugged in to slot 4", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x20", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 5", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to = Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Inc= ludes all requests initiated by the main die, including reads and writes. := x4 card is plugged in to slot 7", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : IOMMU - Type 0", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : IOMMU - Type 1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card p= lugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x40", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plu= gged in to slot 2", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x40", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x80", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card p= lugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x80", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x80", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plu= gged in to slot 6", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x80", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) reading from this card. : Number of DWs (4 bytes) reques= ted by the main die. Includes all requests initiated by the main die, incl= uding reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : IOMMU - Type 0", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : IOMMU - Type 1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x80", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plu= gged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x80", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x02", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugg= ed in to slot 2", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x02", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x02", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plu= gged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x02", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x08", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugg= ed in to slot 6", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x08", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Another card (di= fferent IIO stack) writing to this card. : Number of DWs (4 bytes) requeste= d by the main die. Includes all requests initiated by the main die, includ= ing reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x08", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : IOMMU - Type 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x08", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : IOMMU - Type 1", + "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1,= Or x4 card is plugged in to slot 0", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x4 card is plugged in to slot 1", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x4 card is plugged in to slot 3", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5,= Or x4 card is plugged in to slot 4", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x4 card is plugged in to slot 5", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Atomic requests = targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.= Includes all requests initiated by the Card, including reads and writes= . : x4 card is plugged in to slot 7", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : IOMMU - Type 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : IOMMU - Type 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugge= d in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged = in to slot 2", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x40", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugge= d in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB lookups first", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB lookups all", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", - "PerPkg": "1", - "UMask": "0x02", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 4K Page", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.4K_HITS", - "PerPkg": "1", - "UMask": "0x04", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 2M Page", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.2M_HITS", - "PerPkg": "1", - "UMask": "0x08", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 1G Page", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.1G_HITS", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.MISSES", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache lookups", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache hits", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": PageWalk cache lookup", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOMMU memory access", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": Cycles PWT full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", - "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 5", "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": ": Interrupt Entry cache lookup", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": Interrupt Entry cache hit", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged = in to slot 6", "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : CmpD - device se= nding completion to CPU request : Number of DWs (4 bytes) the card requests= of the main die. Includes all requests initiated by the Card, including= reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus : PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : IOMM= U - Type 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : IOMM= U - Type 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x16 = card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 c= ard is plugged in to slot 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 1"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 2"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x8 c= ard plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "BriefDescription": "PCI Express bandwidth reading at IIO, part 3"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 3", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus : PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x16 = card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 c= ard is plugged in to slot 4", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d !(PCIE bus)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 5", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x8 c= ard plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and PCIE bus", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card reading fro= m DRAM : Number of DWs (4 bytes) the card requests of the main die. Incl= udes all requests initiated by the Card, including reads and writes. : x4 c= ard is plugged in to slot 7", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and !(PCIE bus)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : IOMMU = - Type 0", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number requests PCIe makes of the main die : = Drop request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x02", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : IOMMU = - Type 1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x16 ca= rd plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 car= d is plugged in to slot 0", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 1"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 2"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x8 car= d plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "BriefDescription": "PCI Express bandwidth writing at IIO, part 3"= , + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 3", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x16 ca= rd plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 car= d is plugged in to slot 4", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 5", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x8 car= d plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "UMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to = DRAM : Number of DWs (4 bytes) the card requests of the main die. Includ= es all requests initiated by the Card, including reads and writes. : x4 car= d is plugged in to slot 7", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x16 card plugged i= n to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged= in to slot 0", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x4 card is plugged= in to slot 1", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x8 card plugged in= to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x4 card is plugged= in to slot 3", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x16 card plugged i= n to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged= in to slot 4", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x4 card is plugged= in to slot 5", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x8 card plugged in= to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "UMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Numbe= r of DWs (4 bytes) the card requests of the main die. Includes all reque= sts initiated by the Card, including reads and writes. : x4 card is plugged= in to slot 7", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 ca= rd plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is= plugged in to slot 2", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 ca= rd plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is= plugged in to slot 6", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "UMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading fro= m another Card (same or different stack) : Number of DWs (4 bytes) the card= requests of the main die. Includes all requests initiated by the Card, = including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card= plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is p= lugged in to slot 2", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card= plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is p= lugged in to slot 6", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "UMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to = another Card (same or different stack) : Number of DWs (4 bytes) the card r= equests of the main die. Includes all requests initiated by the Card, in= cluding reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "BriefDescription": "Incoming arbitration requests : Passing data = to be written", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Passing data= to be written : How often different queues (e.g. channel / fc) ask to send= request into pipeline : Only for posted requests", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "BriefDescription": "Incoming arbitration requests : Issuing final= read or write of line", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Issuing fina= l read or write of line : How often different queues (e.g. channel / fc) as= k to send request into pipeline", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "BriefDescription": "Incoming arbitration requests : Processing re= sponse from IOMMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Processing r= esponse from IOMMU : How often different queues (e.g. channel / fc) ask to = send request into pipeline", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "BriefDescription": "Incoming arbitration requests : Issuing to IO= MMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Issuing to I= OMMU : How often different queues (e.g. channel / fc) ask to send request i= nto pipeline", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", + "BriefDescription": "Incoming arbitration requests : Request Owner= ship", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Request Owne= rship : How often different queues (e.g. channel / fc) ask to send request = into pipeline : Only for posted requests", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", + "BriefDescription": "Incoming arbitration requests : Writing line"= , + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Writing line= : How often different queues (e.g. channel / fc) ask to send request into = pipeline : Only for posted requests", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", + "BriefDescription": "Incoming arbitration requests granted : Passi= ng data to be written", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Pass= ing data to be written : How often different queues (e.g. channel / fc) are= allowed to send request into pipeline : Only for posted requests", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", + "BriefDescription": "Incoming arbitration requests granted : Issui= ng final read or write of line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Issu= ing final read or write of line : How often different queues (e.g. channel = / fc) are allowed to send request into pipeline", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "BriefDescription": "Incoming arbitration requests granted : Proce= ssing response from IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x80", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Proc= essing response from IOMMU : How often different queues (e.g. channel / fc)= are allowed to send request into pipeline", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "BriefDescription": "Incoming arbitration requests granted : Issui= ng to IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x80", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Issu= ing to IOMMU : How often different queues (e.g. channel / fc) are allowed t= o send request into pipeline", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "BriefDescription": "Incoming arbitration requests granted : Reque= st Ownership", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x80", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Requ= est Ownership : How often different queues (e.g. channel / fc) are allowed = to send request into pipeline : Only for posted requests", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "BriefDescription": "Incoming arbitration requests granted : Writi= ng line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x80", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Writ= ing line : How often different queues (e.g. channel / fc) are allowed to se= nd request into pipeline : Only for posted requests", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", - "FCMask": "0x07", + "BriefDescription": ": IOTLB Hits to a 1G Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.1G_HITS", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", + "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a tran= saction to a 1G page, on its first lookup, hits the IOTLB.", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", - "FCMask": "0x07", + "BriefDescription": ": IOTLB Hits to a 2M Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a tran= saction to a 2M page, on its first lookup, hits the IOTLB.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 4K Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a tran= saction to a 4K page, on its first lookup, hits the IOTLB.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups all", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": IOTLB lookups all : Some transactions have= to look up IOTLB multiple times. Counts every time a request looks up IOT= LB.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache hits", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", "PerPkg": "1", - "PortMask": "0x20", + "PublicDescription": ": Context cache hits : Counts each time a fi= rst look up of the transaction hits the RCC.", "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", - "FCMask": "0x07", + "BriefDescription": ": Context cache lookups", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x80", + "PublicDescription": ": Context cache lookups : Counts each time a= transaction looks up root context cache.", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", - "FCMask": "0x07", + "BriefDescription": ": IOTLB lookups first", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x80", + "PublicDescription": ": IOTLB lookups first : Some transactions ha= ve to look up IOTLB multiple times. Counts the first time a request looks = up IOTLB.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", + "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.MISSES", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x02", + "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a = transaction misses IOTLB, it does a page walk to look up memory and bring i= n the relevant page translation. Counts when this page translation is writt= en to IOTLB.", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", + "BriefDescription": ": Cycles PWT full", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x02", + "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU = has reached its maximum limit for outstanding page walks.", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", + "BriefDescription": ": IOMMU memory access", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x02", + "PublicDescription": ": IOMMU memory access : IOMMU sends out memo= ry fetches when it misses the cache look up which is indicated by this sign= al. M2IOSF only uses low priority channel", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", + "BriefDescription": ": PWC Hit to a 1G page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x02", + "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", + "BriefDescription": ": PWC Hit to a 2M page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x02", + "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", + "BriefDescription": ": PWC Hit to a 4K page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x02", + "PublicDescription": ": PWC Hit to a 4K page : Counts each time a = transaction's first look up hits the SLPWC at the 4K level", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", + "BriefDescription": ": PWT Hit to a 256T page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x02", + "PublicDescription": ": PWT Hit to a 256T page : Counts each time = a transaction's first look up hits the SLPWC at the 512G level", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", + "BriefDescription": ": PageWalk cache fill", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x02", + "PublicDescription": ": PageWalk cache fill : When a transaction m= isses SLPWC, it does a page walk to look up memory and bring in the relevan= t page translation. When this page translation is written to SLPWC, ObsPwcF= illValid_nnnH is asserted.", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", + "BriefDescription": ": PageWalk cache lookup", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x08", + "PublicDescription": ": PageWalk cache lookup : Counts each time a= transaction looks up second level page walk cache.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", + "BriefDescription": ": Interrupt Entry cache hit", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x08", + "PublicDescription": ": Interrupt Entry cache hit : Counts each ti= me a transaction's first look up hits the IEC.", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", + "BriefDescription": ": Interrupt Entry cache lookup", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x08", + "PublicDescription": ": Interrupt Entry cache lookup : Counts the = number of transaction looks up that interrupt remapping cache.", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", + "BriefDescription": ": Device-selective Context cache invalidation= cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x08", + "PublicDescription": ": Device-selective Context cache invalidatio= n cycles : Counts number of Device selective context cache invalidation eve= nts", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", - "FCMask": "0x07", + "BriefDescription": ": Domain-selective Context cache invalidation= cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x08", + "PublicDescription": ": Domain-selective Context cache invalidatio= n cycles : Counts number of Domain selective context cache invalidation eve= nts", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", - "FCMask": "0x07", + "BriefDescription": ": Context cache global invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x08", + "PublicDescription": ": Context cache global invalidation cycles := Counts number of Context Cache global invalidation events", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", - "FCMask": "0x07", + "BriefDescription": ": Domain-selective IOTLB invalidation cycles"= , + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x08", + "PublicDescription": ": Domain-selective IOTLB invalidation cycles= : Counts number of Domain selective invalidation events", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", - "FCMask": "0x07", + "BriefDescription": ": Global IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x08", + "PublicDescription": ": Global IOTLB invalidation cycles : Indicat= es that IOMMU is doing global invalidation.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", + "BriefDescription": ": Page-selective IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x10", + "PublicDescription": ": Page-selective IOTLB invalidation cycles := Counts number of Page-selective within Domain Invalidation events", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x10", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = : Asserted if all bits specified by mask match", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x10", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x10", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", - "FCMask": "0x07", + "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", + "PublicDescription": "AND Mask/match for debug bus : PCIE bus : As= serted if all bits specified by mask match", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", - "FCMask": "0x07", + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", "PerPkg": "1", - "PortMask": "0x20", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and PCIE bus : Asserted if all bits specified by mask match", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", - "FCMask": "0x07", + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x10", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", - "FCMask": "0x07", + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x10", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus := Asserted if any bits specified by mask match", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x40", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x40", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", + "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x40", + "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Ass= erted if any bits specified by mask match", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x40", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", - "FCMask": "0x07", + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", - "FCMask": "0x07", + "BriefDescription": "Counting disabled", + "EventCode": "0x80", + "EventName": "UNC_IIO_NOTHING", "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "BriefDescription": "Occupancy of outbound request queue : To devi= ce", + "EventCode": "0xC5", + "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x40", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "Occupancy of outbound request queue : To dev= ice : Counts number of outbound requests/completions IIO is currently proce= ssing", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "BriefDescription": ": Passing data to be written", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x80", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": ": Passing data to be written : Only for post= ed requests", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "BriefDescription": ": Issuing final read or write of line", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x01", + "PortMask": "0xFF", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "BriefDescription": ": Processing response from IOMMU", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x01", + "PortMask": "0xFF", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "BriefDescription": ": Issuing to IOMMU", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x02", + "PortMask": "0xFF", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", + "BriefDescription": ": Request Ownership", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x02", + "PortMask": "0xFF", + "PublicDescription": ": Request Ownership : Only for posted reques= ts", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", + "BriefDescription": ": Writing line", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x04", + "PortMask": "0xFF", + "PublicDescription": ": Writing line : Only for posted requests", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", + "BriefDescription": "Number requests sent to PCIe from main die : = >From IRP", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x04", + "PortMask": "0xFF", + "PublicDescription": "Number requests sent to PCIe from main die := From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either no= n-confined P2P traffic or from the CPU", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", + "BriefDescription": "Number requests sent to PCIe from main die : = >From ITC", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x08", + "PortMask": "0xFF", + "PublicDescription": "Number requests sent to PCIe from main die := From ITC : Confined P2P", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", + "BriefDescription": "Number requests sent to PCIe from main die : = Completion allocations", + "EventCode": "0xc2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x08", + "PortMask": "0xFF", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "BriefDescription": "Number requests PCIe makes of the main die : = Drop request", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x10", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die := Drop request : Counts full PCIe requests before they're broken into a seri= es of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_O= F_CPU. : Packet error detected, must be dropped", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "BriefDescription": "Number requests PCIe makes of the main die : = All", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x10", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die := All : Counts full PCIe requests before they're broken into a series of cac= he-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", + "BriefDescription": "Num requests sent by PCIe - by target : Abort= ", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x20", + "PortMask": "0xFF", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", + "BriefDescription": "Num requests sent by PCIe - by target : Confi= ned P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x20", + "PortMask": "0xFF", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "BriefDescription": "Num requests sent by PCIe - by target : Local= P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x40", + "PortMask": "0xFF", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "BriefDescription": "Num requests sent by PCIe - by target : Multi= -cast", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x40", + "PortMask": "0xFF", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", + "BriefDescription": "Num requests sent by PCIe - by target : Memor= y", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x80", + "PortMask": "0xFF", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", + "BriefDescription": "Num requests sent by PCIe - by target : MsgB"= , + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x80", + "PortMask": "0xFF", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "BriefDescription": "Num requests sent by PCIe - by target : Remot= e P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x01", + "PortMask": "0xFF", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "BriefDescription": "Num requests sent by PCIe - by target : Ubox"= , + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x01", + "PortMask": "0xFF", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", + "BriefDescription": "ITC address map 1", + "EventCode": "0x8F", + "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x02", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "BriefDescription": "Outbound cacheline requests issued : 64B requ= ests issued to device", + "EventCode": "0xD0", + "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x02", + "PortMask": "0xFF", + "PublicDescription": "Outbound cacheline requests issued : 64B req= uests issued to device : Each outbound cacheline granular request may need = to make multiple passes through the pipeline. Each time a cacheline comple= tes all its passes it advances line", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "BriefDescription": "Outbound TLP (transaction layer packet) reque= sts issued : To device", + "EventCode": "0xD1", + "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x04", + "PortMask": "0xFF", + "PublicDescription": "Outbound TLP (transaction layer packet) requ= ests issued : To device : Each time an outbound completes all its passes it= advances the pointer", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", + "BriefDescription": "PWT occupancy", + "EventCode": "0x42", + "EventName": "UNC_IIO_PWT_OCCUPANCY", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x04", + "PublicDescription": "PWT occupancy : Indicates how many page walk= s are outstanding at any point in time.", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "BriefDescription": "PCIe Request - cacheline complete : Passing d= ata to be written", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x08", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Passing = data to be written : Each PCIe request is broken down into a series of cach= eline granular requests and each cacheline size request may need to make mu= ltiple passes through the pipeline (e.g. for posted interrupts or multi-cas= t). Each time a cacheline completes all its passes (e.g. finishes posting= writes to all multi-cast targets) it advances line : Only for posted reque= sts", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "BriefDescription": "PCIe Request - cacheline complete : Issuing f= inal read or write of line", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x08", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Issuing = final read or write of line : Each PCIe request is broken down into a serie= s of cacheline granular requests and each cacheline size request may need t= o make multiple passes through the pipeline (e.g. for posted interrupts or = multi-cast). Each time a cacheline completes all its passes (e.g. finishe= s posting writes to all multi-cast targets) it advances line", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", + "BriefDescription": "PCIe Request - cacheline complete : Request O= wnership", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x10", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Request = Ownership : Each PCIe request is broken down into a series of cacheline gra= nular requests and each cacheline size request may need to make multiple pa= sses through the pipeline (e.g. for posted interrupts or multi-cast). Eac= h time a cacheline completes all its passes (e.g. finishes posting writes t= o all multi-cast targets) it advances line : Only for posted requests", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", + "BriefDescription": "PCIe Request - cacheline complete : Writing l= ine", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Writing = line : Each PCIe request is broken down into a series of cacheline granular= requests and each cacheline size request may need to make multiple passes = through the pipeline (e.g. for posted interrupts or multi-cast). Each tim= e a cacheline completes all its passes (e.g. finishes posting writes to all= multi-cast targets) it advances line : Only for posted requests", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "BriefDescription": "PCIe Request complete : Passing data to be wr= itten", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Passing data to be w= ritten : Each PCIe request is broken down into a series of cacheline granul= ar requests and each cacheline size request may need to make multiple passe= s through the pipeline (e.g. for posted interrupts or multi-cast). Each t= ime a single PCIe request completes all its cacheline granular requests, it= advances pointer. : Only for posted requests", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Messages", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "BriefDescription": "PCIe Request complete : Issuing final read or= write of line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x40", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Issuing final read o= r write of line : Each PCIe request is broken down into a series of cacheli= ne granular requests and each cacheline size request may need to make multi= ple passes through the pipeline (e.g. for posted interrupts or multi-cast).= Each time a single PCIe request completes all its cacheline granular req= uests, it advances pointer.", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", + "BriefDescription": "PCIe Request complete : Processing response f= rom IOMMU", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x80", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Processing response = from IOMMU : Each PCIe request is broken down into a series of cacheline gr= anular requests and each cacheline size request may need to make multiple p= asses through the pipeline (e.g. for posted interrupts or multi-cast). Ea= ch time a single PCIe request completes all its cacheline granular requests= , it advances pointer.", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", + "BriefDescription": "PCIe Request complete : Issuing to IOMMU", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x80", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Issuing to IOMMU : E= ach PCIe request is broken down into a series of cacheline granular request= s and each cacheline size request may need to make multiple passes through = the pipeline (e.g. for posted interrupts or multi-cast). Each time a sing= le PCIe request completes all its cacheline granular requests, it advances = pointer.", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "BriefDescription": "PCIe Request complete : Request Ownership", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x01", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Request Ownership : = Each PCIe request is broken down into a series of cacheline granular reques= ts and each cacheline size request may need to make multiple passes through= the pipeline (e.g. for posted interrupts or multi-cast). Each time a sin= gle PCIe request completes all its cacheline granular requests, it advances= pointer. : Only for posted requests", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "BriefDescription": "PCIe Request complete : Writing line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x01", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Writing line : Each = PCIe request is broken down into a series of cacheline granular requests an= d each cacheline size request may need to make multiple passes through the = pipeline (e.g. for posted interrupts or multi-cast). Each time a single P= CIe request completes all its cacheline granular requests, it advances poin= ter. : Only for posted requests", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "BriefDescription": "PCIe Request - pass complete : Passing data t= o be written", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x02", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Passing data = to be written : Each PCIe request is broken down into a series of cacheline= granular requests and each cacheline size request may need to make multipl= e passes through the pipeline (e.g. for posted interrupts or multi-cast). = Each time a cacheline completes a single pass (e.g. posts a write to singl= e multi-cast target) it advances state : Only for posted requests", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "BriefDescription": "PCIe Request - pass complete : Issuing final = read or write of line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x04", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Issuing final= read or write of line : Each PCIe request is broken down into a series of = cacheline granular requests and each cacheline size request may need to mak= e multiple passes through the pipeline (e.g. for posted interrupts or multi= -cast). Each time a cacheline completes a single pass (e.g. posts a write= to single multi-cast target) it advances state", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "BriefDescription": "PCIe Request - pass complete : Request Owners= hip", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x04", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Request Owner= ship : Each PCIe request is broken down into a series of cacheline granular= requests and each cacheline size request may need to make multiple passes = through the pipeline (e.g. for posted interrupts or multi-cast). Each tim= e a cacheline completes a single pass (e.g. posts a write to single multi-c= ast target) it advances state : Only for posted requests", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "BriefDescription": "PCIe Request - pass complete : Writing line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x08", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Writing line = : Each PCIe request is broken down into a series of cacheline granular requ= ests and each cacheline size request may need to make multiple passes throu= gh the pipeline (e.g. for posted interrupts or multi-cast). Each time a c= acheline completes a single pass (e.g. posts a write to single multi-cast t= arget) it advances state : Only for posted requests", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", + "BriefDescription": "Symbol Times on Link", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x08", + "PublicDescription": "Symbol Times on Link : Gen1 - increment once= every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1n= S", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", - "UMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : IOMMU - Ty= pe 0", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", - "UMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : IOMMU - Ty= pe 1", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x20", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x16 card p= lugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is= plugged in to slot 0", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x20", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x4 card is= plugged in to slot 1", + "UMask": "0x40", "Unit": "IIO" }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x8 card pl= ugged in to Lane 2/3, Or x4 card is plugged in to slot 2", "UMask": "0x40", "Unit": "IIO" }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x4 card is= plugged in to slot 3", "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x80", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x16 card p= lugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is= plugged in to slot 4", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x80", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x4 card is= plugged in to slot 5", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x01", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x8 card pl= ugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x01", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's PCICFG space : Also known as Outbound. Number of r= equests initiated by the main die, including reads and writes. : x4 card is= plugged in to slot 7", + "UMask": "0x40", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", - "UMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : IOMMU - Type= 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", - "UMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : IOMMU - Type= 1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x04", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x16 card plu= gged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is p= lugged in to slot 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x04", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x08", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x8 card plug= ged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x08", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 3", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x16 card plu= gged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is p= lugged in to slot 4", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 5", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x100", - "UMask": "0x40", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x8 card plug= ged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0x200", - "UMask": "0x40", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's PCICFG space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 7", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : IOMMU - Type 0= ", "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : IOMMU - Type 1= ", "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Counting disabled", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_IIO_NOTHING", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x16 card plugg= ed in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plu= gged in to slot 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "PWT occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_IIO_PWT_OCCUPANCY", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Symbol Times on Link", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_IIO_SYMBOL_TIMES", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x8 card plugge= d in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "1", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 3", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "2", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x16 card plugg= ed in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plu= gged in to slot 4", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "3", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 5", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "4", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x8 card plugge= d in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "5", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's IO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 7", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "6", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "7", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "8", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x16 card plugged= in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugg= ed in to slot 0", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "9", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x4 card is plugg= ed in to slot 1", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "13", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x8 card plugged = in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "12", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x4 card is plugg= ed in to slot 3", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "11", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x16 card plugged= in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugg= ed in to slot 4", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "10", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x4 card is plugg= ed in to slot 5", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "15", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x8 card plugged = in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "14", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's IO space : Also known as Outbound. Number of request= s initiated by the main die, including reads and writes. : x4 card is plugg= ed in to slot 7", + "UMask": "0x20", "Unit": "IIO" }, { - "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", - "Counter": "16", - "CounterType": "FREERUN", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : IOMMU - Type= 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": PWC Hit to a 4K page", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : IOMMU - Type= 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": PWC Hit to a 2M page", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x16 card plu= gged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is p= lugged in to slot 0", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": PWC Hit to a 1G page", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 1", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": PWT Hit to a 256T page", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x8 card plug= ged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": PageWalk cache fill", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 3", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": Global IOTLB invalidation cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x16 card plu= gged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is p= lugged in to slot 4", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": Domain-selective IOTLB invalidation cycles"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 5", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": Page-selective IOTLB invalidation cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x8 card plug= ged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": Context cache global invalidation cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore reading from Card's MMIO space : Also known as Outbound. Number of req= uests initiated by the main die, including reads and writes. : x4 card is p= lugged in to slot 7", + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": ": Domain-selective Context cache invalidation= cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : IOMMU - Type 0= ", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": ": Device-selective Context cache invalidation= cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : IOMMU - Type 1= ", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : MsgB"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x16 card plugg= ed in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plu= gged in to slot 0", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : Multi= -cast", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x02", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 1", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : Ubox"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x8 card plugge= d in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : Memor= y", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 3", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : Remot= e P2P", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x10", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x16 card plugg= ed in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plu= gged in to slot 4", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : Local= P2P", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 5", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : Confi= ned P2P", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x40", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x8 card plugge= d in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "Num requests sent by PCIe - by target : Abort= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x80", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : C= ore writing to Card's MMIO space : Also known as Outbound. Number of reque= sts initiated by the main die, including reads and writes. : x4 card is plu= gged in to slot 7", + "UMask": "0x1", "Unit": "IIO" }, { - "BriefDescription": "ITC address map 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8F", - "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : IOMMU - Type 0", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": ": Issuing to IOMMU", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : IOMMU - Type 1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": ": Processing response from IOMMU", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x02", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to La= ne 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": ": Request Ownership", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": ": Issuing final read or write of line", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot= 2", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": ": Writing line", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x10", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": ": Passing data to be written", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to La= ne 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "Occupancy of outbound request queue : To devi= ce", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC5", - "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - cacheline complete : Request O= wnership", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot= 6", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - cacheline complete : Issuing f= inal read or write of line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) reading from this card. : Also known as O= utbound. Number of requests initiated by the main die, including reads and= writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - cacheline complete : Writing l= ine", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x10", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : IOMMU - Type 1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - cacheline complete : Passing d= ata to be written", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane= 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request complete : Issuing to IOMMU", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x4 card is plugged in to slot 1", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request complete : Processing response f= rom IOMMU", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x02", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2= ", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request complete : Request Ownership", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x4 card is plugged in to slot 3", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request complete : Issuing final read or= write of line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane= 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request complete : Writing line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x10", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x4 card is plugged in to slot 5", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request complete : Passing data to be wr= itten", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6= ", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - pass complete : Request Owners= hip", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : A= nother card (different IIO stack) writing to this card. : Also known as Out= bound. Number of requests initiated by the main die, including reads and w= rites. : x4 card is plugged in to slot 7", + "UMask": "0x2", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - pass complete : Issuing final = read or write of line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : IOMMU -= Type 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - pass complete : Writing line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : IOMMU -= Type 1", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "PCIe Request - pass complete : Passing data t= o be written", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x16 car= d plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card= is plugged in to slot 0", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests : Issuing to IO= MMU", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x4 card= is plugged in to slot 1", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests : Processing re= sponse from IOMMU", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x02", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x8 card= plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests : Request Owner= ship", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x4 card= is plugged in to slot 3", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests : Issuing final= read or write of line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x16 car= d plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card= is plugged in to slot 4", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests : Writing line"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x4 card= is plugged in to slot 5", "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests : Passing data = to be written", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x8 card= plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests granted : Issui= ng to IOMMU", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : A= tomic requests targeting DRAM : Also known as Inbound. Number of 64B cache= line requests initiated by the Card, including reads and writes. : x4 card= is plugged in to slot 7", + "UMask": "0x10", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests granted : Proce= ssing response from IOMMU", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x02", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : IOMMU - Type 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests granted : Reque= st Ownership", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : IOMMU - Type 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests granted : Issui= ng final read or write of line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lan= e 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests granted : Writi= ng line", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x10", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Incoming arbitration requests granted : Passi= ng data to be written", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot = 2", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Outbound cacheline requests issued : 64B requ= ests issued to device", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD0", - "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Outbound TLP (transaction layer packet) reque= sts issued : To device", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD1", - "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x08", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lan= e 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number requests sent to PCIe from main die : = >From IRP", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x01", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number requests sent to PCIe from main die : = >From ITC", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x02", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot = 6", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "Number requests sent to PCIe from main die : = Completion allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xc2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", + "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x04", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= mpD - device sending completion to CPU request : Also known as Inbound. Nu= mber of 64B cache line requests initiated by the Card, including reads and = writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", - "FCMask": "0x04", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x03", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : IOMMU - Type 0"= , + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", - "Counter": "2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", - "FCMask": "0x04", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0xFF", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : IOMMU - Type 1"= , + "UMask": "0x4", "Unit": "IIO" }, { - "BriefDescription": "Snoop Responses : Hit M", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IRP" + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x16 card plugge= d in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plug= ged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IRP" + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Total Write Cache Occupancy : Any Source", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0F", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IRP" + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x8 card plugged= in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Total Write Cache Occupancy : Snoops", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0F", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IRP" + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Coherent Ops : CLFlush", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x16 card plugge= d in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plug= ged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IRP" + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.EVICTS", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IRP" + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x8 card plugged= in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.FAST_REQ", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IRP" + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from DRAM : Also known as Inbound. Number of 64B cache line re= quests initiated by the Card, including reads and writes. : x4 card is plug= ged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.FAST_REJ", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IRP" + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Re= ad Transactions as Secondary", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IRP" + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IRP" + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x16 card plugged = in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugge= d in to slot 0", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of At= omic Transactions as Secondary", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 1", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers = >From Primary to Secondary", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.FAST_XFER", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x8 card plugged i= n to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints = >From Primary to Secondary", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 3", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn= 't find prefetch", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x16 card plugged = in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugge= d in to slot 4", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line= ", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_I", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IRP" + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 5", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line= ", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_S", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IRP" + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x8 card plugged i= n to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line= ", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_E", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IRP" + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to DRAM : Also known as Inbound. Number of 64B cache line requ= ests initiated by the Card, including reads and writes. : x4 card is plugge= d in to slot 7", + "UMask": "0x1", + "Unit": "IIO" }, { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line= ", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_M", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IRP" + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Misc Events - Set 1 : Received Invalid", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "Misc Events - Set 1 : Received Valid", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x16 card plugged in to Lane 0= /1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot= 0", "UMask": "0x40", - "Unit": "IRP" + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : P2P reads", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IRP" + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x4 card is plugged in to slot= 1", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : P2P Writes", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IRP" + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x8 card plugged in to Lane 2/= 3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : P2P Message", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IRP" + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x4 card is plugged in to slot= 3", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : P2P completions", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x08", - "Unit": "IRP" + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x16 card plugged in to Lane 4= /5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot= 4", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : Match if remote only", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x4 card is plugged in to slot= 5", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : match if remote and target= matches", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x8 card plugged in to Lane 6/= 7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : match if local only", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "FCMask": "0x07", "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : M= essages : Also known as Inbound. Number of 64B cache line requests initiat= ed by the Card, including reads and writes. : x4 card is plugged in to slot= 7", "UMask": "0x40", - "Unit": "IRP" + "Unit": "IIO" }, { - "BriefDescription": "P2P Transactions : match if local and target = matches", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Snoop Responses : Miss", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.MISS", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x01", - "Unit": "IRP" + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Snoop Responses : Hit I", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IRP" + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged = in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Snoop Responses : Hit E or S", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x04", - "Unit": "IRP" + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Snoop Responses : SnpCode", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in= to slot 2", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Snoop Responses : SnpData", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Snoop Responses : SnpInv", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged = in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Inbound Transaction Count : Writes", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WRITES", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x02", - "Unit": "IRP" + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Inbound Transaction Count : Atomic", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in= to slot 6", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Inbound Transaction Count : Other", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.OTHER", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= ard reading from another Card (same or different stack) : Also known as Inb= ound. Number of 64B cache line requests initiated by the Card, including r= eads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" }, { - "BriefDescription": "Inbound Transaction Count : Select Source", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "P2P Requests", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_I_P2P_INSERTS", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "P2P Occupancy", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_I_P2P_OCCUPANCY", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in= to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "AK Egress Allocations", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0B", - "EventName": "UNC_I_TxC_AK_INSERTS", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "BL DRS Egress Cycles Full", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x05", - "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in t= o slot 2", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "BL DRS Egress Inserts", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "BL DRS Egress Occupancy", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x08", - "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in= to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "BL NCB Egress Cycles Full", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x06", - "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "BL NCB Egress Inserts", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in t= o slot 6", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "BL NCB Egress Occupancy", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x09", - "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", "PerPkg": "1", - "Unit": "IRP" + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : C= ard writing to another Card (same or different stack) : Also known as Inbou= nd. Number of 64B cache line requests initiated by the Card, including rea= ds and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" }, { - "BriefDescription": "BL NCS Egress Cycles Full", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x07", - "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "BriefDescription": "Total Write Cache Occupancy : Any Source", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", + "PublicDescription": "Total Write Cache Occupancy : Any Source : A= ccumulates the number of reads and writes that are outstanding in the uncor= e in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRI= TE_OCCUPANCY events. : Tracks all requests from any source port.", + "UMask": "0x1", "Unit": "IRP" }, { - "BriefDescription": "BL NCS Egress Inserts", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "BriefDescription": "Total Write Cache Occupancy : Snoops", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", "PerPkg": "1", + "PublicDescription": "Total Write Cache Occupancy : Snoops : Accum= ulates the number of reads and writes that are outstanding in the uncore in= each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_O= CCUPANCY events.", + "UMask": "0x2", "Unit": "IRP" }, { - "BriefDescription": "BL NCS Egress Occupancy", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0A", - "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory.", + "EventCode": "0x0f", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and writ= e requests to coherent memory. This is effectively the sum of read occupan= cy and write occupancy.", + "UMask": "0x4", "Unit": "IRP" }, { - "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1C", - "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "BriefDescription": "Clockticks of the IO coherency tracker (IRP)"= , + "EventCode": "0x01", + "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", "Unit": "IRP" }, { - "BriefDescription": "No AD0 Egress Credits Stalls", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1A", - "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "BriefDescription": "Coherent Ops : CLFlush", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "PerPkg": "1", + "PublicDescription": "Coherent Ops : CLFlush : Counts the number o= f coherency related operations servied by the IRP", + "UMask": "0x80", "Unit": "IRP" }, { - "BriefDescription": "No AD1 Egress Credits Stalls", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1B", - "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", + "PublicDescription": "PCIITOM request issued by the IRP unit to th= e mesh with the intention of writing a full cacheline to coherent memory, w= ithout a RFO. PCIITOM is a speculative Invalidate to Modified command that= requests ownership of the cacheline and does not move data from the mesh t= o IRP cache.", + "UMask": "0x10", "Unit": "IRP" }, { - "BriefDescription": "No BL Egress Credit Stalls", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x1D", - "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", + "PublicDescription": "RFO request issued by the IRP unit to the me= sh with the intention of writing a partial cacheline to coherent memory. R= FO is a Read For Ownership command that requests ownership of the cacheline= and moves data from the mesh to IRP cache.", + "UMask": "0x8", "Unit": "IRP" }, { - "BriefDescription": "Outbound Read Requests", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0D", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "BriefDescription": "Coherent Ops : WbMtoI", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of= coherency related operations servied by the IRP", + "UMask": "0x40", "Unit": "IRP" }, { - "BriefDescription": "Outbound Read Requests", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0E", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "BriefDescription": "FAF RF full", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", "PerPkg": "1", "Unit": "IRP" }, { - "BriefDescription": "Outbound Request Queue Occupancy", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x0C", - "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", + "PublicDescription": "Inbound read requests to coherent memory, re= ceived by the IRP and inserted into the Fire and Forget queue (FAF), a queu= e used for processing inbound reads in the IRP.", "Unit": "IRP" }, { - "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "BriefDescription": "Occupancy of the IRP FAF queue.", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", - "UMask": "0x71", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) q= ueue, a queue used for processing inbound reads in the IRP.", "Unit": "IRP" }, { - "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "BriefDescription": "FAF allocation -- sent to ADQ", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", "PerPkg": "1", - "UMask": "0x7e", "Unit": "IRP" }, { - "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.EVICTS", "PerPkg": "1", - "UMask": "0x74", + "UMask": "0x4", "Unit": "IRP" }, { - "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", "PerPkg": "1", - "UMask": "0x72", + "UMask": "0x1", "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC Bypass : Not Taken", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of At= omic Transactions as Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "IRP" }, - { - "BriefDescription": "Number of reads in which direct to core trans= action was overridden", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Re= ad Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", - "UMask": "0x0704", - "UMaskExt": "0x07", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - A= ll Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", - "UMask": "0x0701", - "UMaskExt": "0x07", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - All C= hannels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", - "UMask": "0x1C10", - "UMaskExt": "0x1C", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL", + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers = >From Primary to Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", - "UMask": "0x1C01", - "UMaskExt": "0x1C", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints = >From Primary to Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", - "UMask": "0x1C02", - "UMaskExt": "0x1C", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "AD Ingress (from CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x01", - "EventName": "UNC_M2M_RxC_AD_INSERTS", + "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn= 't find prefetch", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", "PerPkg": "1", - "Unit": "M2M" + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x02", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop p= ulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x05", - "EventName": "UNC_M2M_RxC_BL_INSERTS", + "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Misc Events - Set 1 : Received Invalid : Sec= ondary received a transfer that did not have sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x06", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "BriefDescription": "Misc Events - Set 1 : Received Valid", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Misc Events - Set 1 : Received Valid : Secon= dary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "AD Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x09", - "EventName": "UNC_M2M_TxC_AD_INSERTS", + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line= ", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_E", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Lin= e : Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x0A", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line= ", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_I", "PerPkg": "1", - "Unit": "M2M" + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Lin= e : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "BL Egress (to CMS) Allocations : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line= ", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_M", "PerPkg": "1", - "UMask": "0x03", - "Unit": "M2M" + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Lin= e : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC Bypass : Taken", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line= ", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_S", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Lin= e : Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC Bypass : Taken", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "BriefDescription": "P2P Requests", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "P2P Requests : P2P requests from the ITC", + "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC Bypass : Not Taken", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "BriefDescription": "P2P Occupancy", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "BriefDescription": "P2P Transactions : P2P completions", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", "PerPkg": "1", - "UMask": "0x0101", - "UMaskExt": "0x01", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "BriefDescription": "P2P Transactions : match if local only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", "PerPkg": "1", - "UMask": "0x0102", - "UMaskExt": "0x01", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "BriefDescription": "P2P Transactions : match if local and target = matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", "PerPkg": "1", - "UMask": "0x0104", - "UMaskExt": "0x01", - "Unit": "M2M" + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "BriefDescription": "P2P Transactions : P2P Message", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", "PerPkg": "1", - "UMask": "0x0140", - "UMaskExt": "0x01", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "BriefDescription": "P2P Transactions : P2P reads", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", "PerPkg": "1", - "UMask": "0x0201", - "UMaskExt": "0x02", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "BriefDescription": "P2P Transactions : Match if remote only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", "PerPkg": "1", - "UMask": "0x0202", - "UMaskExt": "0x02", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "BriefDescription": "P2P Transactions : match if remote and target= matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", "PerPkg": "1", - "UMask": "0x0204", - "UMaskExt": "0x02", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "BriefDescription": "P2P Transactions : P2P Writes", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", "PerPkg": "1", - "UMask": "0x0240", - "UMaskExt": "0x02", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", "PerPkg": "1", - "UMask": "0x0401", - "UMaskExt": "0x04", - "Unit": "M2M" + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", + "UMask": "0x7e", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", "PerPkg": "1", - "UMask": "0x0402", - "UMaskExt": "0x04", - "Unit": "M2M" + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", + "UMask": "0x74", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", "PerPkg": "1", - "UMask": "0x0404", - "UMaskExt": "0x04", - "Unit": "M2M" + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", + "UMask": "0x72", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", "PerPkg": "1", - "UMask": "0x0408", - "UMaskExt": "0x04", - "Unit": "M2M" + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", "PerPkg": "1", - "UMask": "0x0410", - "UMaskExt": "0x04", - "Unit": "M2M" + "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", + "UMask": "0x71", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "BriefDescription": "Snoop Responses : Hit E or S", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", - "UMaskExt": "0x05", - "Unit": "M2M" + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "BriefDescription": "Snoop Responses : Hit I", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", - "UMask": "0x0801", - "UMaskExt": "0x08", - "Unit": "M2M" + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "BriefDescription": "Snoop Responses : Hit M", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", - "UMask": "0x0802", - "UMaskExt": "0x08", - "Unit": "M2M" + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "BriefDescription": "Snoop Responses : Miss", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", - "UMask": "0x0804", - "UMaskExt": "0x08", - "Unit": "M2M" + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "BriefDescription": "Snoop Responses : SnpCode", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", - "UMask": "0x0808", - "UMaskExt": "0x08", - "Unit": "M2M" + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "BriefDescription": "Snoop Responses : SnpData", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", - "UMask": "0x0810", - "UMaskExt": "0x08", - "Unit": "M2M" + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "BriefDescription": "Snoop Responses : SnpInv", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", - "UMaskExt": "0x09", - "Unit": "M2M" + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "Number Packet Header Matches : Mesh Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MESH", + "BriefDescription": "Inbound Transaction Count : Atomic", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Inbound Transaction Count : Atomic : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "Number Packet Header Matches : MC Match", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MC", + "BriefDescription": "Inbound Transaction Count : Other", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Inbound Transaction Count : Other : Counts t= he number of Inbound transactions from the IRP to the Uncore. This can be = filtered based on request type in addition to the source queue. Note the s= pecial filtering equation. We do OR-reduction on the request type. If the= SOURCE bit is set, then we also do AND qualification based on the source p= ortID. : Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", + "BriefDescription": "Inbound Transaction Count : Writes", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Inbound Transaction Count : Writes : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Trackes only write requests. Each write request should have a pr= efetch, so there is no need to explicitly track these requests. For writes= that are tickled and have to retry, the counter will be incremented for ea= ch retry.", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", + "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Inbound write (fast path) requests to cohere= nt memory, received by the IRP resulting in write ownership requests issued= by IRP to the mesh.", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", + "BriefDescription": "AK Egress Allocations", + "EventCode": "0x0B", + "EventName": "UNC_I_TxC_AK_INSERTS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", + "BriefDescription": "BL DRS Egress Cycles Full", + "EventCode": "0x05", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Cycles Full : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "BriefDescription": "BL DRS Egress Inserts", + "EventCode": "0x02", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Cycles Full : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "BriefDescription": "BL DRS Egress Occupancy", + "EventCode": "0x08", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Inserts : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "BriefDescription": "BL NCB Egress Cycles Full", + "EventCode": "0x06", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Inserts : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "BriefDescription": "BL NCB Egress Inserts", + "EventCode": "0x03", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Cycles Not Empty : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_NE.CH0", + "BriefDescription": "BL NCB Egress Occupancy", + "EventCode": "0x09", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Cycles Not Empty : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_NE.CH1", + "BriefDescription": "BL NCS Egress Cycles Full", + "EventCode": "0x07", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Occupancy : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "BriefDescription": "BL NCS Egress Inserts", + "EventCode": "0x04", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Tracker Occupancy : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "BriefDescription": "BL NCS Egress Occupancy", + "EventCode": "0x0A", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "Unit": "IRP" }, { - "BriefDescription": "Outbound Ring Transactions on AK : NDR Transa= ctions", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.NDR", + "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "EventCode": "0x1C", + "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": ": Counts the number times when it is not pos= sible to issue a request to the M2PCIe because there are no Egress Credits = available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count= as 2", + "Unit": "IRP" }, { - "BriefDescription": "Outbound Ring Transactions on AK : CRD Transa= ctions to Cbo", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "BriefDescription": "No AD0 Egress Credits Stalls", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "No AD0 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD0 Egress Credits available.", + "Unit": "IRP" }, { - "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "BriefDescription": "No AD1 Egress Credits Stalls", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "No AD1 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD1 Egress Credits available.", + "Unit": "IRP" }, { - "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "No BL Egress Credit Stalls", "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "No BL Egress Credit Stalls : Counts the numb= er times when it is not possible to issue data to the R2PCIe because there = are no BL Egress Credits available.", + "Unit": "IRP" }, { - "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0D", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2M" + "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", + "Unit": "IRP" }, { - "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0E", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" + "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", + "Unit": "IRP" }, { - "BriefDescription": "AK Egress (to CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0x0C", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2M" + "PublicDescription": "Outbound Request Queue Occupancy : Accumulte= s the number of outstanding outbound requests from the IRP to the switch (t= owards the devices). This can be used in conjuection with the allocations = event in order to calculate average latency of outbound requests.", + "Unit": "IRP" }, { - "BriefDescription": "AK Egress (to CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x88", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x90", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "UMask": "0xA0", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Full : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Not Empty : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Occupancy : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Full : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Not Empty : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0x03", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "WPQ Flush : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "WPQ Flush : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x58", - "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : = Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : = Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : = Channel 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : = Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : = Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : = Channel 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Full : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Full : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Full : Mirror", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Inserts : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x56", - "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Inserts : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x56", - "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x63", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x63", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x62", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x62", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy : Mirror", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Posted Inserts : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5E", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Posted Inserts : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5E", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5D", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMaskExt": "0x20", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMaskExt": "0x0C", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Deallocs", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "BriefDescription": "M2M to iMC Bypass : Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT", + "BriefDescription": "M2M to iMC Bypass : Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT", + "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "EventName": "UNC_M2M_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT", + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT", + "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", + "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "EventCode": "0x60", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", + "BriefDescription": "Number of reads in which direct to core trans= action was overridden", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", + "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", + "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", "PerPkg": "1", - "UMaskExt": "0x01", + "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", "PerPkg": "1", - "UMaskExt": "0x02", + "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMaskExt": "0x01", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMaskExt": "0x02", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Occupancy : Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Occupancy : Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": ": Channel 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": ": Channel 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x704", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ALL", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x104", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "PerPkg": "1", + "UMask": "0x140", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x102", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x101", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ALL", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x204", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x240", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x202", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x201", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", + "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Chan= nels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TGR", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x740", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x702", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - A= ll Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x701", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", + "BriefDescription": "M2M Writes Issued to iMC : All Writes - All C= hannels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1c10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x410", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x401", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x404", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x402", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x408", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x810", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", "PerPkg": "1", - "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x801", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x804", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", "PerPkg": "1", - "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x802", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x808", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Cha= nnels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1c01", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1c04", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1c02", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Al= l Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1c08", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Write Tracker Inserts", + "EventCode": "0x64", + "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", "PerPkg": "1", - "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x65", + "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", "PerPkg": "1", - "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Number Packet Header Matches : MC Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Number Packet Header Matches : Mesh Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "EventCode": "0x73", + "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Prefetch CAM Cycles Full : All Channels", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x7", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels"= , + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x7", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Data Prefetches Dropped : XPT - All Channels"= , + "EventCode": "0x6f", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x15", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 0", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 0", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 0", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 1", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI - Ch 1", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI- Ch 1", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 2", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 2", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- All Channels", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - All Channels", + "UMask": "0x15", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = All Channels", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x15", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 0", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 0", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 0", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 1", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 1", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 1", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 2", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - All Channels", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x15", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - All Channels", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x15", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", "PerPkg": "1", - "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", "PerPkg": "1", - "UMask": "0x08", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", "PerPkg": "1", - "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x15", "Unit": "M2M" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x7", "Unit": "M2M" }, { - "BriefDescription": "Distress signal asserted : Vertical", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", + "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Distress signal asserted : Horizontal", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", + "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Distress signal asserted : DPT Local", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", + "BriefDescription": ": All Channels", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x7", "Unit": "M2M" }, { - "BriefDescription": "Distress signal asserted : DPT Remote", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", + "BriefDescription": ": Channel 0", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", + "BriefDescription": ": Channel 1", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "EventCode": "0x79", + "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", "PerPkg": "1", - "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBA", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBA", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", + "EventCode": "0x78", + "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "EventCode": "0x77", + "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB9", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB9", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE6", - "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE6", - "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_M2M_RING_SRC_THRTL", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 0", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 1", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 0", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "BriefDescription": "AD Ingress (from CMS) Full", + "EventCode": "0x04", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x08", "Unit": "M2M" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "EventCode": "0x03", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", "PerPkg": "1", - "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "BriefDescription": "AD Ingress (from CMS) Allocations", + "EventCode": "0x01", + "EventName": "UNC_M2M_RxC_AD_INSERTS", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x02", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches"= , + "EventCode": "0x77", + "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x5C", + "EventName": "UNC_M2M_RxC_AK_WR_CMP", "PerPkg": "1", - "UMask": "0x08", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "BriefDescription": "BL Ingress (from CMS) Full", + "EventCode": "0x08", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "EventCode": "0x07", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "BriefDescription": "BL Ingress (from CMS) Allocations", + "EventCode": "0x05", + "EventName": "UNC_M2M_RxC_BL_INSERTS", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "EventCode": "0x06", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "Sink Starvation on Vertical Ring", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", + "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - All", "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", + "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Bypass : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", + "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : BL - All", "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.IV", + "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : IV", "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", + "EventName": "UNC_M2M_RxR_BYPASS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", + "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", + "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", + "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Transgress Injection Starvation : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - All", "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : IV", "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", + "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", + "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", + "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Allocations : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", + "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : BL - All", "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.IV", + "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : IV", "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", + "EventName": "UNC_M2M_RxR_INSERTS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", + "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", + "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Occupancy : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : BL - All", "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : IV", "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", + "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 0", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 1", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 0", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 1", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "BriefDescription": "Tracker Cycles Not Empty : Channel 0", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH0", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "BriefDescription": "Tracker Cycles Not Empty : Channel 1", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH1", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "BriefDescription": "Tracker Occupancy : Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "BriefDescription": "Tracker Occupancy : Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "EventCode": "0x0d", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "EventCode": "0x0e", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", "PerPkg": "1", - "UMask": "0x08", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "BriefDescription": "AD Egress (to CMS) Full", + "EventCode": "0x0c", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", "PerPkg": "1", - "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "BriefDescription": "AD Egress (to CMS) Not Empty", + "EventCode": "0x0b", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", "PerPkg": "1", - "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "BriefDescription": "AD Egress (to CMS) Allocations", + "EventCode": "0x09", + "EventName": "UNC_M2M_TxC_AD_INSERTS", "PerPkg": "1", - "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "EventCode": "0x0f", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", "PerPkg": "1", - "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", "PerPkg": "1", - "UMask": "0x01", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "BriefDescription": "AD Egress (to CMS) Occupancy", + "EventCode": "0x0A", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "BriefDescription": "Outbound Ring Transactions on AK : CRD Transa= ctions to Cbo", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "BriefDescription": "Outbound Ring Transactions on AK : NDR Transa= ctions", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "BriefDescription": "AKC Credits", + "EventCode": "0x5F", + "EventName": "UNC_M2M_TxC_AKC_CREDITS", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2M" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "BriefDescription": "AK Egress (to CMS) Full : All", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x88", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0xa0", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x90", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", + "BriefDescription": "AK Egress (to CMS) Not Empty : All", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", "PerPkg": "1", - "UMask": "0x44", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "BriefDescription": "AK Egress (to CMS) Allocations : All", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", "PerPkg": "1", - "UMask": "0x44", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "BriefDescription": "AK Egress (to CMS) Occupancy : All", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Near Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Far Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", "PerPkg": "1", - "UMask": "0x44", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Cache", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Core", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "BriefDescription": "BL Egress (to CMS) Full : All", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", "PerPkg": "1", - "UMask": "0x44", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", + "BriefDescription": "BL Egress (to CMS) Not Empty : All", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", + "BriefDescription": "BL Egress (to CMS) Allocations : All", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x3", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", "PerPkg": "1", - "UMask": "0x11", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", "PerPkg": "1", - "UMask": "0x44", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited"= , + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", + "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", + "UMask": "0x80", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Vertical IV Ring in Use : Up", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB3", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Vertical IV Ring in Use : Down", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB3", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x60", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x64", - "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Write Tracker Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x65", - "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x73", - "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x79", - "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x78", - "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x77", - "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Source Throttle", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xae", - "EventName": "UNC_M2M_RING_SRC_THRTL", + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "AD Ingress (from CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x04", - "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "AD Ingress (from CMS) Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x03", - "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "AK Egress (to CMS) Allocations", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5C", - "EventName": "UNC_M2M_RxC_AK_WR_CMP", + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "BL Ingress (from CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x08", - "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "BL Ingress (from CMS) Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x07", - "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x10", "Unit": "M2M" }, { - "BriefDescription": "Transgress Injection Starvation", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe4", - "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Number AD Ingress Credits", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_M2M_TGR_AD_CREDITS", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x20", "Unit": "M2M" }, { - "BriefDescription": "Number BL Ingress Credits", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_M2M_TGR_BL_CREDITS", + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Credit Acquired", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x0d", - "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x40", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Credits Occupancy", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x0e", - "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x0c", - "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "AD Egress (to CMS) Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x0b", - "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x0f", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "AKC Credits", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x5F", - "EventName": "UNC_M2M_TxC_AKC_CREDITS", + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ISOCH", + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x0702", - "UMaskExt": "0x07", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Chan= nels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x0740", - "UMaskExt": "0x07", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x1C04", - "UMaskExt": "0x1C", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Al= l Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x1C08", - "UMaskExt": "0x1C", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Cha= nnels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", "PerPkg": "1", - "UMaskExt": "0x1D", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", "PerPkg": "1", - "UMaskExt": "0x1C", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Full : All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x07", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x07", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Data Prefetches Dropped : XPT - All Channels"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6f", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x15", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH", + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x15", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Occupancy : All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x07", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": ": All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x07", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x15", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x15", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x77", - "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x15", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2M" }, { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2M" }, { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- All Channels", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", + "BriefDescription": "WPQ Flush : Channel 0", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH0", "PerPkg": "1", - "UMask": "0x15", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", + "BriefDescription": "WPQ Flush : Channel 1", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH1", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2M" }, { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI - Ch 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : = Channel 0", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : = Channel 1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : = Channel 2", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2PCIe" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : = Channel 0", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : = Channel 1", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : = Channel 2", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" + "UMask": "0x4", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "BriefDescription": "Write Tracker Cycles Full : Channel 0", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "BriefDescription": "Write Tracker Cycles Full : Channel 1", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "BriefDescription": "Write Tracker Cycles Full : Mirror", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "BriefDescription": "Write Tracker Inserts : Channel 0", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "BriefDescription": "Write Tracker Inserts : Channel 1", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", "PerPkg": "1", - "UMask": "0x08", - "Unit": "M2PCIe" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", "PerPkg": "1", "UMask": "0x10", - "Unit": "M2PCIe" + "Unit": "M2M" }, { - "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", "PerPkg": "1", "UMask": "0x20", - "Unit": "M2PCIe" + "Unit": "M2M" }, { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0"= , + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1"= , + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "BriefDescription": "Write Tracker Occupancy : Channel 0", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "BriefDescription": "Write Tracker Occupancy : Channel 1", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "BriefDescription": "Write Tracker Occupancy : Mirror", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" + "UMask": "0x8", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2PCIe" + "UMask": "0x10", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2PCIe" + "UMask": "0x20", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Full", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" + "UMask": "0x1", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" + "UMask": "0x2", + "Unit": "M2M" }, { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Ingress", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AD_0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Ingress", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.BL_0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Ingress", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Ingress", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AD_1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Ingress", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.BL_1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress (to CMS) Ingress", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Shared Credits Returned : Agent0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Shared Credits Returned : Agent1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Local P2P Shared Credits Returned : Agent2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "P2P Credit Occupancy : Local NCB", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "P2P Credit Occupancy : Local NCS", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "P2P Credit Occupancy : Remote NCB", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "P2P Credit Occupancy : Remote NCS", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "P2P Credit Occupancy : All", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Dedicated Credits Received : Local NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Dedicated Credits Received : Local NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Dedicated Credits Received : Remote NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Dedicated Credits Received : Remote NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Dedicated Credits Received : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Shared Credits Received : Local NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Shared Credits Received : Local NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Shared Credits Received : Remote NCB", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Shared Credits Received : Remote NCS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Shared Credits Received : All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "EventCode": "0x01", + "EventName": "UNC_M2P_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x02", "Unit": "M2PCIe" }, { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x04", "Unit": "M2PCIe" }, { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x2d", - "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCS message class.", "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credit fo= r transfer through CMS Port 0s to the IIO for the NCS message class.", "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the DRS message class.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCB message class.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCS message class.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0= ", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1= ", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0= ", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1= ", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0= ", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS me= ssage class.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1= ", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS me= ssage class.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent0", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent1", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent2", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", + "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent3", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", + "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent4", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", + "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent5", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Distress signal asserted : Vertical", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Distress signal asserted : Horizontal", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Distress signal asserted : DPT Local", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Distress signal asserted : DPT Remote", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", "PerPkg": "1", - "UMask": "0x40", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", "PerPkg": "1", - "UMask": "0x80", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xba", - "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xba", - "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "BriefDescription": "P2P Credit Occupancy : All", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "BriefDescription": "P2P Credit Occupancy : Local NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", + "BriefDescription": "P2P Credit Occupancy : Local NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "BriefDescription": "Dedicated Credits Received : All", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "BriefDescription": "Dedicated Credits Received : Local NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "BriefDescription": "Dedicated Credits Received : Local NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "BriefDescription": "Dedicated Credits Received : Remote NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "BriefDescription": "Dedicated Credits Received : Remote NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", + "BriefDescription": "Shared Credits Received : All", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "BriefDescription": "Shared Credits Received : Local NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "BriefDescription": "Shared Credits Received : Local NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "BriefDescription": "Shared Credits Received : Remote NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", + "BriefDescription": "Shared Credits Received : Remote NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb9", - "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", + "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb9", - "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", + "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent0", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe6", - "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", + "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent1", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe6", - "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", + "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent2", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Messages that bounced on the Vertical Ring.", "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Messages that bounced on the Vertical Ring", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", "PerPkg": "1", - "UMask": "0x20", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Sink Starvation on Vertical Ring", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_M2P_RING_SRC_THRTL", "PerPkg": "1", - "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", "Unit": "M2PCIe" }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Bypass : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", + "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Bypass : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : BL - All", "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.IV", + "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", + "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", + "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Bypass : IV", "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", + "EventName": "UNC_M2P_RxR_BYPASS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", + "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Injection Starvation : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - All", "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Injection Starvation : IV", "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", + "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_M2P_RxR_CRD_STARVED_1", "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", + "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Allocations : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", + "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Allocations : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : BL - All", "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.IV", + "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", + "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", + "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Allocations : IV", "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", + "EventName": "UNC_M2P_RxR_INSERTS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Occupancy : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : BL - All", "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Transgress Ingress Occupancy : IV", "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", + "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", "Unit": "M2PCIe" }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "EventCode": "0x2d", + "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd1", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_0", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_1", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal ADS Used : BL - All", "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Bypass Used : IV", "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Inserts : IV", "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress NACKs : IV", "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", + "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", + "UMask": "0x44", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", "PerPkg": "1", - "UMask": "0x11", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", "PerPkg": "1", - "UMask": "0x44", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", "PerPkg": "1", - "UMask": "0x02", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", + "UMask": "0x80", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", "PerPkg": "1", - "UMask": "0x80", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", "Unit": "M2PCIe" }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M2PCIe" + }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", "Unit": "M2PCIe" }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M2PCIe" + }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x10", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x20", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", "PerPkg": "1", - "UMask": "0x10", + "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", "PerPkg": "1", - "UMask": "0x20", + "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", + "UMask": "0x40", "Unit": "M2PCIe" }, { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", "PerPkg": "1", - "UMask": "0x40", + "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", + "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", "PerPkg": "1", - "UMask": "0x04", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical IV Ring in Use : Up", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb3", - "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical IV Ring in Use : Down", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb3", - "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", + "UMask": "0x4", "Unit": "M2PCIe" }, { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", + "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", "PerPkg": "1", - "UMask": "0x08", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", "Unit": "M2PCIe" }, { - "BriefDescription": "Source Throttle", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xae", - "EventName": "UNC_M2P_RING_SRC_THRTL", + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", "Unit": "M2PCIe" }, { - "BriefDescription": "Transgress Injection Starvation", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0xe4", - "EventName": "UNC_M2P_RxR_CRD_STARVED_1", + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", "Unit": "M2PCIe" }, { - "BriefDescription": "Message Received : VLW", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", - "PerPkg": "1", - "UMask": "0x01", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : MSI", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", - "PerPkg": "1", - "UMask": "0x02", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : IPI", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", - "UMask": "0x04", "Unit": "UBOX" }, { "BriefDescription": "Message Received : Doorbell", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", - "UMask": "0x08", + "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "Message Received : Interrupt", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", "PerPkg": "1", + "PublicDescription": "Message Received : Interrupt : Interrupts", "UMask": "0x10", "Unit": "UBOX" }, { - "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "BriefDescription": "Message Received : IPI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Message Received : IPI : Inter Processor Int= errupts", + "UMask": "0x4", "Unit": "UBOX" }, { - "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDRAND", + "BriefDescription": "Message Received : MSI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", "PerPkg": "1", - "UMask": "0x01", + "PublicDescription": "Message Received : MSI : Message Signaled In= terrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket = Mode only)", + "UMask": "0x2", "Unit": "UBOX" }, { - "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDSEED", + "BriefDescription": "Message Received : VLW", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", "PerPkg": "1", - "UMask": "0x02", + "PublicDescription": "Message Received : VLW : Virtual Logical Wir= e (legacy) message were received from Uncore.", + "UMask": "0x1", "Unit": "UBOX" }, { - "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", "PerPkg": "1", - "UMask": "0x04", + "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times = an IDI Lock/SplitLock sequence was started", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", "PerPkg": "1", @@ -25063,8 +21964,6 @@ }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", "PerPkg": "1", @@ -25072,59 +21971,39 @@ "Unit": "UBOX" }, { - "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x2", "Unit": "UBOX" }, { - "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", - "Counter": "0,1", - "CounterType": "PGMABLE", + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", "PerPkg": "1", - "UMask": "0x04", + "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", "PerPkg": "1", - "UMask": "0x08", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", - "PerPkg": "1", - "UMask": "0x10", + "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", "PerPkg": "1", @@ -25133,18 +22012,22 @@ }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", "PerPkg": "1", @@ -25153,40 +22036,59 @@ }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", "PerPkg": "1", - "UMask": "0x01", + "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", "PerPkg": "1", - "UMask": "0x02", + "UMask": "0x2", "Unit": "UBOX" }, { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "Counter": "0,1", - "CounterType": "PGMABLE", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", + "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK := PHOLD cycles.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", "PerPkg": "1", + "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", - "Counter": "0,1", - "CounterType": "PGMABLE", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", + "PublicDescription": "RACU Request : Number outstanding register r= equests within message channel tracker", "Unit": "UBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json b/= tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json index 281f3605881d..27fc155f1223 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json @@ -1,16 +1,12 @@ [ { "BriefDescription": "Clockticks of the power control unit (PCU)", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", "PerPkg": "1", @@ -18,8 +14,6 @@ }, { "BriefDescription": "UNC_P_DEMOTIONS", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", "PerPkg": "1", @@ -27,44 +21,38 @@ }, { "BriefDescription": "Phase Shed 0 Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", "PerPkg": "1", + "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-= shedding power state 0", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", "PerPkg": "1", + "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-= shedding power state 1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", "PerPkg": "1", + "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-= shedding power state 2", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", "PerPkg": "1", + "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-= shedding power state 3", "Unit": "PCU" }, { "BriefDescription": "AVX256 Frequency Clipping", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x49", "EventName": "UNC_P_FREQ_CLIP_AVX256", "PerPkg": "1", @@ -72,8 +60,6 @@ }, { "BriefDescription": "AVX512 Frequency Clipping", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x4a", "EventName": "UNC_P_FREQ_CLIP_AVX512", "PerPkg": "1", @@ -81,155 +67,137 @@ }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x04", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "PerPkg": "1", + "PublicDescription": "Thermal Strongest Upper Limit Cycles : Numbe= r of cycles any frequency is reduced due to a thermal limit. Count only if= throttling is occurring.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x05", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "PerPkg": "1", + "PublicDescription": "Power Strongest Upper Limit Cycles : Counts = the number of cycles when power is the upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "PerPkg": "1", + "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Co= unts the number of cycles when IO P Limit is preventing us from dropping th= e frequency lower. This algorithm monitors the needs to the IO subsystem o= n both local and remote sockets and will maintain a frequency high enough t= o maintain good IO BW. This is necessary for when all the IA cores on a so= cket are idle but a user still would like to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", "PerPkg": "1", + "PublicDescription": "Cycles spent changing Frequency : Counts the= number of cycles when the system is changing frequency. This can not be f= iltered by thread ID. One can also use it with the occupancy counter that = monitors number of threads in C0 to estimate the performance impact that fr= equency transitions had on the system.", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", + "PublicDescription": "Memory Phase Shedding Cycles : Counts the nu= mber of cycles that the PCU has triggered memory phase shedding. This is a= mode that can be run in the iMC physicals that saves power at the expense = of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", "PerPkg": "1", + "PublicDescription": "Package C State Residency - C0 : Counts the = number of cycles when the package was in C0. This event can be used in con= junction with edge detect to count C0 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", "PerPkg": "1", + "PublicDescription": "Package C State Residency - C2E : Counts the= number of cycles when the package was in C2E. This event can be used in c= onjunction with edge detect to count C2E entrances (or exits using invert).= Residency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", "PerPkg": "1", + "PublicDescription": "Package C State Residency - C3 : Counts the = number of cycles when the package was in C3. This event can be used in con= junction with edge detect to count C3 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", "PerPkg": "1", + "PublicDescription": "Package C State Residency - C6 : Counts the = number of cycles when the package was in C6. This event can be used in con= junction with edge detect to count C6 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", "EventCode": "0x06", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "External Prochot", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x0A", - "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "BriefDescription": "Number of cores in C-State : C0 and C1", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", + "PublicDescription": "Number of cores in C-State : C0 and C1 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with threshholding to generate histograms, or with other PCU= events and occupancy triggering to capture other details.", "Unit": "PCU" }, { - "BriefDescription": "Internal Prochot", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x09", - "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "BriefDescription": "Number of cores in C-State : C3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", + "PublicDescription": "Number of cores in C-State : C3 : This is an= occupancy event that tracks the number of cores that are in the chosen C-S= tate. It can be used by itself to get the average number of cores in that = C-state with threshholding to generate histograms, or with other PCU events= and occupancy triggering to capture other details.", "Unit": "PCU" }, { - "BriefDescription": "Total Core C State Transition Cycles", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x72", - "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "BriefDescription": "Number of cores in C-State : C6 and C7", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", + "PublicDescription": "Number of cores in C-State : C6 and C7 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with threshholding to generate histograms, or with other PCU= events and occupancy triggering to capture other details.", "Unit": "PCU" }, { - "BriefDescription": "VR Hot", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x42", - "EventName": "UNC_P_VR_HOT_CYCLES", + "BriefDescription": "External Prochot", + "EventCode": "0x0A", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "PerPkg": "1", + "PublicDescription": "External Prochot : Counts the number of cycl= es that we are in external PROCHOT mode. This mode is triggered when a sen= sor off the die determines that something off-die (like DRAM) is too hot an= d must throttle to avoid damaging the chip.", "Unit": "PCU" }, { - "BriefDescription": "Number of cores in C-State : C0 and C1", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "BriefDescription": "Internal Prochot", + "EventCode": "0x09", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", + "PublicDescription": "Internal Prochot : Counts the number of cycl= es that we are in Internal PROCHOT mode. This mode is triggered when a sen= sor on the die determines that we are too hot and must throttle to avoid da= maging the chip.", "Unit": "PCU" }, { - "BriefDescription": "Number of cores in C-State : C3", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "BriefDescription": "Total Core C State Transition Cycles", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "PerPkg": "1", + "PublicDescription": "Total Core C State Transition Cycles : Numbe= r of cycles spent performing core C state transitions across all cores.", "Unit": "PCU" }, { - "BriefDescription": "Number of cores in C-State : C6 and C7", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "BriefDescription": "VR Hot", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", + "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" } ] diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json index b82f11591f13..cabe29e70e79 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json @@ -1,363 +1,246 @@ [ { "BriefDescription": "Counts the number of page walks due to loads = that miss the PDE (Page Directory Entry) cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccount for all page sizes. Will result in a DTLB write from STLB.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", "SampleAfterValue": "200003", "UMask": "0xe" }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 1G page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. = Includes page walks that page fault.", "SampleAfterValue": "200003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for demand loads every cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for demand loads every cycle. A page walk i= s outstanding from start till PMH becomes idle again (ready to serve next w= alk). Includes EPT-walk intervals.", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of page walks due to stores= that miss the PDE (Page Directory Entry) cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Account = for all pages sizes. Will result in a DTLB write from STLB.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", "SampleAfterValue": "200003", "UMask": "0xe" }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that = page fault.", "SampleAfterValue": "200003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A page walk is outs= tanding from start till PMH becomes idle again (ready to serve next walk). = Includes EPT-walk intervals.", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry hits.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of Extended Page Directory= Entry hits. The Extended Page Directory cache is used by Virtual Machine = operating systems while the guest operating systems use the standard TLB ca= ches.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_MISS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number Extended Page Directory En= try misses. The Extended Page Directory cache is used by Virtual Machine o= perating systems while the guest operating systems use the standard TLB cac= hes.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry hits.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry hits. The Extended Page Directory cache is used by Virtual Mac= hine operating systems while the guest operating systems use the standard T= LB caches.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_MISS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry misses. The Extended Page Directory cache is used by Virtual M= achine operating systems while the guest operating systems use the standard= TLB caches.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of page walks outstanding f= or an Extended Page table walk including GTLB hits per cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding = for an Extended Page table walk including GTLB hits per cycle. The Extende= d Page Directory cache is used by Virtual Machine operating systems while t= he guest operating systems use the standard TLB caches.", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of times there was an ITLB = miss and a new translation was filled into the ITLB.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "ITLB.FILLS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) and a new translation was filled into the ITLB. The event is specul= ative in nature, but will not count translations (page walks) that are begu= n and not finished, or translations that are finished but not filled into t= he ITLB.", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.PDE_CACHE_MISS", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB."= , - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", "SampleAfterValue": "200003", "UMask": "0xe" }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 1G page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes pag= e walks that page fault.", "SampleAfterValue": "200003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for instruction fetches every cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", - "PDIR_COUNTER": "NA", - "PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for instruction fetches every cycle. A page= walk is outstanding from start till PMH becomes idle again (ready to serve= next walk).", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of retired loads that are b= locked due to a first level TLB miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DTLB_MISS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "UMask": "0x8" }, { "BriefDescription": "Counts the number of memory uops retired that= missed in the second level TLB.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x13" }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the second Level TLB.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x11" }, { "BriefDescription": "Counts the number of store uops retired that = miss in the second level TLB.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", "PEBS": "1", - "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", "UMask": "0x12" } --=20 2.39.0.314.g84b9a713c41-goog