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From: Witold Sadowski <wsadowski@marvell.com>
To: <broonie@kernel.org>
Cc: <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <jpawar@cadence.com>,
	<pthombar@cadence.com>, <konrad@cadence.com>,
	<wbartczak@marvell.com>, <wzmuda@marvell.com>,
	<wsadowski@marvell.com>
Subject: [PATCH 5/7] spi: cadence: Add read access size switch
Date: Mon, 19 Dec 2022 06:42:52 -0800	[thread overview]
Message-ID: <20221219144254.20883-6-wsadowski@marvell.com> (raw)
In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com>

Allow to use different SDMA read size.
In Marvell implementation of that IP each SDMA
access will read 8 bytes at once, and is not
configurable.

Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
Reviewed-by: Chandrakala Chavva <cchavva@marvell.com>
Tested-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
---
 drivers/spi/spi-cadence-xspi.c | 99 ++++++++++++++++++++++++++++++++--
 1 file changed, 95 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 25db0d55d5ef..719c2f3b4771 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -209,6 +209,11 @@ enum cdns_xspi_stig_cmd_dir {
 	CDNS_XSPI_STIG_CMD_DIR_WRITE,
 };
 
+enum cdns_xspi_sdma_size {
+	CDNS_XSPI_SDMA_SIZE_8B = 0,
+	CDNS_XSPI_SDMA_SIZE_64B = 1,
+};
+
 struct cdns_xspi_dev {
 	struct platform_device *pdev;
 	struct device *dev;
@@ -230,6 +235,7 @@ struct cdns_xspi_dev {
 	const void *out_buffer;
 
 	u8 hw_num_banks;
+	enum cdns_xspi_sdma_size read_size;
 };
 
 static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi)
@@ -329,6 +335,82 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
 	return 0;
 }
 
+static void cdns_ioreadq(void __iomem  *addr, void *buf, int len)
+{
+	int i = 0;
+	int rcount = len / 8;
+	int rcount_nf = len % 8;
+	uint64_t tmp;
+	uint64_t *buf64 = (uint64_t *)buf;
+
+	if (((uint64_t)buf % 8) == 0) {
+		for (i = 0; i < rcount; i++)
+			*buf64++ = readq(addr);
+	} else {
+		for (i = 0; i < rcount; i++) {
+			tmp = readq(addr);
+			memcpy(buf+(i*8), &tmp, 8);
+		}
+	}
+
+	if (rcount_nf != 0) {
+		tmp = readq(addr);
+		memcpy(buf+(i*8), &tmp, rcount_nf);
+	}
+}
+
+static void cdns_iowriteq(void __iomem *addr, const void *buf, int len)
+{
+	int i = 0;
+	int rcount = len / 8;
+	int rcount_nf = len % 8;
+	uint64_t tmp;
+	uint64_t *buf64 = (uint64_t *)buf;
+
+	if (((uint64_t)buf % 8) == 0) {
+		for (i = 0; i < rcount; i++)
+			writeq(*buf64++, addr);
+	} else {
+		for (i = 0; i < rcount; i++) {
+			memcpy(&tmp, buf+(i*8), 8);
+			writeq(tmp, addr);
+		}
+	}
+
+	if (rcount_nf != 0) {
+		memcpy(&tmp, buf+(i*8), rcount_nf);
+		writeq(tmp, addr);
+	}
+}
+
+static void cdns_xspi_sdma_memread(struct cdns_xspi_dev *cdns_xspi,
+				   enum cdns_xspi_sdma_size size, int len)
+{
+	switch (size) {
+	case CDNS_XSPI_SDMA_SIZE_8B:
+		ioread8_rep(cdns_xspi->sdmabase,
+			    cdns_xspi->in_buffer, len);
+		break;
+	case CDNS_XSPI_SDMA_SIZE_64B:
+		cdns_ioreadq(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len);
+		break;
+	}
+}
+
+static void cdns_xspi_sdma_memwrite(struct cdns_xspi_dev *cdns_xspi,
+				    enum cdns_xspi_sdma_size size, int len)
+{
+	switch (size) {
+	case CDNS_XSPI_SDMA_SIZE_8B:
+		iowrite8_rep(cdns_xspi->sdmabase,
+			     cdns_xspi->out_buffer, len);
+		break;
+	case CDNS_XSPI_SDMA_SIZE_64B:
+		cdns_iowriteq(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len);
+		break;
+	}
+}
+
 static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
 {
 	u32 sdma_size, sdma_trd_info;
@@ -340,13 +422,15 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
 
 	switch (sdma_dir) {
 	case CDNS_XSPI_SDMA_DIR_READ:
-		ioread8_rep(cdns_xspi->sdmabase,
-			    cdns_xspi->in_buffer, sdma_size);
+		cdns_xspi_sdma_memread(cdns_xspi,
+				       cdns_xspi->read_size,
+				       sdma_size);
 		break;
 
 	case CDNS_XSPI_SDMA_DIR_WRITE:
-		iowrite8_rep(cdns_xspi->sdmabase,
-			     cdns_xspi->out_buffer, sdma_size);
+		cdns_xspi_sdma_memwrite(cdns_xspi,
+					cdns_xspi->read_size,
+					sdma_size);
 		break;
 	}
 }
@@ -526,7 +610,14 @@ static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
 {
 	struct device_node *node_prop = pdev->dev.of_node;
 	struct device_node *node_child;
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(master);
 	unsigned int cs;
+	unsigned int read_size = 0;
+
+	if (of_property_read_u32(node_prop, "cdns,read-size", &read_size))
+		dev_info(&pdev->dev, "Missing read size property, usining byte access\n");
+	cdns_xspi->read_size = read_size;
 
 	for_each_child_of_node(node_prop, node_child) {
 		if (!of_device_is_available(node_child))
-- 
2.17.1


  parent reply	other threads:[~2022-12-19 14:43 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-19 14:42 [PATCH 0/7] Support for Marvell modifications for Cadence XSPI Witold Sadowski
2022-12-19 14:42 ` [PATCH 1/7] spi: cadence: Fix busy cycles calculation Witold Sadowski
2022-12-19 14:42 ` [PATCH 2/7] spi: cadence: Change dt-bindings documentation for Cadence XSPI controller Witold Sadowski
2022-12-20 14:08   ` Krzysztof Kozlowski
2022-12-19 14:42 ` [PATCH 3/7] spi: cadence: Add polling mode support Witold Sadowski
2022-12-19 18:05   ` kernel test robot
2022-12-19 14:42 ` [PATCH 4/7] spi: cadence: Change dt-bindings documentation for Cadence XSPI controller Witold Sadowski
2022-12-19 18:14   ` Mark Brown
2022-12-19 21:22   ` Rob Herring
2022-12-20 14:09   ` Krzysztof Kozlowski
2024-04-29 15:13     ` [EXT] " Witold Sadowski
2022-12-19 14:42 ` Witold Sadowski [this message]
2022-12-19 18:16   ` [PATCH 5/7] spi: cadence: Add read access size switch Mark Brown
2024-04-29 15:40     ` [EXT] " Witold Sadowski
2022-12-19 20:26   ` kernel test robot
2022-12-19 14:42 ` [PATCH 6/7] spi: cadence: Add Marvell IP modification changes Witold Sadowski
2022-12-19 18:27   ` Mark Brown
2024-04-29 15:27     ` [EXT] " Witold Sadowski
2022-12-20 14:12   ` Krzysztof Kozlowski
2024-04-29 15:10     ` [EXT] " Witold Sadowski
2022-12-19 14:42 ` [PATCH 7/7] spi: cadence: Force single modebyte Witold Sadowski
2022-12-19 18:28   ` Mark Brown
2022-12-27 11:57 ` (subset) [PATCH 0/7] Support for Marvell modifications for Cadence XSPI Mark Brown

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