Hi Hal,

I love your patch! Perhaps something to improve:

[auto build test WARNING on 830b3c68c1fb1e9176028d02ef86f3cf76aa2476]

url:    https://github.com/intel-lab-lkp/linux/commits/Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131
base:   830b3c68c1fb1e9176028d02ef86f3cf76aa2476
patch link:    https://lore.kernel.org/r/20221220005054.34518-11-hal.feng%40starfivetech.com
patch subject: [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on clock driver
config: riscv-randconfig-s042-20221218
compiler: riscv64-linux-gcc (GCC) 12.1.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/intel-lab-lkp/linux/commit/e30705645d46071dc6c7ce5485b5ebf3aeeaa59c
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131
        git checkout e30705645d46071dc6c7ce5485b5ebf3aeeaa59c
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv SHELL=/bin/bash drivers/clk/starfive/ drivers/reset/starfive/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

sparse warnings: (new ones prefixed by >>)
   WARNING: invalid argument to '-march': '_zihintpause'
>> drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@     expected void *data @@     got void [noderef] __iomem *base @@
   drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse:     expected void *data
   drivers/clk/starfive/clk-starfive-jh7110-aon.c:86:40: sparse:     got void [noderef] __iomem *base

vim +86 drivers/clk/starfive/clk-starfive-jh7110-aon.c

    67	
    68	static int jh7110_aoncrg_probe(struct platform_device *pdev)
    69	{
    70		struct jh71x0_clk_priv *priv;
    71		unsigned int idx;
    72		int ret;
    73	
    74		priv = devm_kzalloc(&pdev->dev,
    75				    struct_size(priv, reg, JH7110_AONCLK_END),
    76				    GFP_KERNEL);
    77		if (!priv)
    78			return -ENOMEM;
    79	
    80		spin_lock_init(&priv->rmw_lock);
    81		priv->dev = &pdev->dev;
    82		priv->base = devm_platform_ioremap_resource(pdev, 0);
    83		if (IS_ERR(priv->base))
    84			return PTR_ERR(priv->base);
    85	
  > 86		dev_set_drvdata(priv->dev, priv->base);
    87	
    88		for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
    89			u32 max = jh7110_aonclk_data[idx].max;
    90			struct clk_parent_data parents[4] = {};
    91			struct clk_init_data init = {
    92				.name = jh7110_aonclk_data[idx].name,
    93				.ops = starfive_jh71x0_clk_ops(max),
    94				.parent_data = parents,
    95				.num_parents =
    96					((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
    97				.flags = jh7110_aonclk_data[idx].flags,
    98			};
    99			struct jh71x0_clk *clk = &priv->reg[idx];
   100			unsigned int i;
   101	
   102			for (i = 0; i < init.num_parents; i++) {
   103				unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
   104	
   105				if (pidx < JH7110_AONCLK_END)
   106					parents[i].hw = &priv->reg[pidx].hw;
   107				else if (pidx == JH7110_AONCLK_OSC)
   108					parents[i].fw_name = "osc";
   109				else if (pidx == JH7110_AONCLK_RTC_OSC)
   110					parents[i].fw_name = "rtc_osc";
   111				else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
   112					parents[i].fw_name = "gmac0_rmii_refin";
   113				else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
   114					parents[i].fw_name = "gmac0_rgmii_rxin";
   115				else if (pidx == JH7110_AONCLK_STG_AXIAHB)
   116					parents[i].fw_name = "stg_axiahb";
   117				else if (pidx == JH7110_AONCLK_APB_BUS)
   118					parents[i].fw_name = "apb_bus";
   119				else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
   120					parents[i].fw_name = "gmac0_gtxclk";
   121			}
   122	
   123			clk->hw.init = &init;
   124			clk->idx = idx;
   125			clk->max_div = max & JH71X0_CLK_DIV_MASK;
   126	
   127			ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
   128			if (ret)
   129				return ret;
   130		}
   131	
   132		ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
   133		if (ret)
   134			return ret;
   135	
   136		return jh7110_reset_controller_register(priv, "reset-aon", 1);
   137	}
   138	

-- 
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