From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11EBEC05027 for ; Thu, 26 Jan 2023 10:02:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236127AbjAZKC4 (ORCPT ); Thu, 26 Jan 2023 05:02:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236640AbjAZKCx (ORCPT ); Thu, 26 Jan 2023 05:02:53 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 571AD2D5F for ; Thu, 26 Jan 2023 02:02:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674727371; x=1706263371; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6ChX89HR/3U78JArj0uB8/BQ22sQtA1WUj0y9whtnMk=; b=f9WMB2tsU/tAkF7bpCg0/iGvDxnJcKEKvBBwzusrTdC9xGFkYSu2lleO e5xV7xMh4u/K2faTXVqcGWybd7q66EgJQ1VqwA10A/fyaEhW5fVn8+RtB mclbKZZV94FUwTekGujkd+i5nR8ufnXnJ+rkZDXeEQVonbUYHQ4wY+THr 3k3qP/j4rDo+spckfo7BlKN7oBeyBkCo0/KzGMh6COUG8w5e436kaWx+4 95GwdMvE9Kmh+oRo57A50OsVcakc1Ke9AI/RiGQ60kKeOuIt2oYLg+F1S HmeUbbFWjxcncp7MJNIewjYBPeei/4QYCBTT7i4oL83KPbdmdy2FyIbEo w==; X-IronPort-AV: E=McAfee;i="6500,9779,10601"; a="354071795" X-IronPort-AV: E=Sophos;i="5.97,248,1669104000"; d="scan'208";a="354071795" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2023 02:02:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10601"; a="612746606" X-IronPort-AV: E=Sophos;i="5.97,248,1669104000"; d="scan'208";a="612746606" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga003.jf.intel.com with ESMTP; 26 Jan 2023 02:02:47 -0800 From: Lu Baolu To: iommu@lists.linux.dev Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Ashok Raj , linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH 1/1] iommu/vt-d: Set No Execute Enable bit in PASID table entry Date: Thu, 26 Jan 2023 17:54:38 +0800 Message-Id: <20230126095438.354205-1-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setup No Execute Enable bit (Bit 133) of a scalable mode PASID entry. It is required when XD bit of the first level page table entry is about to be set. Fixes: ddf09b6d43ec ("iommu/vt-d: Setup pasid entries for iova over first level") Signed-off-by: Ashok Raj Signed-off-by: Lu Baolu --- drivers/iommu/intel/pasid.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index fb3c7020028d..ec964ac7d797 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -364,6 +364,16 @@ static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value) pasid_set_bits(&pe->val[1], 1 << 23, value << 23); } +/* + * Setup No Execute Enable bit (Bit 133) of a scalable mode PASID + * entry. It is required when XD bit of the first level page table + * entry is about to be set. + */ +static inline void pasid_set_nxe(struct pasid_entry *pe) +{ + pasid_set_bits(&pe->val[2], 1 << 5, 1 << 5); +} + /* * Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode * PASID entry. @@ -557,6 +567,7 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, pasid_set_domain_id(pte, did); pasid_set_address_width(pte, iommu->agaw); pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); + pasid_set_nxe(pte); /* Setup Present and PASID Granular Transfer Type: */ pasid_set_translation_type(pte, PASID_ENTRY_PGTT_FL_ONLY); -- 2.34.1