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From: Jordan Crouse <jorcrous@amazon.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: <linux-arm-msm@vger.kernel.org>, <andersson@kernel.org>,
	<agross@kernel.org>, <krzysztof.kozlowski@linaro.org>,
	<freedreno@lists.freedesktop.org>,
	Akhil P Oommen <quic_akhilpo@quicinc.com>,
	David Airlie <airlied@gmail.com>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	<dri-devel@lists.freedesktop.org>,
	Douglas Anderson <dianders@chromium.org>,
	Rob Clark <robdclark@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
	"Dmitry Baryshkov" <dmitry.baryshkov@linaro.org>,
	<marijn.suijten@somainline.org>, Sean Paul <sean@poorly.run>,
	Chia-I Wu <olvaffe@gmail.com>, <linux-kernel@vger.kernel.org>
Subject: Re: [Freedreno] [PATCH 09/14] drm/msm/a6xx: Fix some A619 tunables
Date: Wed, 8 Feb 2023 11:21:01 -0700	[thread overview]
Message-ID: <20230208182101.53ykatzah6zvpy76@amazon.com> (raw)
In-Reply-To: <20230126151618.225127-10-konrad.dybcio@linaro.org>

On Thu, Jan 26, 2023 at 04:16:13PM +0100, Konrad Dybcio wrote:
> Adreno 619 expects some tunables to be set differently. Make up for it.
> 
> Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 7a480705f407..f34ab3f39f09 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1171,6 +1171,8 @@ static int hw_init(struct msm_gpu *gpu)
>                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
>         else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
>                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
> +       else if (adreno_is_a619(adreno_gpu))
> +               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000);
>         else if (adreno_is_a610(adreno_gpu))
>                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000);
>         else
> @@ -1188,7 +1190,9 @@ static int hw_init(struct msm_gpu *gpu)
>         a6xx_set_ubwc_config(gpu);
> 
>         /* Enable fault detection */
> -       if (adreno_is_a610(adreno_gpu))
> +       if (adreno_is_a619(adreno_gpu))
> +               gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
> +       else if (adreno_is_a610(adreno_gpu))
>                 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff);
>         else
>                 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);

The number appended to the register is the number of clock ticks to wait
before declaring a hang. 0x3fffff happens to be the largest value that
can be set for the a6xx family (excepting the 610 which, IIRC, used older
hardware that had a smaller field for the counter). Downstream the
number would creep up over time as unexplained hangs were discovered and
diagnosed or covered up as "just wait longer".

So in theory you could leave this with the "default value" or even bump
up the default value to 0x3fffff for all targets if you wanted to. An
alternate solution (that downstream does) is to put this as a
pre-defined configuration in gpulist[].

Jordan

  reply	other threads:[~2023-02-08 18:21 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20230126151618.225127-1-konrad.dybcio@linaro.org>
2023-01-26 15:16 ` [PATCH 01/14] drm/msm/a6xx: De-staticize sptprac en/disable functions Konrad Dybcio
2023-01-26 15:16 ` [PATCH 02/14] drm/msm/a6xx: Extend UBWC config Konrad Dybcio
2023-02-01  9:30   ` Akhil P Oommen
2023-02-01 10:51     ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 03/14] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio
2023-01-26 15:16 ` [PATCH 04/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio
2023-01-26 15:16 ` [PATCH 05/14] drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi Konrad Dybcio
2023-01-26 15:16 ` [PATCH 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs Konrad Dybcio
2023-02-06 18:30   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 07/14] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio
2023-01-26 15:16 ` [PATCH 08/14] drm/msm/a6xx: Add A610 support Konrad Dybcio
2023-01-26 15:16 ` [PATCH 09/14] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio
2023-02-08 18:21   ` Jordan Crouse [this message]
2023-02-14 11:25     ` [Freedreno] " Konrad Dybcio
2023-01-26 15:16 ` [PATCH 10/14] drm/msm/a6xx: Fix up A6XX protected registers Konrad Dybcio
2023-01-26 15:16 ` [PATCH 11/14] drm/msm/a6xx: Enable optional icc voting from OPP tables Konrad Dybcio
2023-01-26 15:16 ` [PATCH 12/14] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio
2023-01-26 15:16 ` [PATCH 13/14] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio
2023-01-27 14:19   ` Dmitry Baryshkov
2023-01-27 14:20     ` Konrad Dybcio
2023-01-27 14:22     ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 14/14] drm/msm/a6xx: Add A610 " Konrad Dybcio

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