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Fri, 10 Feb 2023 14:44:12 -0800 (PST) X-Google-Smtp-Source: AK7set/pYb5EOh/Drz42V1PJ5+VKWj6WP/ITUzBus6W3/LeQWRmoejvgCP3pyCdxFAjIjZZ39ARC1A== X-Received: by 2002:a05:6602:2acd:b0:722:827d:e6ac with SMTP id m13-20020a0566022acd00b00722827de6acmr17507122iov.6.1676069052584; Fri, 10 Feb 2023 14:44:12 -0800 (PST) Received: from redhat.com ([38.15.36.239]) by smtp.gmail.com with ESMTPSA id c11-20020a02a40b000000b003bf39936d1esm1666882jal.131.2023.02.10.14.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:44:11 -0800 (PST) Date: Fri, 10 Feb 2023 15:44:10 -0700 From: Alex Williamson To: Yi Liu Cc: joro@8bytes.org, jgg@nvidia.com, kevin.tian@intel.com, robin.murphy@arm.com, cohuck@redhat.com, eric.auger@redhat.com, nicolinc@nvidia.com, kvm@vger.kernel.org, mjrosato@linux.ibm.com, chao.p.peng@linux.intel.com, yi.y.sun@linux.intel.com, peterx@redhat.com, jasowang@redhat.com, shameerali.kolothum.thodi@huawei.com, lulu@redhat.com, suravee.suthikulpanit@amd.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, baolu.lu@linux.intel.com Subject: Re: [PATCH 2/6] iommu/vt-d: Implement hw_info for iommu capability query Message-ID: <20230210154410.2b3b8296.alex.williamson@redhat.com> In-Reply-To: <20230209041642.9346-3-yi.l.liu@intel.com> References: <20230209041642.9346-1-yi.l.liu@intel.com> <20230209041642.9346-3-yi.l.liu@intel.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.35; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 8 Feb 2023 20:16:38 -0800 Yi Liu wrote: > From: Lu Baolu > > To support nested translation in the userspace, it should check the > underlying hardware information for the capabilities. > > Add intel_iommu_hw_info() to report cap_reg and ecap_reg information. > > Signed-off-by: Lu Baolu > Signed-off-by: Yi Liu > Signed-off-by: Nicolin Chen > Signed-off-by: Yi Sun > --- > drivers/iommu/intel/iommu.c | 19 +++++++++++++++++++ > drivers/iommu/intel/iommu.h | 1 + > include/uapi/linux/iommufd.h | 21 +++++++++++++++++++++ > 3 files changed, 41 insertions(+) > > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index 59df7e42fd53..929f600cc350 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -4760,8 +4760,26 @@ static void intel_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid) > intel_pasid_tear_down_entry(iommu, dev, pasid, false); > } > > +static void *intel_iommu_hw_info(struct device *dev, u32 *length) > +{ > + struct device_domain_info *info = dev_iommu_priv_get(dev); > + struct intel_iommu *iommu = info->iommu; > + struct iommu_device_info_vtd *vtd; > + > + vtd = kzalloc(sizeof(*vtd), GFP_KERNEL); > + if (!vtd) > + return ERR_PTR(-ENOMEM); > + > + vtd->cap_reg = iommu->cap; > + vtd->ecap_reg = iommu->ecap; Just a friendly reminder that these registers are already exposed to userspace under /sys/class/iommu/ and each device has an iommu link back to their iommu device there. This series doesn't really stand on its own without some discussion of why that interface is not sufficient for this use case. Thanks, Alex