From: arinc9.unal@gmail.com
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Paul Cercueil <paul@crapouillou.net>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Sergio Paracuellos <sergio.paracuellos@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>
Cc: "Arınç ÜNAL" <arinc.unal@arinc9.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
devicetree@vger.kernel.org, linux-mips@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, erkin.bozoglu@xeront.com
Subject: [PATCH 2/2] mips: dts: ralink: mt7621: add port@5 as CPU port
Date: Sat, 11 Feb 2023 13:49:15 +0300 [thread overview]
Message-ID: <20230211104915.116253-2-arinc.unal@arinc9.com> (raw)
In-Reply-To: <20230211104915.116253-1-arinc.unal@arinc9.com>
From: Arınç ÜNAL <arinc.unal@arinc9.com>
On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
connected to the second MAC of the SoC as a CPU port. Add the port and set
up the second MAC on the bindings. Revert PHY muxing on GB-PC1.
There's an external PHY connected to the second MAC of the SoC on GB-PC2,
therefore, disable port@5 for this device.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
---
.../boot/dts/ralink/mt7621-gnubee-gb-pc1.dts | 16 +++++-----------
.../boot/dts/ralink/mt7621-gnubee-gb-pc2.dts | 9 ++++++++-
arch/mips/boot/dts/ralink/mt7621.dtsi | 19 ++++++++++++++++++-
3 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
index 4314aee97e18..129b6710b699 100644
--- a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
+++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
@@ -91,22 +91,16 @@ &pcie {
status = "okay";
};
-&gmac1 {
- status = "okay";
- phy-handle = <ðphy4>;
-};
-
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
-};
-
&switch0 {
ports {
port@0 {
status = "okay";
label = "ethblack";
};
+
+ port@4 {
+ status = "okay";
+ label = "ethblue";
+ };
};
};
diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
index 3ebbf933f644..f810cd10f4f4 100644
--- a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
+++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
@@ -112,9 +112,12 @@ &pcie {
};
&gmac1 {
- status = "okay";
phy-mode = "rgmii-rxid";
phy-handle = <ðphy5>;
+
+ fixed-link {
+ status = "disabled";
+ };
};
&mdio {
@@ -134,5 +137,9 @@ port@4 {
status = "okay";
label = "ethblue";
};
+
+ port@5 {
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index aec85c779359..290d47fbcfbb 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -332,8 +332,13 @@ fixed-link {
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
- status = "disabled";
phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
};
mdio: mdio-bus {
@@ -384,6 +389,18 @@ port@4 {
label = "swp4";
};
+ port@5 {
+ reg = <5>;
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
port@6 {
reg = <6>;
ethernet = <&gmac0>;
--
2.37.2
next prev parent reply other threads:[~2023-02-11 10:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-11 10:49 [PATCH 1/2] mips: dts: align LED node names with dtschema arinc9.unal
2023-02-11 10:49 ` arinc9.unal [this message]
2023-02-14 12:33 ` [PATCH 2/2] mips: dts: ralink: mt7621: add port@5 as CPU port Sergio Paracuellos
2023-02-17 11:03 ` Thomas Bogendoerfer
2023-02-14 12:36 ` [PATCH 1/2] mips: dts: align LED node names with dtschema Sergio Paracuellos
2023-02-17 11:02 ` Thomas Bogendoerfer
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