From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 501A2C636D4 for ; Mon, 13 Feb 2023 15:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231384AbjBMPDS (ORCPT ); Mon, 13 Feb 2023 10:03:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231339AbjBMPDK (ORCPT ); Mon, 13 Feb 2023 10:03:10 -0500 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [5.144.164.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C93C98A76 for ; Mon, 13 Feb 2023 07:02:51 -0800 (PST) Received: from SoMainline.org (D57D4C6E.static.ziggozakelijk.nl [213.125.76.110]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id D91E01F55E; Mon, 13 Feb 2023 16:02:27 +0100 (CET) Date: Mon, 13 Feb 2023 16:02:26 +0100 From: Marijn Suijten To: Dmitry Baryshkov Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org, Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Robert Foss , AngeloGioacchino Del Regno , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Message-ID: <20230213150226.du27ocydnyrkvuin@SoMainline.org> References: <20230211122656.1479141-1-konrad.dybcio@linaro.org> <20230211122656.1479141-6-konrad.dybcio@linaro.org> <20230213111220.ietr4aro6xu4emtu@SoMainline.org> <20230213143148.qvyagudd3qm5jgwd@SoMainline.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023-02-13 16:40:56, Dmitry Baryshkov wrote: > On 13/02/2023 16:31, Marijn Suijten wrote: > > On 2023-02-13 13:38:33, Dmitry Baryshkov wrote: > >> On 13/02/2023 13:12, Marijn Suijten wrote: > >>> On 2023-02-11 13:26:51, Konrad Dybcio wrote: > >>>> These blocks are of variable length on different SoCs. Set the > >>>> correct values where I was able to retrieve it from downstream > >>>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for > >>>> intf) otherwise. > >>>> > >>>> Signed-off-by: Konrad Dybcio > >>>> --- > >>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++--------- > >>>> 1 file changed, 121 insertions(+), 121 deletions(-) > >>>> > >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > >>>> index 802050118345..d9ef1e133c1e 100644 > >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > >>> [..] > >>>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = { > >>>> /************************************************************* > >>>> * INTF sub blocks config > >>>> *************************************************************/ > >>>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ > >>>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ > >>> > >>> Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE > >>> macro that accounts for the INTF TE registers using this higher register > >>> area, as well as an extended signature to configure extra interrupts. > >> > >> Yes, that's still the plan. It's slightly painful that we are touching > >> this are simultaneously. > > > > Should we (Konrad) then drop this patch as there's no need to add these > > (mostly RAZ/WI) registers to the dump until my INTF TE series starts > > using them? That'll make rebasing easier on everyone too. > > RAZ/WI is for not present registers (read-as-zero/write-ignore). I think > that the growing register space is getting populated with registers > (which we have been ignoring up to now). They are, but not until my INTF TE series lands; hence again the request to drop this patch until that happens? - Marijn