From: Harsha Harsha <harsha.harsha@amd.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
<linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <michals@xilinx.com>
Cc: <saratcha@xilinx.com>, <git@amd.com>,
Harsha Harsha <harsha.harsha@amd.com>,
Dhaval Shah <dhaval.r.shah@amd.com>
Subject: [PATCH 1/4] firmware: xilinx: Get the SoC family specific data for crypto operation
Date: Sat, 18 Feb 2023 11:08:06 +0530 [thread overview]
Message-ID: <20230218053809.1780-2-harsha.harsha@amd.com> (raw)
In-Reply-To: <20230218053809.1780-1-harsha.harsha@amd.com>
Get family type and sub-family type of SoC and on basis of that, return the
data specific to the SoC which can be used for the required crypto
operations.
Signed-off-by: Harsha Harsha <harsha.harsha@amd.com>
Co-developed-by: Dhaval Shah <dhaval.r.shah@amd.com>
Signed-off-by: Dhaval Shah <dhaval.r.shah@amd.com>
---
drivers/firmware/xilinx/zynqmp.c | 79 ++++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 34 ++++++++++++
2 files changed, 113 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 129f68d7a6f5..10ae42a2ae22 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -339,6 +339,8 @@ int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
static u32 pm_api_version;
static u32 pm_tz_version;
+static u32 pm_family_code;
+static u32 pm_sub_family_code;
int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
{
@@ -404,6 +406,78 @@ int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid);
+/**
+ * zynqmp_pm_get_family_info() - Get family info of platform
+ * @family: Returned family code value
+ * @subfamily: Returned sub-family code value
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u32 idcode;
+ int ret;
+
+ /* Check is family or sub-family code already received */
+ if (pm_family_code && pm_sub_family_code) {
+ *family = pm_family_code;
+ *subfamily = pm_sub_family_code;
+ return 0;
+ }
+
+ ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
+ if (ret < 0)
+ return ret;
+
+ idcode = ret_payload[1];
+ pm_family_code = FIELD_GET(GENMASK(FAMILY_CODE_MSB, FAMILY_CODE_LSB),
+ idcode);
+ pm_sub_family_code = FIELD_GET(GENMASK(SUB_FAMILY_CODE_MSB,
+ SUB_FAMILY_CODE_LSB), idcode);
+ *family = pm_family_code;
+ *subfamily = pm_sub_family_code;
+
+ return 0;
+}
+
+/**
+ * xlnx_get_crypto_dev_data() - Get crypto dev data of platform
+ * @feature_map: List of available feature map of all platform
+ *
+ * Return: Returns crypto dev data, either address crypto dev or ERR PTR
+ */
+void *xlnx_get_crypto_dev_data(struct xlnx_feature *feature_map)
+{
+ struct xlnx_feature *feature;
+ u32 v, api_id;
+ int ret;
+
+ ret = zynqmp_pm_get_api_version(&v);
+ if (ret)
+ return ERR_PTR(ret);
+
+ feature = feature_map;
+ for (; feature->family; feature++) {
+ if (feature->family == pm_family_code &&
+ (feature->subfamily == ALL_SUB_FAMILY_CODE ||
+ feature->subfamily == pm_sub_family_code)) {
+ api_id = FIELD_GET(API_ID_MASK, feature->feature_id);
+ if (feature->family == ZYNQMP_FAMILY_CODE) {
+ ret = zynqmp_pm_feature(api_id);
+ if (ret < 0)
+ return ERR_PTR(ret);
+ } else {
+ return ERR_PTR(-ENODEV);
+ }
+
+ return feature->data;
+ }
+ }
+ return ERR_PTR(-ENODEV);
+}
+EXPORT_SYMBOL_GPL(xlnx_get_crypto_dev_data);
+
/**
* zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version
* @version: Returned version value
@@ -1855,6 +1929,11 @@ static int zynqmp_firmware_probe(struct platform_device *pdev)
pr_info("%s Platform Management API v%d.%d\n", __func__,
pm_api_version >> 16, pm_api_version & 0xFFFF);
+ /* Get the Family code and sub family code of platform */
+ ret = zynqmp_pm_get_family_info(&pm_family_code, &pm_sub_family_code);
+ if (ret < 0)
+ return ret;
+
/* Check trustzone version number */
ret = zynqmp_pm_get_trustzone_version(&pm_tz_version);
if (ret)
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index b986e267d149..cd5acfa29cbc 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -34,6 +34,20 @@
/* PM API versions */
#define PM_API_VERSION_2 2
+#define ZYNQMP_FAMILY_CODE 0x23
+
+/* When all subfamily of platform need to support */
+#define ALL_SUB_FAMILY_CODE 0
+#define VERSAL_SUB_FAMILY_CODE 1
+#define VERSALNET_SUB_FAMILY_CODE 3
+
+#define FAMILY_CODE_LSB 21
+#define FAMILY_CODE_MSB 27
+#define SUB_FAMILY_CODE_LSB 19
+#define SUB_FAMILY_CODE_MSB 20
+
+#define API_ID_MASK GENMASK(7, 0)
+
/* ATF only commands */
#define TF_A_PM_REGISTER_SGI 0xa04
#define PM_GET_TRUSTZONE_VERSION 0xa03
@@ -475,12 +489,27 @@ struct zynqmp_pm_query_data {
u32 arg3;
};
+/**
+ * struct xlnx_feature - Feature data
+ * @family: Family code of platform
+ * @subfamily: Subfamily code of platform
+ * @feature_id: Feature id of module
+ * @data: Collection of all supported platform data
+ */
+struct xlnx_feature {
+ u32 family;
+ u32 subfamily;
+ u32 feature_id;
+ void *data;
+};
+
int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
u32 arg2, u32 arg3, u32 *ret_payload);
#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
int zynqmp_pm_get_api_version(u32 *version);
int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
+void *xlnx_get_crypto_dev_data(struct xlnx_feature *feature_map);
int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
int zynqmp_pm_clock_enable(u32 clock_id);
int zynqmp_pm_clock_disable(u32 clock_id);
@@ -561,6 +590,11 @@ static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
return -ENODEV;
}
+static inline void *xlnx_get_crypto_dev_data(struct xlnx_feature *feature_map)
+{
+ return ERR_PTR(-ENODEV);
+}
+
static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
u32 *out)
{
--
2.36.1
next prev parent reply other threads:[~2023-02-18 5:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-18 5:38 [PATCH 0/4] crypto: Add Xilinx ZynqMP RSA driver support Harsha Harsha
2023-02-18 5:38 ` Harsha Harsha [this message]
2023-02-18 5:38 ` [PATCH 2/4] firmware: xilinx: Add ZynqMP RSA API for RSA encrypt/decrypt operation Harsha Harsha
2023-02-18 5:38 ` [PATCH 3/4] crypto: xilinx: Add ZynqMP RSA driver Harsha Harsha
2023-03-10 10:31 ` Herbert Xu
2023-03-15 5:02 ` Harsha, Harsha
2023-03-15 5:06 ` Herbert Xu
2023-02-18 5:38 ` [PATCH 4/4] MAINTAINERS: Add maintainer for Xilinx " Harsha Harsha
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