[PATCH v3 0/7] PCI: dwc: Add support for Marvell AC5 SoC

[Elad Nachman <enachman@marvell.com>]

From: Elad Nachman <enachman@marvell.com>

Add support for AC5 SoC with MSI and in message emulated legacy mode.
There are differences in the registers addresses, blocks, DDR location
for coherent DMA allocation and additional implementation specific registers.
In addition, support cases of older Designware IP (Armada 7020) which supports
above 4GB PCIe physical memory window by use of device tree.

v3:
   1) Add dt bindings for DMA and region mask bits

   2) Support AC5 Legacy PCIe interrupts

   3) Introduce Configurable DMA mask

   4) Introduce region limit from DT

v2:
   1) add patch with adding compatible string for dt-bindings description

   2) fix W1 warnings which caused by unused leftover code

   3) Use one xlate function to translate ac5 dbi access. Also add
      mode description in comments about this translation.

   4) Use correct name of Raz

   5) Use matching data to pass the SoC specific params (type & ops)

Elad Nachman (4):
  dt-bindings: PCI: dwc: add DMA, region mask bits
  PCI: dwc: support AC5 Legacy PCIe interrupts
  PCI: dwc: Introduce Configurable DMA mask
  PCI: dwc: Introduce region limit from DT

Raz Adashi (1):
  PCI: armada8k: Add AC5 SoC support

Vadym Kochan (1):
  dt-bindings: PCI: armada8k: Add compatible string for AC5 SoC

Yuval Shaia (1):
  PCI: armada8k: Add MSI support for AC5 SoC

 .../devicetree/bindings/pci/pci-armada8k.txt  |   4 +-
 .../bindings/pci/snps,dw-pcie-common.yaml     |  10 +
 drivers/pci/controller/dwc/pcie-armada8k.c    | 184 +++++++++++++++---
 .../pci/controller/dwc/pcie-designware-host.c |  23 ++-
 drivers/pci/controller/dwc/pcie-designware.c  |  13 +-
 5 files changed, 197 insertions(+), 37 deletions(-)

-- 
2.17.1