From: Heiko Stuebner <heiko@sntech.de>
To: palmer@rivosinc.com
Cc: greentime.hu@sifive.com, conor@kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
christoph.muellner@vrull.eu, heiko@sntech.de,
Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: [PATCH RFC v2 07/16] RISC-V: add helper function to read the vector VLEN
Date: Tue, 28 Feb 2023 01:05:35 +0100 [thread overview]
Message-ID: <20230228000544.2234136-8-heiko@sntech.de> (raw)
In-Reply-To: <20230228000544.2234136-1-heiko@sntech.de>
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
VLEN describes the length of each vector register and some instructions
need specific minimal VLENs to work correctly.
The vector code already includes a variable riscv_vsize that contains the
value of "32 vector registers with vlenb length" that gets filled during
boot. vlenb is the value contained in the CSR_VLENB register and
the value represents "VLEN / 8".
So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
users when they need to check the available VLEN.
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
arch/riscv/include/asm/vector.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index f38266ec483a..ad9e6161dd89 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -163,4 +163,15 @@ static inline bool vstate_query(struct pt_regs *regs) { return false; }
#endif /* CONFIG_RISCV_ISA_V */
+/*
+ * Return the implementation's vlen value.
+ *
+ * riscv_vsize contains the value of "32 vector registers with vlenb length"
+ * so rebuild the vlen value in bits from it.
+ */
+static inline int riscv_vector_vlen(void)
+{
+ return riscv_vsize / 32 * 8;
+}
+
#endif /* ! __ASM_RISCV_VECTOR_H */
--
2.39.0
next prev parent reply other threads:[~2023-02-28 0:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-28 0:05 [PATCH RFC v2 00/16] RISC-V: support some cryptography accelerations Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 01/16] riscv: Add support for kernel mode vector Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 02/16] riscv: Add vector extension XOR implementation Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 03/16] RISC-V: add Zbc extension detection Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 04/16] RISC-V: add Zbkb " Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 05/16] RISC-V: hook new crypto subdir into build-system Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 06/16] RISC-V: crypto: add accelerated GCM GHASH implementation Heiko Stuebner
2023-02-28 0:05 ` Heiko Stuebner [this message]
2023-02-28 0:05 ` [PATCH RFC v2 08/16] RISC-V: add vector crypto extension detection Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 09/16] RISC-V: crypto: update perl include with helpers for vector (crypto) instructions Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 10/16] RISC-V: crypto: add Zvkb accelerated GCM GHASH implementation Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 11/16] RISC-V: crypto: add Zvkg " Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 12/16] RISC-V: crypto: add a vector-crypto-accelerated SHA256 implementation Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 13/16] RISC-V: crypto: add a vector-crypto-accelerated SHA512 implementation Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 14/16] RISC-V: crypto: add Zvkned accelerated AES encryption implementation Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 15/16] RISC-V: crypto: add Zvksed accelerated SM4 " Heiko Stuebner
2023-02-28 0:05 ` [PATCH RFC v2 16/16] RISC-V: crypto: add Zvksh accelerated SM3 hash implementation Heiko Stuebner
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