From: David Yang <mmyangfl@gmail.com>
To: mmyangfl@gmail.com
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/6] clk: hisilicon: Rename some symbols for Hi3798CV200
Date: Sat, 4 Mar 2023 14:33:27 +0800 [thread overview]
Message-ID: <20230304063333.162309-6-mmyangfl@gmail.com> (raw)
In-Reply-To: <20230304063333.162309-1-mmyangfl@gmail.com>
These symbols might cause confusion when adding support for other Hi3798
series SoCs.
Signed-off-by: David Yang <mmyangfl@gmail.com>
---
drivers/clk/hisilicon/crg-hi3798.c | 35 +++++++++++++++---------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c
index 9c933172b..b52d44350 100644
--- a/drivers/clk/hisilicon/crg-hi3798.c
+++ b/drivers/clk/hisilicon/crg-hi3798.c
@@ -177,30 +177,31 @@ static void hi3798_sysctrl_clk_unregister(
/* hi3798CV200 */
-static const char *const mmc_mux_p[] = {
+static const char *const hi3798cv200_mmc_mux_p[] = {
"100m", "50m", "25m", "200m", "150m" };
-static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
+static u32 hi3798cv200_mmc_mux_table[] = {0, 1, 2, 3, 6};
-static const char *const comphy_mux_p[] = {
+static const char *const hi3798cv200_comphy_mux_p[] = {
"100m", "25m"};
-static u32 comphy_mux_table[] = {2, 3};
+static u32 hi3798cv200_comphy_mux_table[] = {2, 3};
-static const char *const sdio_mux_p[] = {
+static const char *const hi3798cv200_sdio_mux_p[] = {
"100m", "50m", "150m", "166p5m" };
-static u32 sdio_mux_table[] = {0, 1, 2, 3};
+static u32 hi3798cv200_sdio_mux_table[] = {0, 1, 2, 3};
static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
- { HI3798_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
- CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
- { HI3798_COMBPHY0_MUX, "combphy0_mux",
- comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
- CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
- { HI3798_COMBPHY1_MUX, "combphy1_mux",
- comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
- CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
- { HI3798_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
- ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
- 0x9c, 8, 2, 0, sdio_mux_table, },
+ { HI3798_MMC_MUX, "mmc_mux", hi3798cv200_mmc_mux_p,
+ ARRAY_SIZE(hi3798cv200_mmc_mux_p), CLK_SET_RATE_PARENT,
+ 0xa0, 8, 3, 0, hi3798cv200_mmc_mux_table, },
+ { HI3798_COMBPHY0_MUX, "combphy0_mux", hi3798cv200_comphy_mux_p,
+ ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT,
+ 0x188, 2, 2, 0, hi3798cv200_comphy_mux_table, },
+ { HI3798_COMBPHY1_MUX, "combphy1_mux", hi3798cv200_comphy_mux_p,
+ ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT,
+ 0x188, 10, 2, 0, hi3798cv200_comphy_mux_table, },
+ { HI3798_SDIO0_MUX, "sdio0_mux", hi3798cv200_sdio_mux_p,
+ ARRAY_SIZE(hi3798cv200_sdio_mux_p), CLK_SET_RATE_PARENT,
+ 0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, },
};
static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
--
2.39.2
next prev parent reply other threads:[~2023-03-04 6:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-04 6:33 [PATCH v2 0/6] Add CRG driver for Hi3798MV100 SoC David Yang
2023-03-04 6:33 ` [PATCH v2 1/6] clk: hisilicon: Rename Hi3798CV200 to Hi3798 David Yang
2023-03-06 12:08 ` Claudiu.Beznea
2023-03-04 6:33 ` [PATCH v2 2/6] clk: hisilicon: Extract common functions David Yang
2023-03-04 6:33 ` [PATCH v2 3/6] dt-bindings: clk: Add Hi3798MV100 CRG driver binding David Yang
2023-03-05 9:54 ` Krzysztof Kozlowski
2023-03-04 6:33 ` [PATCH v2 3/6] dt-bindings: clock: " David Yang
2023-03-05 9:55 ` Krzysztof Kozlowski
2023-03-04 6:33 ` David Yang [this message]
2023-03-04 6:33 ` [PATCH v2 5/6] clk: hisilicon: Add inner clocks for Hi3798MV100 David Yang
2023-03-04 6:33 ` [PATCH v2 6/6] clk: hisilicon: Add CRG driver for Hi3798MV100 SoC David Yang
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