Re: [PATCH] arm64/sysreg: Convert HW[RW]TR_EL2 to automatic generation

[Joey Gouly <joey.gouly@arm.com>]

Hi again!

Just noticed there's also a typo in the subject:

    arm64/sysreg: Convert HW[RW]TR_EL2 to automatic generation

Should be `HFG[RW]TR_EL2`.

Thanks,
Joey

On Mon, Mar 06, 2023 at 08:46:18PM +0000, Mark Brown wrote:
> Convert the fine grained traps read and write control registers to
> automatic generation as per DDI0601 2022-12. No functional changes.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h |  8 -----
>  arch/arm64/tools/sysreg         | 75 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 75 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 9e3ecba3c4e6..e5ca9ece1606 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -419,8 +419,6 @@
>  #define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
>  #define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
>  #define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
> -#define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
> -#define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
>  #define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
>  #define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
>  
> @@ -758,12 +756,6 @@
>  #define ICH_VTR_TDS_SHIFT	19
>  #define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
>  
> -/* HFG[WR]TR_EL2 bit definitions */
> -#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT	55
> -#define HFGxTR_EL2_nTPIDR2_EL0_MASK	BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
> -#define HFGxTR_EL2_nSMPRI_EL1_SHIFT	54
> -#define HFGxTR_EL2_nSMPRI_EL1_MASK	BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
> -
>  #define ARM64_FEATURE_FIELD_BITS	4
>  
>  /* Defined for compatibility only, do not add new users. */

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