From: Jacky Huang <ychuang570808@gmail.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
p.zabel@pengutronix.de, gregkh@linuxfoundation.org,
jirislaby@kernel.org
Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
schung@nuvoton.com, Jacky Huang <ychuang3@nuvoton.com>
Subject: [PATCH 11/15] arm64: dts: nuvoton: Add initial ma35d1 device tree
Date: Wed, 15 Mar 2023 07:28:58 +0000 [thread overview]
Message-ID: <20230315072902.9298-12-ychuang570808@gmail.com> (raw)
In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com>
From: Jacky Huang <ychuang3@nuvoton.com>
Add initial device tree support for Nuvoton ma35d1 SoC, including
cpu, clock, reset, and serial controllers.
Add reference boards som-256m and iot-512m.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
arch/arm64/boot/dts/nuvoton/Makefile | 2 +
.../boot/dts/nuvoton/ma35d1-iot-512m.dts | 24 ++
.../boot/dts/nuvoton/ma35d1-som-256m.dts | 23 ++
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 272 ++++++++++++++++++
4 files changed, 321 insertions(+)
create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
index a99dab90472a..c11ab4eac9c7 100644
--- a/arch/arm64/boot/dts/nuvoton/Makefile
+++ b/arch/arm64/boot/dts/nuvoton/Makefile
@@ -1,2 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb
+dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-iot-512m.dtb
+dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-som-256m.dtb
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
new file mode 100644
index 000000000000..dffcaef1e6d8
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * Jacky huang <ychuang3@nuvoton.com>
+ */
+
+/dts-v1/;
+#include "ma35d1.dtsi"
+
+/ {
+ model = "Nuvoton MA35D1-IoT";
+ compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ mem: memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */
+ };
+};
+
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
new file mode 100644
index 000000000000..3e6c3d5469ac
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * Jacky huang <ychuang3@nuvoton.com>
+ */
+
+/dts-v1/;
+#include "ma35d1.dtsi"
+
+/ {
+ model = "Nuvoton MA35D1-SOM";
+ compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ mem: memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */
+ };
+};
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
new file mode 100644
index 000000000000..8c855f6b330a
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * Jacky huang <ychuang3@nuvoton.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+#include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
+
+/ {
+ compatible = "nuvoton,ma35d1";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ serial10 = &uart10;
+ serial11 = &uart11;
+ serial12 = &uart12;
+ serial13 = &uart13;
+ serial14 = &uart14;
+ serial15 = &uart15;
+ serial16 = &uart16;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clk_hxt: clock_hxt {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "clk_hxt";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ clock-frequency = <12000000>;
+ interrupt-parent = <&gic>;
+ };
+
+ sys: system-management@40460000 {
+ compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";
+ reg = <0x0 0x40460000 0x0 0x200>;
+
+ reset: reset-controller {
+ compatible = "nuvoton,ma35d1-reset";
+ regmap = <&sys>;
+ #reset-cells = <1>;
+ };
+ };
+
+ clk: clock-controller@40460200 {
+ compatible = "nuvoton,ma35d1-clk", "syscon";
+ reg = <0x00000000 0x40460200 0x0 0x100>;
+ #clock-cells = <1>;
+ clocks = <&clk_hxt>;
+ clock-names = "clk_hxt";
+ assigned-clocks = <&clk CAPLL>,
+ <&clk DDRPLL>,
+ <&clk APLL>,
+ <&clk EPLL>,
+ <&clk VPLL>;
+ assigned-clock-rates = <800000000>,
+ <266000000>,
+ <180000000>,
+ <500000000>,
+ <102000000>;
+ nuvoton,pll-mode = <0>, <1>, <0>, <0>, <0>;
+ nuvoton,sys = <&sys>;
+ };
+
+ gic: interrupt-controller@50801000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0x0 0x50801000 0 0x1000>, /* GICD */
+ <0x0 0x50802000 0 0x2000>, /* GICC */
+ <0x0 0x50804000 0 0x2000>, /* GICH */
+ <0x0 0x50806000 0 0x2000>; /* GICV */
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ uart0:serial@40700000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40700000 0x0 0x100>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART0_GATE>;
+ status = "okay";
+ };
+
+ uart1:serial@40710000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40710000 0x0 0x100>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART1_GATE>;
+ status = "disabled";
+ };
+
+ uart2:serial@40720000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40720000 0x0 0x100>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART2_GATE>;
+ status = "disabled";
+ };
+
+ uart3:serial@40730000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40730000 0x0 0x100>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART3_GATE>;
+ status = "disabled";
+ };
+
+ uart4:serial@40740000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40740000 0x0 0x100>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART4_GATE>;
+ status = "disabled";
+ };
+
+ uart5:serial@40750000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40750000 0x0 0x100>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART5_GATE>;
+ status = "disabled";
+ };
+
+ uart6:serial@40760000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40760000 0x0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART6_GATE>;
+ status = "disabled";
+ };
+
+ uart7:serial@40770000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40770000 0x0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART7_GATE>;
+ status = "disabled";
+ };
+
+ uart8:serial@40780000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40780000 0x0 0x100>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART8_GATE>;
+ status = "disabled";
+ };
+
+ uart9:serial@40790000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40790000 0x0 0x100>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART9_GATE>;
+ status = "disabled";
+ };
+
+ uart10:serial@407a0000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x407a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART10_GATE>;
+ status = "disabled";
+ };
+
+ uart11:serial@407b0000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x407b0000 0x0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART11_GATE>;
+ status = "disabled";
+ };
+
+ uart12:serial@407c0000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x407c0000 0x0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART12_GATE>;
+ status = "disabled";
+ };
+
+ uart13:serial@407d0000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x407d0000 0x0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART13_GATE>;
+ status = "disabled";
+ };
+
+ uart14:serial@407e0000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x407e0000 0x0 0x100>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART14_GATE>;
+ status = "disabled";
+ };
+
+ uart15:serial@407f0000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x407f0000 0x0 0x100>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART15_GATE>;
+ status = "disabled";
+ };
+
+ uart16:serial@40880000 {
+ compatible = "nuvoton,ma35d1-uart";
+ reg = <0x0 0x40880000 0x0 0x100>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk UART16_GATE>;
+ status = "disabled";
+ };
+};
--
2.34.1
next prev parent reply other threads:[~2023-03-15 7:32 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-15 7:28 [PATCH 00/15] Introduce Nuvoton ma35d1 SoC Jacky Huang
2023-03-15 7:28 ` [PATCH 01/15] arm64: Kconfig.platforms: Add config for Nuvoton MA35 platform Jacky Huang
2023-03-15 7:28 ` [PATCH 02/15] arm64: defconfig: Add Nuvoton MA35 family support Jacky Huang
2023-03-16 14:23 ` Arnd Bergmann
2023-03-17 9:05 ` Jacky Huang
2023-03-15 7:28 ` [PATCH 03/15] mfd: Add the header file of Nuvoton ma35d1 system manager Jacky Huang
2023-03-16 13:30 ` Ilpo Järvinen
2023-03-17 6:51 ` Jacky Huang
2023-03-16 14:44 ` Arnd Bergmann
2023-03-17 9:28 ` Jacky Huang
2023-03-15 7:28 ` [PATCH 04/15] dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller Jacky Huang
2023-03-16 7:31 ` Krzysztof Kozlowski
2023-03-16 13:35 ` Jacky Huang
2023-03-16 14:09 ` Krzysztof Kozlowski
2023-03-15 7:28 ` [PATCH 05/15] dt-bindings: reset: nuvoton: add binding for ma35d1 IP reset control Jacky Huang
2023-03-16 7:31 ` Krzysztof Kozlowski
2023-03-15 7:28 ` [PATCH 06/15] dt-bindings: mfd: syscon: Add nuvoton,ma35d1-sys compatible Jacky Huang
2023-03-16 7:31 ` Krzysztof Kozlowski
2023-03-17 1:03 ` Jacky Huang
2023-03-15 7:28 ` [PATCH 07/15] dt-bindings: arm: Add initial bindings for Nuvoton platform Jacky Huang
2023-03-16 7:33 ` Krzysztof Kozlowski
2023-03-16 14:32 ` Arnd Bergmann
2023-03-18 1:26 ` Jacky Huang
2023-03-15 7:28 ` [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings Jacky Huang
2023-03-15 21:59 ` Stephen Boyd
2023-03-16 3:24 ` Jacky Huang
2023-03-16 7:35 ` Krzysztof Kozlowski
2023-03-17 3:47 ` Jacky Huang
2023-03-17 9:13 ` Krzysztof Kozlowski
2023-03-17 9:52 ` Jacky Huang
2023-03-17 16:03 ` Krzysztof Kozlowski
2023-03-18 2:11 ` Jacky Huang
2023-03-15 7:28 ` [PATCH 09/15] dt-bindings: reset: Document ma35d1 reset " Jacky Huang
2023-03-16 7:37 ` Krzysztof Kozlowski
2023-03-16 7:39 ` Krzysztof Kozlowski
2023-03-18 4:30 ` Jacky Huang
2023-03-19 11:05 ` Krzysztof Kozlowski
2023-03-20 6:26 ` Jacky Huang
2023-03-15 7:28 ` [PATCH 10/15] dt-bindings: serial: Document ma35d1 uart " Jacky Huang
2023-03-16 7:40 ` Krzysztof Kozlowski
2023-03-17 4:18 ` Jacky Huang
2023-03-15 7:28 ` Jacky Huang [this message]
2023-03-16 7:45 ` [PATCH 11/15] arm64: dts: nuvoton: Add initial ma35d1 device tree Krzysztof Kozlowski
2023-03-18 6:07 ` Jacky Huang
2023-03-19 11:06 ` Krzysztof Kozlowski
2023-03-19 14:16 ` Jacky Huang
2023-03-16 14:17 ` Arnd Bergmann
2023-03-16 16:44 ` Lee Jones
2023-03-18 13:32 ` Jacky Huang
2023-03-18 13:17 ` Jacky Huang
2023-03-18 14:04 ` Arnd Bergmann
2023-03-20 15:38 ` Jacky Huang
2023-03-15 7:28 ` [PATCH 12/15] clk: nuvoton: Add clock driver for ma35d1 clock controller Jacky Huang
2023-03-15 22:07 ` kernel test robot
2023-03-15 22:30 ` Stephen Boyd
2023-03-17 3:07 ` Jacky Huang
2023-03-16 7:51 ` Krzysztof Kozlowski
2023-03-19 2:55 ` Jacky Huang
2023-03-16 15:56 ` Ilpo Järvinen
2023-03-19 5:16 ` Jacky Huang
2023-03-20 10:31 ` Ilpo Järvinen
2023-03-21 15:03 ` Jacky Huang
2023-03-15 7:29 ` [PATCH 13/15] reset: Add Nuvoton ma35d1 reset driver support Jacky Huang
2023-03-16 7:51 ` Krzysztof Kozlowski
2023-03-17 7:13 ` Jacky Huang
2023-03-16 15:05 ` Ilpo Järvinen
2023-03-19 13:10 ` Jacky Huang
2023-03-15 7:29 ` [PATCH 14/15] tty: serial: Add Nuvoton ma35d1 serial " Jacky Huang
2023-03-15 7:37 ` Greg KH
2023-03-15 9:40 ` Jacky Huang
2023-03-15 9:48 ` kernel test robot
2023-03-15 10:13 ` Jiri Slaby
2023-03-16 13:28 ` Jacky Huang
2023-03-16 14:54 ` Ilpo Järvinen
2023-03-20 8:23 ` Jacky Huang
2023-03-20 10:04 ` Ilpo Järvinen
2023-03-21 14:23 ` Jacky Huang
2023-03-15 7:29 ` [PATCH 15/15] MAINTAINERS: Add entry for NUVOTON MA35 Jacky Huang
2023-03-16 14:38 ` Arnd Bergmann
2023-03-19 12:01 ` Jacky Huang
2023-03-19 12:36 ` Tomer Maimon
2023-03-16 7:41 ` [PATCH 00/15] Introduce Nuvoton ma35d1 SoC Krzysztof Kozlowski
2023-03-16 14:05 ` Arnd Bergmann
2023-03-17 6:30 ` Jacky Huang
2023-03-17 13:21 ` Arnd Bergmann
2023-03-17 16:06 ` Krzysztof Kozlowski
2023-03-18 3:07 ` Jacky Huang
2023-03-18 9:07 ` Arnd Bergmann
2023-03-18 3:00 ` Jacky Huang
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