From: Vignesh Raghavendra <vigneshr@ti.com>
To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 2/2] arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB
Date: Mon, 20 Mar 2023 10:19:35 +0530 [thread overview]
Message-ID: <20230320044935.2512288-2-vigneshr@ti.com> (raw)
In-Reply-To: <20230320044935.2512288-1-vigneshr@ti.com>
Per AM62Ax SoC datasheet[0] L2 cache is 512KB.
[0] https://www.ti.com/lit/gpn/am62a7 Page 1.
Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
index 9734549851c0..58f1c43edcf8 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
@@ -97,7 +97,7 @@ L2_0: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
- cache-size = <0x40000>;
+ cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
--
2.40.0
next prev parent reply other threads:[~2023-03-20 4:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 4:49 [PATCH 1/2] arm64: dts: ti: k3-am625: " Vignesh Raghavendra
2023-03-20 4:49 ` Vignesh Raghavendra [this message]
2023-03-20 22:49 ` Nishanth Menon
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