From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC65FC76196 for ; Fri, 31 Mar 2023 06:26:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229567AbjCaG0K (ORCPT ); Fri, 31 Mar 2023 02:26:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229823AbjCaG0C (ORCPT ); Fri, 31 Mar 2023 02:26:02 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27812191E6 for ; Thu, 30 Mar 2023 23:25:43 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32V6PTuT100228; Fri, 31 Mar 2023 01:25:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680243929; bh=9h/ntFw0EFUnq0el7i0tjeXB41W/9vSfuU1AW08A8ko=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WPOCJGAQvLAxLltOfCdtJEgQHGkDpDxV9xWewkHzqzRvxDjA4Xgswypj+iN/nTwSx LZbPEkDL1cP7fr/dN3NFnlDFx9kKRyYYnRM0H3Gx1s2COUX6rhKk4Vtj3G/rWRH7va /85cNL0vX8jrN1QjJK37YGC6j43QXU6qbE/wxFJQ= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32V6PTWI074210 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 31 Mar 2023 01:25:29 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 31 Mar 2023 01:25:29 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 31 Mar 2023 01:25:29 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32V6PLvB027504; Fri, 31 Mar 2023 01:25:27 -0500 From: Siddharth Vadapalli To: , , CC: , , , , Subject: [PATCH 2/2] phy: ti: gmii-sel: Enable USXGMII mode for J784S4 Date: Fri, 31 Mar 2023 11:55:21 +0530 Message-ID: <20230331062521.529005-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230331062521.529005-1-s-vadapalli@ti.com> References: <20230331062521.529005-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's SoC data. Signed-off-by: Siddharth Vadapalli --- drivers/phy/ti/phy-gmii-sel.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index fba5c0c0771c..6286cf25a426 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -25,6 +25,7 @@ /* J72xx SoC specific definitions for the CONTROL port */ #define J72XX_GMII_SEL_MODE_SGMII 3 #define J72XX_GMII_SEL_MODE_QSGMII 4 +#define J72XX_GMII_SEL_MODE_USXGMII 5 #define J72XX_GMII_SEL_MODE_QSGMII_SUB 6 #define PHY_GMII_PORT(n) BIT((n) - 1) @@ -114,6 +115,13 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII; break; + case PHY_INTERFACE_MODE_USXGMII: + if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_USXGMII))) + goto unsupported; + else + gmii_sel_mode = J72XX_GMII_SEL_MODE_USXGMII; + break; + default: goto unsupported; } @@ -239,7 +247,8 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | + BIT(PHY_INTERFACE_MODE_USXGMII), .num_ports = 8, .num_qsgmii_main_ports = 2, }; -- 2.25.1