From: Achal Verma <a-verma1@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Krzysztof Wilczy_ski <kw@linux.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Dhananjay Vilasrao Kangude <dkangude@cadence.com>,
Anindita Das <dasa@cadence.com>, Yuan Zhao <yuanzhao@cadence.com>,
Milind Parab <mparab@cadence.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Achal Verma <a-verma1@ti.com>
Subject: [PATCH v12 0/5] PCI: add 4x lane support for pci-j721e controllers
Date: Sat, 1 Apr 2023 16:56:28 +0530 [thread overview]
Message-ID: <20230401112633.2406604-1-a-verma1@ti.com> (raw)
Adding of additional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.
Changes from v1:
* Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause
regressions on 1-2x lane platforms
Changes from v2:
* Correct dev_warn format string from %d to %u since lane count is a
unsigned integer
* Update CC list
Changes from v3:
* Use the max_lanes setting per chip for the mask size required since
bootloader could have set num_lanes to a higher value that the
device tree which would leave in an undefined state
* Reorder patches do the previous change to not break bisect
* Remove line breaking for dev_warn to allow better grepping and since
no strict 80 columns anymore
Changes from v4:
* Correct invalid settings for j7200 PCIe RC + EP
* Add j784s4 configuration for selection of 4x lanes
Changes from v5:
* Dropped 'PCI: j721e: Add warnings on num-lanes misconfiguration' patch
from series
* Reworded 'PCI: j721e: Add per platform maximum lane settings' commit
message
* Added yaml documentation and schema checks for ti,j721e-pci-* lane
checking
Changes from v6:
* Fix wordwrapping in commit messages from ~65 columns to correct 75
columns
* Re-ran get_maintainers.pl to add missing maintainers in CC
Changes from v7:
* Addressed review comments in ti,j721e-pci-ep.yaml and
ti,j721e-pci-host.yaml from v6
* Added warn message if num-lanes property value is invalid.
* Addressed build issue reported in
https://lore.kernel.org/all/202211260346.4JvNnDdc-lkp@intel.com/
Changes from v8:
* Use "const: 1" in ti,j721e-pci-ep.yaml and ti,j721e-pci-host.yaml
when num-lanes min and max values are equal.
Changes from v9:
* Rebase on next-20230315
Changes from v10:
* Rebase on next-20230317
Changes from v12:
* Rebase on next-20230331
Matt Ranostay (5):
dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes
PCI: j721e: Add per platform maximum lane settings
PCI: j721e: Add PCIe 4x lane selection support
dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings
PCI: j721e: add j784s4 PCIe configuration
.../bindings/pci/ti,j721e-pci-ep.yaml | 39 ++++++++++++++--
.../bindings/pci/ti,j721e-pci-host.yaml | 39 ++++++++++++++--
drivers/pci/controller/cadence/pci-j721e.c | 45 ++++++++++++++++---
3 files changed, 112 insertions(+), 11 deletions(-)
--
2.25.1
next reply other threads:[~2023-04-01 11:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-01 11:26 Achal Verma [this message]
2023-04-01 11:26 ` [PATCH v12 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Achal Verma
2023-04-03 9:33 ` Krzysztof Kozlowski
2023-04-01 11:26 ` [PATCH v12 2/5] PCI: j721e: Add per platform maximum lane settings Achal Verma
2023-04-01 11:26 ` [PATCH v12 3/5] PCI: j721e: Add PCIe 4x lane selection support Achal Verma
2023-04-01 11:26 ` [PATCH v12 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Achal Verma
2023-04-01 11:26 ` [PATCH v12 5/5] PCI: j721e: add j784s4 PCIe configuration Achal Verma
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