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[72.137.118.218]) by smtp.gmail.com with ESMTPSA id v6-20020ad45346000000b005e231177992sm2670207qvs.74.2023.04.03.16.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 16:18:06 -0700 (PDT) From: Radu Rendec To: linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Pierre Gondois , Sudeep Holla , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 0/2] arch_topology: Pre-allocate cacheinfo from primary CPU Date: Mon, 3 Apr 2023 19:15:49 -0400 Message-Id: <20230403231551.1090704-1-rrendec@redhat.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU") tries to build the cacheinfo from the primary CPU prior to secondary CPUs boot, if the DT/ACPI description contains cache information. However, if such information is not present, it still reverts to the old behavior, which allocates the cacheinfo memory on each secondary CPU. On RT kernels, this triggers a "BUG: sleeping function called from invalid context" because the allocation is done before preemption is first enabled on the secondary CPU. The solution is to add cache information to DT/ACPI, but at least on arm64 systems this can be avoided by leveraging automatic detection (through the CLIDR_EL1 register), which is already implemented but currently doesn't work on RT kernels for the reason described above. This patch series attempts to enable automatic detection for RT kernels when no DT/ACPI cache information is available, by pre-allocating cacheinfo memory on the primary CPU. The first patch adds an architecture independent infrastructure that allows architecture specific code to take an early guess at the number of cache leaves of the secodary CPUs, while it runs in preemptible context on the primary CPU. At the same time, it gives architecture specific code the opportunity to go back later, while it runs on the secondary CPU, and reallocate the cacheinfo memory if the initial guess proves to be wrong. The second patch leverages the infrastructure implemented in the first patch and enables early cache depth detection for arm64. The patch series is based on an RFC patch that was posted to the linux-arm-kernel mailing list and discussed with a smaller audience: https://lore.kernel.org/all/20230323224242.31142-1-rrendec@redhat.com/ Radu Rendec (2): cacheinfo: Add arch specific early level initializer cacheinfo: Add arm64 early level initializer implementation arch/arm64/kernel/cacheinfo.c | 32 +++++++++++++++----- drivers/base/cacheinfo.c | 57 +++++++++++++++++++++++------------ include/linux/cacheinfo.h | 2 ++ 3 files changed, 64 insertions(+), 27 deletions(-) -- 2.39.2