[PATCH 4/5] dt-bindings: clock: Add binding constants for BLZP1600

[Niko Pasaloukos <nikolaos.pasaloukos@blaize.com>]

Add SCMI clock IDs which are used on Blaize BLZP1600 SoC.

Co-developed-by: James Cowgill <james.cowgill@blaize.com>
Signed-off-by: James Cowgill <james.cowgill@blaize.com>
Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
Co-developed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 .../dt-bindings/clock/blaize,blzp1600-clk.h   | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 include/dt-bindings/clock/blaize,blzp1600-clk.h

diff --git a/include/dt-bindings/clock/blaize,blzp1600-clk.h b/include/dt-bindings/clock/blaize,blzp1600-clk.h
new file mode 100644
index 000000000000..bcc8ff513b28
--- /dev/null
+++ b/include/dt-bindings/clock/blaize,blzp1600-clk.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2022, Blaize, Inc.
+ */
+
+#ifndef DT_BINDING_CLK_BLZP1600_H
+#define DT_BINDING_CLK_BLZP1600_H
+
+/* Simple clock-gates */
+#define BLZP1600_CPU_CLK	0
+#define BLZP1600_CRYPTO_CLK	7
+#define BLZP1600_GSP_CLK	9
+#define BLZP1600_USB_CLK	24
+#define BLZP1600_USB_PHY_CLK	25
+#define BLZP1600_CAN0_CLK	26
+#define BLZP1600_CAN1_CLK	27
+#define BLZP1600_CAN2_CLK	28
+#define BLZP1600_ETH_MAC_CLK	29
+#define BLZP1600_SDIO0_CLK	30
+#define BLZP1600_SDIO1_CLK	31
+#define BLZP1600_SDIO2_CLK	32
+#define BLZP1600_SD_CARD_CLK	34
+#define BLZP1600_CSI0_CTRL_CLK	35
+#define BLZP1600_CSI0_VDMA_CLK	36
+#define BLZP1600_CSI1_CTRL_CLK	37
+#define BLZP1600_CSI1_VDMA_CLK	38
+#define BLZP1600_CSI2_CTRL_CLK	39
+#define BLZP1600_CSI2_VDMA_CLK	40
+#define BLZP1600_CSI3_CTRL_CLK	41
+#define BLZP1600_CSI3_VDMA_CLK	42
+#define BLZP1600_CSID_CTRL_CLK	43
+#define BLZP1600_CSID_VDMA_CLK	44
+#define BLZP1600_DSI_CTRL_CLK	45
+#define BLZP1600_DSI_VDMA_CLK	46
+#define BLZP1600_I2S_CODEC_CLK	48
+#define BLZP1600_DMA_CLK	49
+#define BLZP1600_QSPI_PCLK	50
+#define BLZP1600_QSPI_CLK	51
+#define BLZP1600_I2S_TX_CLK	52
+#define BLZP1600_I2S_RX_CLK	53
+#define BLZP1600_I2C0_CLK	54
+#define BLZP1600_I2C1_CLK	55
+#define BLZP1600_I2C2_CLK	56
+#define BLZP1600_I2C3_CLK	57
+#define BLZP1600_I2C4_CLK	58
+#define BLZP1600_UART0_CLK	59
+#define BLZP1600_UART1_CLK	60
+#define BLZP1600_SPIS_PCLK	61
+#define BLZP1600_SPIS_CLK	62
+#define BLZP1600_TSENSOR_CLK	64
+#define BLZP1600_VIDEO_E_CLK	65
+#define BLZP1600_VIDEO_D_CLK	68
+/* Special clock-gates */
+#define BLZP1600_NIC_CLK	69
+#define BLZP1600_NIC_HALF_CLK	70
+#define BLZP1600_ETH_MAC_M_CLK	71
+#define BLZP1600_I2S_MASTER_CLK	72
+/* Clock sources */
+#define BLZP1600_SRC_XTAL_CLK	100
+#define BLZP1600_SRC_PLL0_CLK	101
+#define BLZP1600_SRC_PLL1_CLK	102
+#define BLZP1600_SRC_PLL2_CLK	103
+#define BLZP1600_SRC_I2S_CLK	104
+#define BLZP1600_SRC_CSID_CLK	105
+#define BLZP1600_SRC_DSI_CLK	106
+
+#endif
-- 
2.25.1