From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35763C77B6C for ; Thu, 6 Apr 2023 18:48:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240514AbjDFSsL (ORCPT ); Thu, 6 Apr 2023 14:48:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240377AbjDFSrv (ORCPT ); Thu, 6 Apr 2023 14:47:51 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C945FB45C for ; Thu, 6 Apr 2023 11:47:30 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id g5-20020a25a485000000b009419f64f6afso39675911ybi.2 for ; Thu, 06 Apr 2023 11:47:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680806846; h=content-transfer-encoding:to:from:subject:references:mime-version :message-id:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=ZVCjXqgbqxvDmKa/w96p1nDNDvVhGvDEgrQKrp9bUXU=; b=DLf+RzjLaxJIRtEVUfjTaB6fI0E9IonGzVz1KZGW3kt01kv0idkIRuQaxkdit/+66Y Hj7/thsF/F1gbhhGVVDmc4bOMUDhvQNNhxODH87noP/wxWui5n9KiGgdXZC4qU4/FX4d CuSIy9ImKtF8txIDYZ4NiZ1zVzOY9JG84GCAB7zFMewmkA04xE0WfKONnivPdRrDsdpn ak+NlQIY42Z21qytmFQcBqyYwNXZLaE+qKveF7RHddumFkbShkdn9baozMz0jJuONElk ugvO0aMZdAO4PWywmtXhK5o6uZhWHWmEe+owBQvYYzS5V8BKV7VtGLvOmqgD0Myer+8T Z/Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680806846; h=content-transfer-encoding:to:from:subject:references:mime-version :message-id:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=ZVCjXqgbqxvDmKa/w96p1nDNDvVhGvDEgrQKrp9bUXU=; b=8PSrsijm/q+Lnmwv4BZ+gflD8eWip1JrbxuUigcIihkfSfvAAaap9kU/C2974/b689 I7S7Ugq84SgyLxOS6OwHLXyXNmG9Y23DxkJJcKQVr5h1yWl6L5fDXtfxV8key+3+paj+ s8hQJrwHbQxvKbCZwWAes0tCA8YePlGR1FZ3w7SF3vMsOSvZ0zDPpXfyvOfU2mwPjG4l yp3y1Nu5jEiGRdN+82GvRKy3gf1wEb3VcovH+6WX4unEMjHO23cgrIqdv1vcbtkcLKcW NNRCDsv2pDmFSoKpp+Xb4KFO9z+jhiGq9JEyTLCshhFMVjl6yZQGNs7qNCXOXPBV1xur hMAA== X-Gm-Message-State: AAQBX9ch1/8E8jApvzsidTZ6syDBEBmOZXzG2qlWltSVKv3LYp5LJsfH TKO+k9mUbrY5tLQzg+c3mZ/Jvn8Tdj7O X-Google-Smtp-Source: AKy350avPDOIJWHZUPgGEk9wFR12CQQnWKHGMGvV9GIyzn2cwS+goUrkZNDtEg6llKu2nLr3shMnjI7QPDhY X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:939d:185a:97bb:59ee]) (user=irogers job=sendgmr) by 2002:a25:6e0a:0:b0:ac9:cb97:bd0e with SMTP id j10-20020a256e0a000000b00ac9cb97bd0emr108432ybc.5.1680806846306; Thu, 06 Apr 2023 11:47:26 -0700 (PDT) Date: Thu, 6 Apr 2023 11:46:38 -0700 In-Reply-To: <20230406184638.2632300-1-irogers@google.com> Message-Id: <20230406184638.2632300-5-irogers@google.com> Mime-Version: 1.0 References: <20230406184638.2632300-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.577.gac1e443424-goog Subject: [PATCH v1 5/5] perf vendor events intel: Update free running tigerlake events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , Kan Liang , Zhengjun Xing , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix the topic, PMU name, event code and umask. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers --- .../arch/x86/tigerlake/uncore-memory.json | 50 +++++++++++++++++++ .../arch/x86/tigerlake/uncore-other.json | 36 ------------- 2 files changed, 50 insertions(+), 36 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.= json diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json b/= tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json new file mode 100644 index 000000000000..bba7b6d04e1d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json @@ -0,0 +1,50 @@ +[ + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "imc_free_running" + }, + { + "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "imc_free_running" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "imc_free_running" + }, + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "imc_free_running" + }, + { + "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "imc_free_running" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "imc_free_running" + } +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json index a5a254327ae9..6e43aaf64e28 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json @@ -93,41 +93,5 @@ "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", "Unit": "CLOCK" - }, - { - "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", - "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", - "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", - "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", - "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", - "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", - "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" } ] --=20 2.40.0.577.gac1e443424-goog