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Mon, 10 Apr 2023 08:57:23 -0700 From: Shanker Donthineni To: Thomas Gleixner , Marc Zyngier CC: Sebastian Andrzej Siewior , Michael Walle , Shanker Donthineni , , Vikram Sethi Subject: [PATCH v3 0/3] Increase the number of IRQ descriptors for SPARSEIRQ Date: Mon, 10 Apr 2023 10:57:18 -0500 Message-ID: <20230410155721.3720991-1-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT070:EE_|SA1PR12MB7104:EE_ X-MS-Office365-Filtering-Correlation-Id: 7de02d9a-0dec-4a40-6b50-08db39dc4953 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: T+b0vJTe3Mlt4iHVr3F9S1Jza2jcRFYoq1e0vOisXR++KO/0dIUYrOSwqjOl9JPQpHA63uscYxAmjmbxipUb9pQXK/B6vsVcdeQZdNzZDzEt5ZYMrNP2TBdXV7YBfF4nhDe5YcollBMz5hluBTLN4UIrdOzFaxAB8Mo9RIOJD4rrcvfF43DHuritDmyaDsHu9taX34qTbeanbTfdxs2/5+pV1egVCfyGbURfuEPILx96x1p+e4DT6W2t7sNOmlzhU64ly7XqMiBMhYrahis+1FuaJxK6BE71lKDt3N3Cfpzv5Jnqu+actPzFo3+nJ76eH2AxUH0p7Z6+Tx1udHqaw6GgfNxEdzu2pwpfRzHTYj6lN1q5c3NAzLUJpsnI49kKukhnj35Eg78Ovnrco94ReuyoOhfalyOs9tww5Ct7dHzwRS3CXzo9+EXCZ1kgVX5n4pDuqKZcCoqbuM3ibxsxY+4ZyFO2BM6n4kE52Ue6sEFV5VWPMROZUwPLd6lSROI/aTdj22m6HqZXY10O1TTQeQ9pR5cXXm2TFsdvamfZC2M2BBVzvbniF37uL9U47YMC4bqq5/93Y1S/yMisyKFQ4wnMa96GZPRvRPp3kpDLkyiNvnoKp4abyP410aUONxLHMoKfeMrJrMUGldFmv4wrWO4zEGE+xs7PrE6eWoeHmgRQ2wMtr4rEHS+OL7BRBiTInzHse959k8+vH/39lH1JAXT0ymQ3AeiDG1AA22OrOTJWvbFqwKgzHJmAg+GMSn5Mo/R9C4x6tVWFqke0tQ12GwMQSq2oM4yO+gCMxiKpbL0= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(396003)(39860400002)(136003)(376002)(451199021)(40470700004)(46966006)(36840700001)(7636003)(5660300002)(356005)(41300700001)(40480700001)(478600001)(107886003)(82310400005)(2616005)(36860700001)(8676002)(8936002)(82740400003)(83380400001)(47076005)(2906002)(336012)(426003)(186003)(40460700003)(1076003)(26005)(86362001)(70206006)(70586007)(4326008)(110136005)(316002)(7696005)(54906003)(36756003)(6666004)(966005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 15:57:28.7443 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7de02d9a-0dec-4a40-6b50-08db39dc4953 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7104 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ARM64 architecture uses SPARSEIRQ with a default value of NR_IRQS, which is set to 64. This means that only 64+8192 IRQ descriptors are allowed, which may not be sufficient for modern ARM64 servers that have a large number of IO devices and GIC hardware that supports direct vSGI and vLPI injection features. This limitation has caused issues when attempting to launch multiple virtual machines with GICv4.1 features, resulting in the error message 'kvm_err("VPE IRQ allocation failure\n")'. The root cause of this issue is the ~8K IRQ descriptor limit. To address this issue, an initial proposal was made to define NR_IRQS to 2^19 for ARM64. However, Marc Zyngier suggested implementing a generic solution instead of hard-coded values. Thomas Gleixner advised to use the maple tree data structure and provided most of the necessary functions. For more information, refer to the discussion thread at https://lore.kernel.org/linux-arm-kernel/20230104023738.1258925-1-sdonthineni@nvidia.com/. This patch series converts the static memory allocation to dynamic using the maple tree, and increases the maximum number of IRQ descriptors to INT_MAX from NR_IRQS+8192. This change has been tested on an ARM64 server with CONFIG_SPARSE_IRQ=y, where 256 virtual machines were launched, creating a total of 128K+ IRQ descriptors, and IRQ injection was verified. Changes in v3: - Edited commit text - Added a helper function irq_resend_init() - Rebased to v6.3-rc6 Changes in v2: - The patches have been updated to v6.3-rc5. - The patches 2/5 and 4/5 have been removed as they are unnecessary. - The review comments from Thomas have been addressed. Shanker Donthineni (3): genirq: Use hlist for managing resend handlers genirq: Encapsulate sparse bitmap handling genirq: Use the maple tree for IRQ descriptors management include/linux/irqdesc.h | 3 ++ kernel/irq/chip.c | 1 + kernel/irq/internals.h | 6 ++-- kernel/irq/irqdesc.c | 76 +++++++++++++++++++++++++---------------- kernel/irq/resend.c | 47 ++++++++++++++++--------- 5 files changed, 85 insertions(+), 48 deletions(-) -- 2.25.1