[PATCH] irqchipi/gic-v4: Ensure accessing the correct RD when and writing INVLPIR

[Kunkun Jiang <jiangkunkun@huawei.com>]

commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual exclusion between
vPE affinity change and RD access") tried to address the race
between the RD accesses and the vPE affinity change, but somehow
forgot to take GICR_INVLPIR into account. Let's take the vpe_lock
before evaluating vpe->col_idx to fix it.

Fixes: f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access")
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Nianyao Tang <tangnianyao@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 586271b8aa39..041f06922587 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3943,13 +3943,17 @@ static void its_vpe_send_inv(struct irq_data *d)
 
 	if (gic_rdists->has_direct_lpi) {
 		void __iomem *rdbase;
+		unsigned long flags;
+		int cpu;
 
 		/* Target the redistributor this VPE is currently known on */
-		raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
-		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
+		cpu = vpe_to_cpuid_lock(vpe, &flags);
+		raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
+		rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
 		gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
 		wait_for_syncr(rdbase);
-		raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
+		raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
+		vpe_to_cpuid_unlock(vpe, flags);
 	} else {
 		its_vpe_send_cmd(vpe, its_send_inv);
 	}
-- 
2.27.0