From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
Mark Brown <broonie@kernel.org>,
Shaoqin Huang <shahuang@redhat.com>
Subject: [PATCH v2 2/7] arm64/sysreg: Convert MDSCR_EL1 to automatic register generation
Date: Tue, 23 May 2023 19:35:59 +0100 [thread overview]
Message-ID: <20230419-arm64-syreg-gen-v2-2-e0064336e2dd@kernel.org> (raw)
In-Reply-To: <20230419-arm64-syreg-gen-v2-0-e0064336e2dd@kernel.org>
Convert MDSCR_EL1 to automatic register generation as per DDI0616 2023-03.
No functional change.
Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3d69bda0e608..95de1aaee0e9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -135,7 +135,6 @@
#define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
-#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
#define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
#define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index df7a7ba97b43..601cc8024734 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -55,6 +55,34 @@ Field 29 TX
Res0 28:0
EndSysreg
+Sysreg MDSCR_EL1 2 0 0 2 2
+Res0 63:36
+Field 35 EHBWE
+Field 34 EnSPM
+Field 33 TTA
+Field 32 EMBWE
+Field 31 TFO
+Field 30 RXfull
+Field 29 TXfull
+Res0 28
+Field 27 RXO
+Field 26 TXU
+Res0 25:24
+Field 23:22 INTdis
+Field 21 TDA
+Res0 20
+Field 19 SC2
+Res0 18:16
+Field 15 MDE
+Field 14 HDE
+Field 13 KDE
+Field 12 TDCC
+Res0 11:7
+Field 6 ERR
+Res0 5:1
+Field 0 SS
+EndSysreg
+
Sysreg ID_PFR0_EL1 3 0 0 1 0
Res0 63:32
UnsignedEnum 31:28 RAS
--
2.30.2
next prev parent reply other threads:[~2023-05-23 18:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 18:35 [PATCH v2 0/7] b4/sysreg: More conversions to automatic generation Mark Brown
2023-05-23 18:35 ` [PATCH v2 1/7] arm64/sysreg: Convert MDCCINT_EL1 to automatic register generation Mark Brown
2023-05-23 18:35 ` Mark Brown [this message]
2023-05-23 18:36 ` [PATCH v2 3/7] arm64/sysreg: Standardise naming of bitfield constants in OSL[AS]R_EL1 Mark Brown
2023-05-23 18:36 ` [PATCH v2 4/7] arm64/sysreg: Convert OSLAR_EL1 to automatic generation Mark Brown
2023-05-23 18:36 [PATCH v2 0/7] arm64/sysreg: More conversions " Mark Brown
2023-05-23 18:37 ` [PATCH v2 2/7] arm64/sysreg: Convert MDSCR_EL1 to automatic register generation Mark Brown
2023-05-25 21:39 ` Oliver Upton
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