From: Mario Limonciello <mario.limonciello@amd.com>
To: <linus.walleij@linaro.org>,
Basavaraj Natikar <Basavaraj.Natikar@amd.com>,
Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Cc: <nakato@nakato.io>, <korneld@chromium.org>,
<richard.gong@amd.com>, <stable@vger.kernel.org>,
Mario Limonciello <mario.limonciello@amd.com>,
<linux-gpio@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 3/4] pinctrl: amd: Detect and mask spurious interrupts
Date: Fri, 21 Apr 2023 07:06:23 -0500 [thread overview]
Message-ID: <20230421120625.3366-4-mario.limonciello@amd.com> (raw)
In-Reply-To: <20230421120625.3366-1-mario.limonciello@amd.com>
From: Kornel Dulęba <korneld@chromium.org>
Leverage gpiochip_line_is_irq to check whether a pin has an irq
associated with it. The previous check ("irq == 0") didn't make much
sense. The irq variable refers to the pinctrl irq, and has nothing do to
with an individual pin.
On some systems, during suspend/resume cycle, the firmware leaves
an interrupt enabled on a pin that is not used by the kernel.
Without this patch that caused an interrupt storm.
Cc: stable@vger.kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315
Signed-off-by: Kornel Dulęba <korneld@chromium.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/pinctrl/pinctrl-amd.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 24465010397b..675c9826b78a 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -660,21 +660,21 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
* We must read the pin register again, in case the
* value was changed while executing
* generic_handle_domain_irq() above.
- * If we didn't find a mapping for the interrupt,
- * disable it in order to avoid a system hang caused
- * by an interrupt storm.
+ * If the line is not an irq, disable it in order to
+ * avoid a system hang caused by an interrupt storm.
*/
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
regval = readl(regs + i);
- if (irq == 0) {
- regval &= ~BIT(INTERRUPT_ENABLE_OFF);
+ if (!gpiochip_line_is_irq(gc, irqnr + i)) {
+ regval &= ~BIT(INTERRUPT_MASK_OFF);
dev_dbg(&gpio_dev->pdev->dev,
"Disabling spurious GPIO IRQ %d\n",
irqnr + i);
+ } else {
+ ret = true;
}
writel(regval, regs + i);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
- ret = true;
}
}
/* did not cause wake on resume context for shared IRQ */
--
2.34.1
next prev parent reply other threads:[~2023-04-21 12:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 12:06 [PATCH 0/4] pinctrl: amd: Adjust handling for firmware misconfigurations Mario Limonciello
2023-04-21 12:06 ` [PATCH 1/4] pinctrl: amd: Detect internal GPIO0 debounce handling Mario Limonciello
2023-04-21 12:06 ` [PATCH 2/4] pinctrl: amd: Fix mistake in handling clearing pins at startup Mario Limonciello
2023-04-21 12:06 ` Mario Limonciello [this message]
2023-04-21 12:06 ` [PATCH 4/4] pinctrl: amd: Revert "pinctrl: amd: disable and mask interrupts on probe" Mario Limonciello
2023-04-28 13:54 ` Limonciello, Mario
2023-05-05 11:43 ` [PATCH 0/4] pinctrl: amd: Adjust handling for firmware misconfigurations Linus Walleij
2023-05-05 12:14 ` Limonciello, Mario
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