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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT089.mail.protection.outlook.com (10.13.176.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.33 via Frontend Transport; Tue, 9 May 2023 11:17:29 +0000 Received: from titanite-d432host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 9 May 2023 06:17:27 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 0/5] iommu/amd: AVIC Interrupt Remapping Improvements Date: Tue, 9 May 2023 07:16:41 -0400 Message-ID: <20230509111646.369661-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT089:EE_|DM4PR12MB6470:EE_ X-MS-Office365-Filtering-Correlation-Id: fab377a5-914a-447e-c1ae-08db507efa19 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2023 11:17:29.4681 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fab377a5-914a-447e-c1ae-08db507efa19 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6470 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For IOMMU AVIC, the IOMMU driver needs to keep track of vcpu scheduling changes, and updates interrupt remapping table entry (IRTE) accordingly. The IRTE is normally cached by the hardware, which requires the IOMMU driver to issue IOMMU IRT invalidation command and wait for completion everytime it updates the table. Enabling IOMMU AVIC on a large scale system with lots of vcpus and VFIO pass-through devices running interrupt-intensive workload, it could result in high IRT invalidation rate. In such case, the overhead from IRT invalidation could outweigh the benefit of IRTE caching. Therefore, introduce a new AMD IOMMU driver option "amd_iommu=irtcachedis" to allow disabling IRTE caching, and avoid the need for IRTE invalidation. Patch 1,2 prepare the AMD IOMMU driver to support IRT cache disabling. Patch 3,4 introduce IRT cache disabling support Patch 5 improves the code path in IOMMU driver for updating vcpu scheduling for AVIC. Thank you, Suravee Joao Martins (1): iommu/amd: Switch amd_iommu_update_ga() to use modify_irte_ga() Suravee Suthikulpanit (4): iommu/amd: Remove the unused struct amd_ir_data.ref iommu/amd: Introduce Disable IRTE Caching Support iommu/amd: Do not Invalidate IRT when disable IRTE caching iommu/amd: Improving Interrupt Remapping Table Invalidation .../admin-guide/kernel-parameters.txt | 1 + drivers/iommu/amd/amd_iommu_types.h | 7 +- drivers/iommu/amd/init.c | 27 +++++- drivers/iommu/amd/iommu.c | 97 ++++++++++--------- 4 files changed, 83 insertions(+), 49 deletions(-) -- 2.31.1