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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>
Cc: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<stefank@nvidia.com>
Subject: [PATCH v2 4/6] dt-bindings: Add bindings to support DRAM MRQ GSCs
Date: Wed, 10 May 2023 14:31:32 +0300	[thread overview]
Message-ID: <20230510113129.4167493-5-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <20230510113129.4167493-1-pdeschrijver@nvidia.com>

Add bindings for DRAM MRQ GSC support.

Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 .../nvidia,tegra264-bpmp-shmem.yaml           | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml

diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
new file mode 100644
index 000000000000..1f9c2dfbf8c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra CPU-NS - BPMP IPC reserved memory
+
+maintainers:
+  - Peter De Schrijver <pdeschrijver@nvidia.com>
+
+description: |
+  Define a memory region used for communication between CPU-NS and BPMP.
+  Typically this node is created by the bootloader as the physical address
+  has to be known to both CPU-NS and BPMP for correct IPC operation.
+  The memory region is defined using a child node under /reserved-memory.
+  The sub-node is named shmem@<address>.
+
+allOf:
+  - $ref: reserved-memory.yaml
+
+properties:
+  compatible:
+    const: nvidia,tegra264-bpmp-shmem
+
+  reg:
+    description: The physical address and size of the shared SDRAM region
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - no-map
+
+examples:
+  - |
+    reserved-memory {
+       dram_cpu_bpmp_mail: shmem@f1be0000  {
+           compatible = "nvidia,tegra264-bpmp-shmem";
+           reg = <0x0 0xf1be0000 0x0 0x2000>;
+           no-map;
+       };
+    };
+...
-- 
2.34.1


  parent reply	other threads:[~2023-05-10 11:37 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-10 11:31 [PATCH v2 0/6] firmware: tegra: Add MRQ support for Tegra264 Peter De Schrijver
2023-05-10 11:31 ` [PATCH v2 1/6] dt-bindings: mailbox: tegra: Document Tegra264 HSP Peter De Schrijver
2023-05-10 13:50   ` Thierry Reding
2023-05-10 11:31 ` [PATCH v2 2/6] mailbox: tegra: add support for Tegra264 Peter De Schrijver
2023-05-10 13:50   ` Thierry Reding
2023-05-10 11:31 ` [PATCH v2 3/6] soc: tegra: fuse: " Peter De Schrijver
2023-05-10 14:35   ` Thierry Reding
2023-05-10 11:31 ` Peter De Schrijver [this message]
2023-05-10 12:47   ` [PATCH v2 4/6] dt-bindings: Add bindings to support DRAM MRQ GSCs Krzysztof Kozlowski
2023-05-10 11:31 ` [PATCH v2 5/6] dt-bindings: memory-region property for tegra186-bpmp Peter De Schrijver
2023-05-10 14:40   ` Thierry Reding
2023-05-10 11:31 ` [PATCH v2 6/6] firmware: tegra: bpmp: Add support for DRAM MRQ GSCs Peter De Schrijver
2023-05-10 14:33   ` Thierry Reding
2023-05-11  8:04     ` Peter De Schrijver
2023-05-10 11:44 ` [PATCH v2 0/6] firmware: tegra: Add MRQ support for Tegra264 Peter De Schrijver

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